INSTITUTO

POLITECNICO NACIONAL ESCUELA SUPERIOR DE INGENIERIA MECANICA Y ELECTRICA UNIDAD ZACATENCO INGENIERIA EN COMUNICACIONES Y ELECTRONICA Guia de Instrucciones del Microcontrolador MSP430G2231 y Modos de Direccionamiento
Alumno: Gonzlez Mondragn Luis Alejandro Grupo: 7CM7 Materia: Microcontroladores Profesor: Edgar Roman Caldern Daz

Indice
Modos de Direccionamiento a) Modo de Registros b) Modo Indexado c) Modo Simbolico d) Modo Absoluto e) Modo de Registros Indirecto f) Modo Indirecto de Registro Autoincrementado g) Modo Inmediato Set de Instrucciones del Microcontrolador MSP430G2231 a) b) c) d) e) Set de Instrucciones Instrucciones de Formato Doble Instrucciones de Formato Simple Instrucciones de Salto Ciclos y Longitudes de las Instrucciones

Mem (0203h) = 0A1h C = 0, Z = 0, N = 1 (Low byte of register) + (Addressed byte) - (Addressed byte)

R5 = 00061h C = 0, Z = 0, N = 0 (Addressed byte) + (Low byte of register) - (Low byte of register, zero to High byte)

Modos de Direccionamiento

3.3

Existen 7 diferentes modos de direccionamiento para el operando de Seven addressing modes for the source operand and four addressing modes for the destination operand fuente y 4 para el de destino que pueden direccionar numbers in Table 3-3 describe the can address the complete address space with no exceptions. The bit el espacio contents of the direccin sin e (destination) mode completo de As (source) and Ad xcepciones. bits.

Addressing Modes

As/Ad 00/0 01/1 01/1 01/1

Table 3-3. Source/Destination Operand Addressing Modes

Addressing Mode Register mode Indexed mode Symbolic mode Absolute mode Syntax Rn X(Rn) ADDR ADDR Description Register contents are operand (Rn + X) points to the operand. X is stored in the next word. (PC + X) points to the operand. X is stored in the next word. Indexed mode X(PC) is used. The word following the instruction contains the absolute address. X is stored in the next word. Indexed mode X(SR) is used. Rn is used as a pointer to the operand. Rn is used as a pointer to the operand. Rn is incremented afterwards by 1 for .B instructions and by 2 for .W instructions. The word following the instruction contains the immediate constant N. Indirect autoincrement mode @PC+ is used.

10/11/11/-

Indirect register mode Indirect autoincrement Immediate mode

@Rn @Rn+ #N

seven addressing modes detail in the following sections. Most of the examples Thesame addressing mode forare explained in destination, but any valid combination of source and show the the source and NOTA: .B o .W explican lis possible inn qinstruction. destination addressing modes a forma e an ue se tratara la instruccin, si es a

nivel de Bit (8 Bits) o a nivel de Palabra (16 Bits)

NOTE:

Use of Labels EDE, TONI, TOM, and LEO Throughout MSP430 documentation EDE, TONI, TOM, and LEO are used as generic labels. They are only labels. They have no special meaning.

a) Modo de Registros (Rn) MOV.W R6 , R7 CPU Copyright MOV.B R5 , R7

Opera con informacin dentro de los registros de la ALU

R6 AA R7 AA FF FF

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R5 02 R6 AA R7 00 0A FF 0A

b) Modo Indexado X(Rn) MOV.W 2(R5) , 4(R4)

2+ 0X020A 2+ 0X020C Dato 4+ 0X0200= 0X0204 R4 02 R5 02 R6 AA R7 00 BH 0X21 BL 0XDC 0X21 0XDC 0A 0x020D 0x020C 0X0205 0X0204 FF 0A 00

Dir de mem Donde esta el dato fuente

0X21DC MOV.B 2(R5) , 4(R4)

2+ 0X020A 2+ 0X020C Dato 4+ 0X0200= 0X0204

R4 02 R5 02 R6 AA R7 00 BH 0X21 BL 0XDC 0XFF 0XDC 0X0205 0X0204 0A 0x020D 0x020C FF 0A 00

Dir de mem Donde esta el dato fuente

0XDC

MOV.W 2(R5) , R4 2+ 0X020A 2+ 0X020C Dato 0X21DC 21

R4 DC R5 02 R6 0A

BH 0X21 BL 0XDC

0x020D 0x020C

MOV.B R6 , 3(R5)
AA 0XAAFF Dato 4+ 0X020A= 0X020D 00

R6 FF R7 0A

BH 0XFF 0XFF BL 0XDC

0x020D 0x020C 0x020B

c) Modo Simbolico EDE=0X201 TONY=0X206 MOV.W TONY , 2(R4)

Dir de mem 0X206 Dato 0X202 0X2000 2 +0X200 R4 02 00

BH 0X20 BL 0X00 0X20 0X00 0x0207 0x0206 0x0205 0x0204 0x0203 0x0202

MOV.B TONY , EDE

Dir de mem 0X206 Dato 0X00 0X201

BH 0X20 BL 0X00 0X00

0x0207 0x0206 0x0205 0x0204 0x0203 0x0202 0X201

d) Modo Absoluto (&) Se usa en Registros de los subsistemas del Microcontrolador MOV.W &TONY , 2(R4) R4
0X206 Dato 2 +0X200= 0x202 02 00

0X2000 MOV.B &TONY , &EDE

0X206 Dato 0x201

0X00

e) Modo de Registro Indirecto @Rn MOV.W @R4 , R7

0X200 Dato

 MOV.B @R5 , 4(R5) 0X20A Dato 0X20 f) Modo Indirecto de Registro Auto-Incrementado @Rn+ MOV.W @R4++2 , R7 0X20A Dato 0X00FF MOV.B @R5++1 , R7 0X207 Dato 0X00 g) Modo Inmediato # MOV.W #0X3575 , 0(R4) MOV.B #0XFF, EDE MOV.W #EDE , R4 EDE=0X201

El set completo del MSP430 consiste en 27 instrucciones de Nucleo y 24 instrucciones emuladas. Hay 3 formatos para las instrucciones de Nucleo: Operando Doble Operando Simple Salto Todas las instrucciones de operando Simple y de Doble Operando pueden ser instrucciones usadas como byte o palabra mediante las extensiones .B o .W. Si no se usa una extensin, la instruccin es una Figure 3-12. Core Instruction Map instruccin de palabra. Table 3-17. MSP430 Instruction Set
Mnemonic ADC(.B) ADD(.B) ADDC(.B) AND(.B) BIC(.B) BIS(.B) BIT(.B) BR
(1) (1)

8xxx Cxxx 1xxx 14xx 18xx 1Cxx 20xx 24xx 28xx 2Cxx 30xx 34xx 38xx 3Cxx 4xxx 5xxx 6xxx 7xxx 8xxx 9xxx Axxx Bxxx Cxxx Dxxx Exxx Fxxx

RRC RRC.B SWPB

RRA

RRA.B

SXT

PUSH

PUSH.B

CALL

RETI

SET DE INSTRUCCIONES JNE/JNZ

JEQ/JZ JNC JC JN JGE JL JMP MOV, MOV.B ADD, ADD.B ADDC, ADDC.B SUBC, SUBC.B SUB, SUB.B CMP, CMP.B DADD, DADD.B BIT, BIT.B BIC, BIC.B BIS, BIS.B XOR, XOR.B AND, AND.B

Description Add C to destination Add source to destination Add source and C to destination AND source and destination Clear bits in destination Set bits in destination Test bits in destination Branch to destination Call destination Clear destination Clear C Clear N Clear Z dst + C src + dst dst dst dst dst dst dst

V * * * 0 0 PC * dst (decimally) dst (decimally) * * V *

N * * * * * 0 * * * N *

Z * * * * * 0 * * * *Z

C * * * * * 0 * * * *C

dst src,dst src,dst src,dst src,dst src,dst src,dst dst dst

src + dst + C src .and. dst src .or. dst src .and. dst dst PC+2 0 0 0 0 dst C N Z PC not.src .and. dst

CALL CLR(.B) CLRC CLRN

(1) (1) (1)

stack, dst

dst

CLRZ (1) www.ti.com CMP(.B) DADC(.B)

(1)

src,dst dst

Compare source and destination Add C decimally to destination

dst - src dst + C

Instruction Set

DADD(.B) src,dst (1) Mnemonic DEC(.B) dst

Add source and C decimally to dst src + dst + C Description - 1 Decrement destination dst dst

Table 3-17. MSP430 Instruction Set (continued)

dst - 2 0 1 GIE GIE dst

DECD(.B)
(1)

(1)

dst

Double-decrement destination Disable interrupts Enable interrupts Increment destination Invert destination Jump if C set/Jump if higher or same Jump if equal/Jump if Z set Jump if greater or equal Jump if less Jump Jump if N set Jump if C not set/Jump if lower Jump if not equal/Jump if Z not set Move source to destination No operation Pop item from stack to destination Push source onto stack Return from subroutine Return from interrupt

* -

* -

* -

* -

DINT (1) Emulated Instruction

(1) (1)

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EINT (1) CPU INC(.B) INV(.B) JC/JHS JEQ/JZ JGE JL JMP JN JNC/JLO JNE/JNZ MOV(.B) NOP
(2)

dst dst dst label label label label label label label label src,dst

dst +1 .not.dst

SLAU144H December 2004 Revised April 2011 dst * * * * Submit Documentation Feedback * * * * * * * * * * * * * * * * * * * * dst

INCD(.B)

Copyright 2004 2011, Texas Double-increment destination Instruments Incorporated dst+2 dst

(1)

PC + 2

offset

PC

src @SP SP - 2 @SP

dst dst, SP+2 SP, src PC, SP + 2 SP @SP SP

* * * 0

PUSH(.B) RET
POP(.B)
(2)

(2)

dst src

RETI RLA(.B) RLC(.B) RRA(.B)

(2) (2)

dst dst dst

Rotate left arithmetically Rotate left through C Rotate right arithmetically

JN JNC/JLO JNE/JNZ MOV(.B)

label label label src,dst

(2)

Jump if N set Jump if C not set/Jump if lower Jump if not equal/Jump if Z not set Move source to destination No operation Pop item from stack to destination Push source onto stack Return from subroutine Return from interrupt src @SP SP - 2 @SP dst dst, SP+2 SP, src PC, SP + 2 SP @SP SP

* * * 0 * dst + 0FFFFh + C 1 1 1 C N C dst dst dst * * * 0 dst + 0FFFFh + 1 src .xor. dst dst 0 *

* * * * * * 1 * * * * *

* * * * * * 1 * * * * *

* * * * * * 1 * * * 1 *

NOP

(2)

POP(.B) RET
(2)

dst src

PUSH(.B) RETI RLA(.B) RLC(.B) RRA(.B) RRC(.B) SBC(.B) SETC SETN SETZ
(2) (2) (2) (2) (2) (2)

dst dst dst dst dst

Rotate left arithmetically Rotate left through C Rotate right arithmetically Rotate right through C Subtract not(C) from destination Set C Set N Set Z

SUB(.B) SUBC(.B) SWPB SXT TST(.B) XOR(.B)

(2) (2)

src,dst src,dst dst dst dst src,dst

Subtract source from destination Subtract source and not(C) from dst Swap bytes Extend sign Test destination Exclusive OR source and destination

dst + .not.src + 1 dst + .not.src + C

Emulated Instruction

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Instruction Set

3.4.1 Double-Operand (Format I) Instructions

Figure 3-9 illustrates the double-operand instruction format.
15

Instrucciones de Formato Doble

14 13 12 11 10 S-Reg 9 8 7 Ad Op-code

6 B/W

5 As

2 D-Reg

En el siguiente listado se pueden apreciar las instrucciones que gozan Table 3-11 lists and describes the double operand instructions. de este formato. Table 3-11. Double Operand Instructions
Mnemonic MOV(.B) ADD(.B) ADDC(.B) SUB(.B) SUBC(.B) CMP(.B) DADD(.B) BIT(.B) BIC(.B) BIS(.B) XOR(.B) AND(.B) S-Reg, D-Reg src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst src,dst Operation src dst dst dst dst dst Status Bits V * * * * * dst (decimally) * 0 dst * 0 N * * * * * * * * * Z * * * * * * * * * C * * * * * * * * *

Figure 3-9. Double Operand Instruction Format

src + dst

src + dst + C

dst + .not.src + 1 dst + .not.src + C dst - src src + dst + C src .and. dst not.src .and. dst src .or. dst src .xor. dst src .and. dst dst dst dst

* The status bit is affected The status bit is not affected 0 The status bit is de algunas instrucciones de Doble formato usando Ejemplos de el uso cleared 1 The status algunos modos bite Direccionamiento previamente vistos: d is set NOTE: Instructions CMP and MOV.B #0X00, &P2SEL SUB The instructions CMP and MOV.W #DATOS, R5 AND SUB are identical except for the storage of the result. The same is true for the BIT and instructions. MOV.B @R5+,&PIOUT MOV.W #49998,R4 MOV.B &P2IN,R5 CMP.B #0XC0,R5 BIC.B #BIT6 + BIT7,&P2DIR BIS.B #0XFF, &P1DIR AND.B #0XC0,R5 SLAU144H December 2004 Revised April 2011 CPU Submit Documentation Feedback Copyright 2004 2011, Texas Instruments Incorporated

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3.4.2 Single-Operand (Format II) Instructions

Figure 3-10 illustrates the single-operand instruction format.
15

Instrucciones de Formato Simple Op-code

14

13

12

11

10

6 B/W

5 Ad

D/S-Reg

Ahora tenemos las Instrucciones de Formato Simple en la siguiente Table 3-12 lists and describes the single operand instructions. Tabla:

Mnemonic RRC(.B) RRA(.B) PUSH(.B) SWPB CALL RETI SXT dst S-Reg, D-Reg dst dst src dst dst

Figure 3-10. Single Operand Instruction Format

Table 3-12. Single Operand Instructions

Operation C MSB SP 2 MSB .......LSB ....LSB C C Status Bits V * 0 @SP SP SP 0 * * * * N * * * Z * * * C * * *

MSB

SP, src

@SP

Swap bytes SP dst TOS TOS Bit 7 2 PC SR, SP + 2 PC,SP + 2 SP, PC+2

Bit 8........Bit 15

* 0

The status bit is affected The status bit is not affected The status bit is cleared Algunos The status bitde las Instrucciones de Formato Simple: ejemplos is set 1

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All addressing modes are possible for the CALL instruction. If the symbolic mode (ADDRESS), the immediate mode (#N), the absolute mode ( EDE) or the indexed mode x(RN) is used, the word that follows contains the address information. CALL #TIEMP0 CALL #0AA04h CALL R5 MOVE.B &EDE,R5 SXT R5 ADD R5,R7 MOV #1234h,&EDE SWPB &EDE CPU SLAU144H December 2004 Revised April 2011 Submit Documentation Feedback Copyright 2004 2011, Texas Instruments Incorporated

Figure 3-11 shows the conditional-jump instruction format.

15 14 Op-code 13 12 11 C 10 9 8 7 6 5 4 3 2 1

Table 3-13 lists and describes the jump instructions

Mnemonic JEQ/JZ JNE/JNZ JC JNC JN JGE JL JMP Label Label Label Label Label Label Label Label

Instrucciones de Salto 3-11. Jump Instruction Format Figure

10-Bit PC Offset

Ahora podemos apreciar las Instrucciones de Salto en la siguiente Tabla:

Table 3-13. Jump Instructions
Operation Jump to label if zero bit is set Jump to label if zero bit is reset Jump to label if carry bit is set Jump to label if carry bit is reset Jump to label if negative bit is set Jump to label if (N .XOR. V) = 0 Jump to label if (N .XOR. V) = 1 Jump to label unconditionally S-Reg, D-Reg

Conditional jumps support program branching relative to the PC and do not affect the status bits. The possible jump range is from 511 to +512 words relative to the PC value at the jump instruction. The 10-bit Algunos ejemplos de lis utilizacin de estas Instrucciones dentro de un added to the progr program-counter offset a treated as a signed 10-bit value that is doubled and counter: programa:

PCnew = PCold + 2 + PCoffset

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JMP APAGADO JNE ENCENDER JEQ INICIO JNZ TIEMPO

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addressing modes used - not the instruction itself. The number of clock cycles refers to the MCLK. 3.4.4.1 Interrupt and Reset Cycles

Table 3-14 lists the CPU cycles for interrupt overhead and reset.

Ciclos y Longitudes de las Instrucciones Table 3-14. Interrupt and Reset Cycles Action No. of Cycles Length of Instruction
Return from interrupt (RETI) 5 1

Interrupt ciclos El numero de accepted de reloj del CPU requeridos 6por una Instruccin WDT reset 4 depende del formato de la instruccin y de los modos de Reset (RST/NMI) 4 direccionamiento usados, no de la misma Instruccin. El numero -de ciclos de reloj se refiere al MCLK. 3.4.4.2 Format-II (Single Operand) Instruction Cycles and Lengths Table 3-15 lists the length Ciclos y Longitudes de land ICPU cycles for alldaddressing modes of format-II instructions. as nstrucciones e Formato Simple: Table 3-15. Format-II Instruction Cycles and Lengths No. of Cycles Addressing Mode Rn @Rn @Rn+ #N X(Rn) EDE EDE RRA, RRC SWPB, SXT 1 3 3 (See note) 4 4 4 PUSH 3 4 5 4 5 5 5 CALL 4 4 5 5 5 5 5 Length of Instruction 1 1 1 2 2 2 2 Example

SWPB R5 RRC @R9 SWPB @R10+ CALL #0F000h CALL 2(R7) PUSH EDE SXT &EDE

NOTE: Instruction Format Salto requieren Todas las instrucciones de II Immediate Mode un cdigo de palabra, y Do not e CPU para ejecutarse, and importar si el salto s in the destination toman 2 ciclos duse instruction RRA, RRC, SWPB, sin SXT with the immediate modee hace o field. Use of these in the immediate mode results in an unpredictable program operation. no. 3.4.4.3 Format-III (Jump) Instruction Cycles and Lengths All jump instructions require one code word, and take two CPU cycles to execute, regardless of whether the jump is taken or not. 62 CPU SLAU144H December 2004 Revised April 2011 Submit Documentation Feedback Copyright 2004 2011, Texas Instruments Incorporated

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Instruction Set

3.4.4.4

Format-I (Double Operand) Instruction Cycles and Lengths Table 3-16 lists the length Ciclos y Longitudes and las Icycles for all addressing ormato Doble: de CPU nstrucciones de Fmodes of format-I instructions. Table 3-16. Format 1 Instruction Cycles and Lengths
Addressing Mode Src Rn Rm PC x(Rm) EDE EDE @Rn Rm PC x(Rm) EDE EDE @Rn+ Rm PC x(Rm) EDE EDE #N Rm PC x(Rm) EDE EDE x(Rn) Rm PC TONI x(Rm) TONI EDE Rm PC TONI x(Rm) TONI EDE Rm PC TONI x(Rm) TONI Dst No. of Cycles 1 2 4 4 4 2 2 5 5 5 2 3 5 5 5 2 3 5 5 5 3 3 6 6 6 3 3 6 6 6 3 3 6 6 6 Length of Instruction 1 1 2 2 2 1 1 2 2 2 1 1 2 2 2 2 2 3 3 3 2 2 3 3 3 2 2 3 3 3 2 2 3 3 3 Example

MOV BR ADD XOR MOV AND BR XOR MOV XOR ADD BR XOR MOV MOV MOV BR MOV ADD ADD MOV BR MOV ADD MOV AND BR CMP MOV MOV MOV BRA MOV MOV MOV

R5,R8 R9 R5,4(R6) R8,EDE R5,&EDE @R4,R5 @R8 @R5,8(R6) @R5,EDE @R5,&EDE @R5+,R6 @R9+ @R5,8(R6) @R9+,EDE @R9+,&EDE #20,R9 #2AEh #0300h,0(SP) #33,EDE #33,&EDE 2(R5),R7 2(R6) 4(R7),TONI 4(R4),6(R9) 2(R4),&TONI EDE,R6 EDE EDE,TONI EDE,0(SP) EDE,&TONI &EDE,R8 &EDE &EDE,TONI &EDE,0(SP) &EDE,&TONI

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