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  • G Tomorrrow Verilog Xilinx Alu Brown Alu Alu HTML Fit S

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    Registers Used 0 / 36 (0%) PIN RESOURCES Function Block Inputs Used 32 / 108 (30%) Signal Type Input Output Bidirectional GCK GTS GSR Pin Type I / O GCK / IO GSR / IO Global clock net(s) used Total macrocells in high performance mode (MCHP) macrocells in low power mode (MCLP) Total macrocells used (MC) back to top 0 15 15 print page 1 of 1

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    G Tomorrrow Verilog Xilinx Alu Brown Alu Alu HTML Fit s

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    Registers Used 0 / 36 (0%) PIN RESOURCES Function Block Inputs Used 32 / 108 (30%) Signal Type Input Output Bidirectional GCK GTS GSR Pin Type I / O GCK / IO GSR / IO Global clock net(s) used Total macrocells in high performance mode (MCHP) macrocells in low power mode (MCLP) Total macrocells used (MC) back to top 0 15 15 print page 1 of 1

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    8 Ansichten1 Seite

    G Tomorrrow Verilog Xilinx Alu Brown Alu Alu HTML Fit S

    Hochgeladen von

    message4guru
    Registers Used 0 / 36 (0%) PIN RESOURCES Function Block Inputs Used 32 / 108 (30%) Signal Type Input Output Bidirectional GCK GTS GSR Pin Type I / O GCK / IO GSR / IO Global clock net(s) used Total macrocells in high performance mode (MCHP) macrocells in low power mode (MCLP) Total macrocells used (MC) back to top 0 15 15 print page 1 of 1

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    Summary
    Design Name Fitting Status Software Version Device Used Date alu Successful J.36 XA9536XL-15-VQ44 10-29-2011, 8:59PM
    RESOURCES SUMMARY

    Macrocells Used 15/36 (42%)

    Pterms Used 66/180 (37%)

    Registers Used 0/36 (0%)


    PIN RESOURCES

    Pins Used 15/34 (45%)

    Function Block Inputs Used 32/108 (30%)

    Signal Type Input Output Bidirectional GCK GTS GSR

    Required 11 4 0 0 0 0

    Mapped 11 4 0 0 0 0

    Pin Type I/O GCK/IO GTS/IO GSR/IO

    Used 13 1 0 1

    Total 28 3 2 1

    GLOBAL RESOURCES

    Global clock net(s) used Global output enable net(s) used Global set/rest net(s) used

    0 0 0
    POWER DATA

    Macrocells in high performance mode (MCHP) Macrocells in low power mode (MCLP) Total macrocells used (MC)
    back to top

    0 15 15
    print page

    file://G:\tomorrrow\verilog\Xilinx\alu_brown\alu\alu_html\fit\summary.htm

    29-Oct-2011

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