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Discovery Visual Environment User Guide

Version B-2008.12 December 2008

Comments? E-mail your comments about this manual to: vcs_support@synopsys.com.

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1
Getting Started
This chapter describes getting started using DVE. It covers the following topics: General Requirements on page 2 Enabling Debugging on page 2 Invoking DVE on page 4 Running a Simulation from the Command Line on page 8 Running a Simulation from the GUI on page 10 Saving a Session or Layout on page 16 Loading a Saved Session on page 18 Closing a Database on page 19 Exiting DVE on page 19

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General Requirements
You must use the same version of VCS and DVE to ensure problemfree debugging of your simulation. There are three ways to check the DVE version: Enter the dve -v command line option. Enter gui_get_version on the DVE command line. Use the Help > About menu option.

Enabling Debugging
This section describes how to enable debugging options for your simulation. Note: If you run DVE in a directory where you dont have file write privileges, DVE will be unable to write log files. In this case, you will get a warning message that says DVE is unable to write files.

Compile-Time Options
-debug_pp Enables r/w access and callbacks to design nets, and enables memory callback and assertion debug.

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In addition, -debug_pp enables VCS DKI and VPI routine usage. The debug_pp is ideally suited for using DVE in post processing mode. You can also run interactive simulation when the design is compiled with the debug_pp option, but certain capabilities like breakpoints and force will not be enabled. -debug Provides force net and reg capabilities in addition to all capabilities of debug_pp. This option is best suited for interactive simulation. -debug_all Instruments all design capabilities in the design, and consequently adds significant compile time overhead. This option enables all capabilities as debug and also enables setting breakpoints and stepping through the code. This option is recommended only for interactive simulations where breakpoint and line-stepping capabilities are essential.

Required Files
DVE requires the following input files to enable its debug functionality: VPD file - VPD files are platform-independent, versioned files into which you can dump selected signals during simulation. DVE gets hierarchy, value change, and some assertion information from these files. Basic debugging can be achieved in post process using just a VPD file.

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However, VPD files are not guaranteed to contain the entire design hierarchy because you can selectively choose subsets of the design to be dumped to the VPD file. For all DVE functionality to be available while debugging, it is imperative that the VCS version used to generate the VPD and the DVE version used to view the VPD are identical. OVA library - DVE uses this library for advanced assertion debugging. This library is produced when a design contains OVA/ SVA/PSL assertions and the correct VCS compile options are used. The library is platform dependent. Coverage databases - In DVE, you specify one of three types of coverage databases to display coverage information. If other coverage databases for different types of coverage exist, DVE automatically opens them as well. You can select either of the following two kinds of databases: - A code coverage directory (by default named simv.cm by VCS and VCS MX. - An OpenVera or SystemVerilog assertions database directory (by default named simv.vdb by VCS).

Invoking DVE
This section describes how to invoke DVE.

Informational
dve -help

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Displays DVE basic commands. dve -v | -V Displays version information.

64-bit Platform Support


-full64 To use the -full64 option, you must download and install the 32-bit and 64-bit VCS binaries. By default, DVE is invoked in 32bit mode. You can use the -full64 option to invoke DVE in 64bit mode. If only 32-bit VCS binaries are installed, DVE can be invoked only in 32-bit. If only 64-bit VCS binaries are installed, DVE can be invoked only in 64-bit, and use of -full64 option is redundant. To activate 64-bit support enter:
dve -full64

Post Process
dve Brings up an empty DVE top level window with no arguments. DVE usage can be post-processing or interactive mode from this point. dve -vpd filename Opens up DVE, reads VPD file given on the command line, and opens the top level scope for that design.

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dve -vpd test.vpd -session mysession.vpd Brings up DVE with the VPD file test.vpd and applies settings from the session file mysession.tcl.

Interactive
dve -nogui The DVE GUI is not displayed; instead UCLI mode is invoked and the simulator is not attached. To start the simulator, enter "start <simv or executable name>" at the UCLI prompt. simv -ucli Runs VCS/ VCS MX for UCLI debugging. The DVE GUI is not displayed. simv -gui Opens DVE with the simv simulator attached at time 0. vcs -gui -R Same as above but invoked at compile time. dve -toolexe name -toolargs simulator args Starts DVE, connects to a simulator called name and runs it with the arguments specified in simulator args.

Scripts
dve -cmd "cmd"

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Starts DVE and executes the Tcl command enclosed in quotation marks. Multiple commands separated by semi-colons are allowed. dve -script name Starts DVE and reads in a Tcl script specified by name. dve -session name Starts DVE and reads in a session file. If the -session and -script options are combined, the session is read first and then the script.

DVE's Log Files.


DVE produces the following two log files in the DVEfiles directory, which is located in the current working directory. These logs are useful to give to Synopsys in the event of problems. dve_gui.log contains all input and output that goes to the console log. dve_history.log contains all commands that occur during the lifetime of a debug session. This is useful for capturing scripts for replay.

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Running a Simulation from the Command Line


DVE with VCS, SystemVerilog, and NTB (OV and SV)
To run DVE, you must enable it at compile time. You can use the -debug, -debug_all, or -debug_pp argument to enable DVE, or set DVE as the default command line interface. To run DVE with VCS, enter VCS commands with DVE-enabling command line options:
vcs (-debug | -debug_all | -debug_pp) [-sverilog] [-ntb] [VCS_options] design.v [testbench_files] simv -gui [runtime_options]

VCS MX and VHDL Pure VHDL


To run a VHDL simulation with DVE, enter the VCS MX commands with options enabling DVE:
vhdlan design.vhd vcs cfg_tb (-debug | -debug_all) simv -gui [runtime_options]

Mixed Simulation with Verilog on Top


To run a mixed Verilog/VHDL simulation with Verilog on top, enter the commands with options enabling DVE:
vlogan Verilog_files [options] vhdlan vhdl_filename -vlib Verilog

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vcs (-debug | -debug_all) [options] design.v simv -gui [runtime_options]

Mixed Simulation with VHDL on Top


To run a mixed Verilog/VHDL simulation with VHDL on top, enter the commands with DVE enabling options:
vlogan Verilog_files [options] vhdlan vhdl_filename -vlib Verilog vcs cfg_tb (-debug | -debug_all) -verilogcomp "options" simv -gui -verilogrun "-q" [options]

Methodology for Checkpoint Restore


When saving and restoring a simulation, use the same technology or flow to restore that you used to save the checkpoint, for example: Save using UCLI commands and restore using UCLI commands Save in DVE and restore in DVE Save using SCL commands and restore using SCL commands Save using CLI commands and restore using CLI commands

Do not mix the technologies for saving and restoring, for example: Save using UCLI commands and restore using SCL commands Save in DVE and restore with UCLI commands Save using UCLI commands and restore using DVE Save using CLI commands and restore using UCLI commands

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Also, if you are running an external application that communicates with VCS MX using the VHPI or PLI, and if there are files opened for this application, you must close these files before you save and open them again after you restore.

Running a Simulation from the GUI


You can open DVE and start the simulation from the gui.

Post-processing
You can load and display any number of VPD files for postprocessing. To open a database in DVE 1. Select File > Open Database. The Open Database dialog box appears. 2. Browse and select the name of the VPD file you want to load. 3. Enter or accept a Designator for your design. 4. Enter a time range to load. The default is start of simulation to the end. 5. Click Open. DVE loads the selected VPD file.

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Setting Up and Starting an Interactive Session


In addition to loading VPD files for post-processing, you can also setup and run a simulation interactively in real-time using a compiled Verilog, VHDL, or mixed design. 1. From the command line, open DVE. %dve 2. Select Simulator > Setup, then select Start the simulation from the Simulator Setup dialog box.

3. Browse to a simulator executable. 4. Enter simulator arguments. 5. Set the name of the VPD file or select an existing file that will be written during this interactive session.

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6. Click OK. The simulation is set.

Running the Simulation


This section describes using DVE to run and control the simulation. The following topics are covered: Using the Toolbar Using Simulator Menu Commands Using the Command Line

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Using the Toolbar


When you start the simulation, DVE activates toolbar commands for running and controlling the simulation. Click the following icons in the simulator toolbar to control the simulation.
Icon Description Runs the simulation until a breakpoint is hit, the simulation finishes, or for the duration specified in the Set Continue Time dialog box or toolbar time entries. Runs the simulation for the specified time, then stops.

Start/Continue

Continue for Specified Time


When the simulation is running, this icon is activated. Click to stop the simulation.

Stop
For VHDL, Verilog, and TB code, next steps over tasks and functions.

Next

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Icon

Description Moves the simulation forward by stepping one line of code, irrespective of the language of the code. This is the same as the UCLI Step command.

Step In
Steps to the next executable line in the current active thread.

Step In Active Thread


For Native TestBench (NTB), OpenVera, and SystemVerilog testbenches, stops at the next executable line in the testbench.

Step In Any Testbench Thread


Steps to the next executable line outside of the current function or a task.

Step Out
Stops the currently running simulation and restarts it with the current simulation setup. This retains all open windows and GUI setups.

Restart

Using Simulator Menu Commands


After you start the simulation, you can use menu commands to run and control the simulation. Select the following commands to control the simulation.
Command Start/Continue Description Runs the simulation until a breakpoint is hit, the simulation finishes, or for the duration specified in the Set Continue Time dialog box or toolbar time entries. Stops a running simulation (same as the UCLI stop command).

Stop

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Command Step

Description Moves the simulation forward by stepping one line of code, irrespective of the language of the code. This is the same as the UCLI Step command. For VHDL, Verilog, and TB code, next steps over tasks and functions. Stops at the next executable line in the current active thread. For Native TestBench (NTB) OpenVera and SystemVerilog testbenches, stops at the next executable line in the testbench. Steps to the next executable line outside of the current function or a task. Stops the currently running simulation and restarts it with the current simulation setup. This retains all open windows and GUI setups. The simulation will be started if not already running.

Next Step In Active Thread Step In Testbench

Step Out Restart

Using the Command Line


Use the command line at the bottom of the DVE top level window to enter DVE and Unified Command Line Interface (UCLI) commands to run and control your simulation. Figure 1-2 shows the command line where you enter commands with the results displayed in the Log tab above the command line. Figure 1-1 Command Line with the Log tab

To view DVE commands, enter

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help -gui

For more information about using UCLI, see the Unified Command Language User Guide. For a quick view of the UCLI commands and their use, at the DVE command prompt, enter
help -ucli [argument]

When entered without an argument, a list of UCLI commands and a short description is displayed. Enter a command name as the argument, and a description and command syntax are displayed. The UCLI commands and definitions are displayed.

Saving a Session or Layout


You preserve session data display layout, and VPD path options using the Save Sessions dialog box. To save a session 1. Select File > Save Session.

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The Save Session dialog box appears.

2. Enter a file name for the session. 3. Select on option to specify the session type to save: - All session data including layout, wavelists, database, and simulation state. - Only window layout to save the arrangement of windows, views, and panes for later reuse. This option will not save any data contents. - All signals in all groups to save the signal list for all signal groups. - For a Wave or List view, Only signal list for view save the signal list. After opening any required simulator or VPD files, the signal list can be used to reload a window with the current signal list. 4. Select a path option for the VPD:

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- Save full (absolute) path for opened VPDs (default). - Save relative path for opened VPD (relative to the directory where the session file is stored). - Do not save opened VPD. If multiple designs are opened, this option is disabled. 5. Select saved content: - Only window layout. - All signals in all groups. - For a Wave or List view, only signal list for view. 6. Click Save.

Loading a Saved Session


To load a saved session 1. Load a VPD file. 2. Select File > Load Session. The Load Session dialog box appears. 3. Browse to the session and select it from the list of saved session TCL files. 4. Click Load. The session is loaded.

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Closing a Database
To close a currently open database 1. Select File > Close Database. The Close Database dialog box appears. 2. Make sure the correct database is selected, then click OK. DVE closes the display of the selected database in the Hierarchy pane.

Exiting DVE
To exit DVE, select File > Exit.

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2
Using the Graphical User Interface 2
This chapter describes the basics of using the DVE graphical user interface and management of the windows. It contains the following sections: Overview of DVE Window Configuration on page 1 DVE Panes on page 4 Managing DVE Views on page 4 Setting Display Preferences on page 10

Overview of DVE Window Configuration


DVE has a completely flexible window model. This model is based on the concept of the TopLevel window.

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A TopLevel window contains a frame, menus, toolbars, status bar, and pane targets. Any number of TopLevel windows are possible. The default at startup is one. A DVE TopLevel window is a frame for displaying design and debug data. The default DVE window configuration is to display the TopLevel window with the Hierarchy Browser on the left, the Console pane at bottom, and the Source view occupying the remaining space. You can change the default using the preference file, the session file or a startup script. Figure 2-1 shows the default TopLevel window. You can create a file '.synopsys_dve_usersetup.tcl' in your home directory for storing short cuts. Example
gui_set_hotkey -menu "Signal->Compare..." -hot_key "c"

The file '.synopsys_dve_prefs.tcl' stores the user preferences. This is created by the tool.

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Figure 2-1

DVE Top Level Frame Initial View


Menu Bar Source view Toolbar

Hierarchy Browser

Data Pane

Command Line

Status Bar

Target View Control

Console Tabs Console

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DVE Panes
A TopLevel window is a frame that displays panes and views. A pane can be displayed one time on each TopLevel window and serves a specific debug purpose. Examples of panes are Hierarchy, Data, and the Console panes. A view can have multiple instances per TopLevel window. Examples of views are Source, Wave, List, Memory, and Schematic. Panes can be docked on any side to a TopLevel window or left floating in the area in the frame not occupied by docked panes (called the workspace).

Managing DVE Views


DVE TopLevel window can contain any number of DVE views and panes. You can choose to display data in one or many DVE windows and panes by setting defaults, using the status bar window controls, or docking and undocking windows as you work.

Managing Target Views


The target policy dictates where panes will be created. On each TopLevel at the bottom right corner of the frame are target icons (Figure 2-2). These icons represent pane types.

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Figure 2-2

View targeting icons


Check marks indicate targeted windows are attached to the current window.

No check in targeted Wave view icon

Target icons can have the following two states: Targeted Icon has a dart in it, which means an action that requires a new pane creates that pane in the current frame. Untargeted icon has no dart in it, which means an action that requires a new pane creates a new TopLevel window that contains that pane.

To open a pane in a new TopLevel window 1. Click the icon in the status bar to remove the check mark.
Targets a new Source pane in a new TopLevel window.

Source
Targets a new Schematic view pane in a new TopLevel window.

Schematic
Targets a new Path Schematic pane in a new TopLevel window.

Path Schematic

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Targets a new Wave pane in a new TopLevel window.

Wave
Targets a List pane in a new TopLevel window.

List
Targets a new Memory pane in a new TopLevel window.

Memory 2. Click a corresponding window icon in the toolbar to open a window of that type. It will not be attached to the current window and will open in a new TopLevel window.

Docking and Undocking Views and Panes


You can use the Windows menu to dock and undock windows and panes. Select Windows > Dock in New Row, then select the row position in which to dock the currently active window. Select Windows > Dock in New Column, then select the column position in which to dock the currently active window. Select Undock to detach the currently active window or pane.

To delete a window, click the X icon in the corner of the pane. This is the same for all dockable windows.

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Dark blue color of dock handle (dock handle is the train track that connects to the X icon) indicates that this docked window is active. This is the same for all dockable windows. An action must occur such as a click to make the window active.

Dragging and Dropping Docked windows


Left-click on the dock handle and drag and drop the window to a new dock location or to a non docked window. Right-clicking on dock handle brings up a small popup menu:
Undock Dock Undocks the active window. Left Docks the selected window to the left wall of the TopLevel window. Right Docks the selected window to the right wall of the TopLevel window. Top Docks the selected window to the top wall of the TopLevel window. Not recommended. Bottom Docks the selected window to the bottom wall of the TopLevel window.

Using the Menu Bar and Toolbar


The menu bar and toolbar allows you to perform standard simulation analysis tasks, such as opening and closing a database, moving the waveform to display different simulation times, or viewing HDL source code. Most items in the menu bar correspond to icons or text fields in the toolbar. For example, you can set the simulation time display in the waveform by doing either of the following:

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Select View > Go To Time, then enter a value in the Go To Time dialog box, and click Apply or OK. Enter a value in the Time text field on the toolbar, then press Enter on your keyboard.

See Figure 2-3 for an example.

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Figure 2-3

Methods for Setting the Simulation Time


OR Toolbar: Enter value in Time text field of the toolbar, then press the Enter key.

Menu Bar:

Select View > Go To Time, enter a value in the Go To Time dialog box, then click Apply or OK.

Results: Waveform display moves to specified simulation time.

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Note: For complete descriptions of all menu bar and toolbar functions, see Menu Bar Reference and Toolbar Reference . For complete descriptions of setting the simulation time and using the Waveform window, see, Using the Waveform Pane on page 14.

Setting Display Preferences


You can set preferences to customize the display of DVE windows and panes. To customize the display 1. In the TopLevel window, select Edit > Preferences.

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The Application Preferences dialog box displays the Global Settings category.

2. Select settings as follows: - Global Settings Select settings to set the font and font sizes to display in DVE windows. You can specify multiple database options by selecting whether to ignore case or delimiter when matching signals and scopes. The default is to log only UCLI commands. To also log GUI commands, select the Log GUI commands in Console window checkbox. You can specify the maximum number of log lines.

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- Debug Settings Select signal compare parameters, value transition, and assertion window docking defaults, and first frame target setup options. - Hierarchy Browser Sets the appearance and initial filter states. - Data Pane Sets the appearance parameters, signal sorting, signal levels to display, and scroll bar conditions. - Source view Specifies data and annotation loading options, line wrap, line number display, tab width, default editor, and automatic reload of changed source code. - Source colors subcategory Specifies colors to display Source view components by clicking the drop-down arrows and clicking on a color. - Schematic view Sets line colors for schematic objects in Schematic and Path Schematic views. - Schematic Value Annotations subcategory Sets the Port/Pin visibility and color. - Waveform window Sets appearance parameters and display settings for signal levels, marker values, and waveform values. - Waveform Styles subcategory Selects the waveform display styles for data types. - List view Specifies grid display, signal name truncation, signal levels to display, and column spacing settings. 3. Click OK to save your selections and close the dialog box, Save to save your settings and keep the dialog box open, or Reset to return the default settings.

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3
Using the Hierarchy and Data Panes 3
This chapter describes how to use the DVE Hierarchy and Data panes to show the static design structure in a tree view, navigate the design to view results in other DVE windows and panes, and display signal data. It contains the following sections: The Hierarchy Pane on page 3-1 The Data Pane on page 3-16

The Hierarchy Pane


The Hierarchy pane, shown in Figure 3-1, is composed of two drop-down lists on top of a tree view. The drop-down list on the left is the design selection list. It contains a list of currently open designs with the current design at the top.

Using the Hierarchy and Data Panes 3-1

The drop-down list on the right is for filtering object types. The tree view is made up of two columns: Hierarchy and Type. - The Hierarchy column shows the static instance tree. The names in the instance tree are in the instance name (definition name) format. Top modules (or scopes) are at the top-level of the tree. - The type column displays the type of hierarchical object.

Using the Hierarchy and Data Panes 3-2

Figure 3-1

Hierarchy Pane
Click to select from opened designs Filter option list

Current design

Scopes Object type Object definition name (in parentheses)

Click to expand or collapse hierarchy

Scope Types and Icons


DVE displays a wide variety of scope types in the Hierarchy pane.
Using the Hierarchy and Data Panes 3-3

Each scope type is represented by a specific icon. The following table provides an overview of the various scope types and their corresponding icons:
Scope Type Design Root Verilog Module Icon Description The top of the design hierarchy. Expand the Design Root to see the design. Denotes an instance of a Verilog module. Verilog instances are listed as instance name (module name). Denotes a Verilog task. Denotes a Verilog task. Denotes a named begin. Denotes a named fork. Denotes an assertion unit. In hierarchy, an assertion unit is listed below the instance to which it is bound. Assertions are listed as instance name (unit name). Denotes an instance of a VHDL entity that was simulated in cycle mode. VHDL instances are listed as instance name (Entity:Architecture). Denotes an instance of a VHDL Entity that was simulated in event mode. VHDL instances are listed as instance name (Entity:Architecture). Denotes a VHDL package. Denotes a VHDL procedure. Denotes a VHDL function. Denotes a VHDL process. Denotes a VHDL block.

Verilog Task Verilog Function Verilog Named Begin Verilog Named Fork Assertion Unit

VHDL Cycle Instance

VHDL Event Instance

VHDL Package VHDL Procedure VHDL Function VHDL Process VHDL Block

Using the Hierarchy and Data Panes 3-4

Scope Type VHDL Generic SystemC Instance SystemC Process

Icon

Description Denotes a VHDL generic Denotes an instance of a SystemC entity. Denotes a SystemC process.

Navigating Open Designs


In DVE, more than one design can be open, but only one of them can be active at any point of time. This design is the "current design". Designs are given designator strings, so that in cases where objects from more than one design are allowed (for example, in the Wave view), it is possible to relate object names to their designs. By default, the designators are V1, V2, V3, and so on. For example, if a design A contains an object called top.a and design B also contains an object called top.a, these objects would be shown as V1:top.a and V2:top.a by default. You can also choose your own design designators from the Open Database dialog box.

Using the Hierarchy and Data Panes 3-5

Figure 3-2

Navigating Among Multiple Designs


Click the arrow to display a list of loaded designs. Select a design to display.

Filtering the Hierarchy Display by Object Type


Use the drop-down list at the top right of the Hierarchy pane to filter the scopes in the Hierarchy view by object type. Currently supported object types are: Tasks, Functions, Named Blocks, Packages, Processes, and Unnamed Processes. To filter the data in the Hierarchy pane 1. Open DVE and load the database. The database is displayed in the Hierarchy pane.

Using the Hierarchy and Data Panes 3-6

2. In the Hierarchy pane, click the down arrow to display the type filtering pulldown of the list and select and deselect the object types. For example, in Figure 3-3 the Packages checkbox is cleared. Figure 3-3 Navigating Among Multiple Designs
Click the arrow and deselect Packages. The Hierarchy pane no longer displays the package type.

The packages are removed from the Hierarchy pane. 3. To see them again, select the Packages checkbox.
Using the Hierarchy and Data Panes 3-7

Expanding and Collapsing the Hierarchy Tree


For any scope, if the scope has one or more subscopes a "+" (plus) sign appears to the left of the scope. Left-click on the plus sign to display all the subscopes and turn the "+" sign to a "-" (minus) sign. Figure 3-4 Expanding the Hierarchy Tree

Click to expand Hierarchy tree expands

Left-clicking the minus sign causes the expanded child scopes to collapse. Note that all levels of expanded scopes beneath the scope that was clicked will collapse.

Using the Hierarchy and Data Panes 3-8

Rearranging Hierarchy Information


You can sort the hierarchy column or rearrange the order in which the column headings appear in the Hierarchy pane.

Using the Hierarchy and Data Panes 3-9

Figure 3-5

Moving a Column Heading


Drag the heading to new location and release mouse button.

Click and hold down your mouse on the column heading you want to move.

The column heading moves to new location.

Click the triangle to reverse the sort order of the column.

Populating Other Views and Panes


Use the Hierarchy pane to view data in other DVE windows and panes.

Using the Hierarchy and Data Panes 3-10

Displaying Variables in the Data Pane


Single-clicking on a hierarchy object selects it. Selecting a hierarchy object automatically displays that objects variables in the data pane. You can drag and drop a selected object into any other DVE pane or window that will accept it (such as the Source view, the Wave view, and the List view).

Dragging and Dropping Scopes


A selected object can be dragged and dropped into any other DVE pane or window that will accept it. You can do the following scope dragging operations: Dropping a scope into the Source view displays the definition of that object in the Source view and selects the definition line. Dropping a scope into the Data Pane causes the scope to be selected in the Hierarchy pane and displays the scope variables in the Data pane. If the scope is already selected in the Hierarchy pane, dropping it in the Data pane has no effect because the variables of the scope selected in the Hierarchy pane are automatically displayed in the Data pane. Dropping a scope into the Wave view adds all the scopes signals to a new group or puts them under the insertion bar of the wave signal list. Dropping a scope into the Schematic view displays the design schematic for that scope. Dropping a scope into the Path Schematic view has no useful results.
Using the Hierarchy and Data Panes 3-11

Dropping a scope into the Memory view is not allowed. Dropping a scope from elsewhere into the Hierarchy pane window selects that scope, if it is available. If you drag a scope into the Hierarchy pane but the object has not yet been loaded into the Hierarchy pane, use the Edit > Search For Signal/Scopes menu option. Dropping a scope into a text area, such as the DVE command line drops the full hierarchical text. The exception to this is dropping a scope in the Find Dialog text entry area (either dialog or toolbar area). In this special case, just the leaf string is dropped. For example, dropping "top.c.b.a" results in just "a" in the Find text area. If you select more than one hierarchy object (you can do this with Ctrl-Left Click), the object closest to the linear top of the list is dropped. For example:
top top.a top.a.b top.b top.b.b

In this example, if you select, drag and drop both top.a.b and top.b into a text area, DVE drops only top.a.b. Double-clicking on a Hierarchy object causes the object's definition to be displayed and highlighted in the Source view (based on the reuse policy of the Source view).

Using the Hierarchy and Data Panes 3-12

Using Context Sensitive Menus


In any DVE window, right-click to display the context-sensitive menu, and then select a command. The Hierarchy pane context sensitive menu is as follows:
Command Copy Show Source Show Schematic Show Path Schematic Description Copies the selected text. Displays source code in the Source view for the selected scope; same as double clicking.. Displays the design schematic of the selected object in a new window. Displays the path schematic of the selected object in a new window. Note: This will just show the scopes ports. Adds all the scope's variables to the Wave view (opens one if none currently opened). Adds all the scope's variables to the List view (opens one if none currently opened.) Allows expansion of multiple levels with a single action. Expands the entire hierarchy at once. There may be a delay getting the hierarchy from the simulation when working interactively. Collapses the selected scope. Collapses all expanded scopes. Allows you to select more than one level at a time. Selects all levels that are visible (does not implicitly expand). Opens the Dump Values dialog box for specifying dump parameters. Appends signals and scopes or objects to the current dump file.

Add to Waves Add to Lists Expand By Levels Expand All

Collapse Parent Collapse All Select by Levels Select All Add Dump Dump

Using the Hierarchy and Data Panes 3-13

Dumping Signal Values


There are two ways you can specify scope and signals values to save: Select signals in the hierarchy pane of the Top Level Window or the tree view of the Wave or List view, then select Simulator > Dump or right-click in the Hierarchy pane and select Dump. Specify scopes and signals in the Dump Values dialog box. Dump Values dialog box

Figure 3-6

To dump signal values 1. Select Simulator > Add Dump or right-click in the Hierarchy Pane and select Add Dump. The Dump Values window opens. 2. Select the Scope/Signal that are to be dumped. 3. Select the Depth field to specify the level in the hierarchy for which the objects are to be dumped. 4. Select Aggregates to dump all complex data types.

Using the Hierarchy and Data Panes 3-14

5. Select Add to Waves to add the scopes and signals to the Wave view. 6. Click Dump the save the specified objects.

Forcing Signal Values


You can force a value onto a signal or variable by specifying force criteria in the Force Values dialog box. Figure 3-7 Force Values dialog box.

To force signal values 1. Select Simulator > Add Force. The Add Force dialog box opens.

Using the Hierarchy and Data Panes 3-15

2. In the Signal/Variable field, specify signal/variable whose value is to be forced. 3. In the Table, specify a timed sequence of values by a set of valuetime pairs. - The unit of time in time expressions is optional and defaults to the time precision of the tool. - The @ sign is optional and indicates that the following time expression is relative to the beginning of the simulation. If it is omitted, the time expression is considered as relative to the current simulation time 4. Click Add or Delete to add or delete the rows in the table. 5. Use Repeat period to specify a repeat delay, after which the sequence of forced values have to be restarted. 6. Use the Cancel force section to specify a cancelation time for the force command. 7. Click OK to apply your force specification and close the dialog box, Apply to apply your force specification and have the dialog box remain open, or Cancel to close and not apply the specification.

The Data Pane


DVE displays simulation analysis data corresponding to the contents of the scope you select in the Hierarchy pane.

Using the Hierarchy and Data Panes 3-16

To select a scope in the Hierarchy pane Click on the scope name to select the scope and populate the Data pane. Double-click anywhere on the name of the scope to select the scope and populate the Data pane and the Source view.

Viewing Values
To view the values of an object of the scope selected in the Data pane at the current simulation time, click the arrow object in the Data pane. next to the

Using the Hierarchy and Data Panes 3-17

Figure 3-8

The Data pane. Click to display value.

Rearranging the Data Pane Display


You can sort the signal column or rearrange the order in which the column headings appear.

Using the Hierarchy and Data Panes 3-18

Figure 3-9

Sorting in the Data Pane

Click the triangle to reverse the sort order of the hierarchy column.

Filtering Signal Data


Filter signal data in the Data pane using the scope list at the top right of the pane. To filter the data 1. Left-click the down arrow to display the type filtering pulldown menu. 2. Select signals to filter and display.

Using the Hierarchy and Data Panes 3-19

Figure 3-10 Filtering signals

The signals are filtered per your selection.

Viewing Signal Source Code


To view source code for a signal in the Data pane, select a signal in the Data pane, then select Source > Show Source. The Source view displays the source code for the selected signal. See Figure 3-11 for an illustration of the process.

Using the Hierarchy and Data Panes 3-20

Figure 3-11

Display of Data for a Scope


The Data Pane displays signals in the selected scope.

Select a scope in the Hierarchy pane to populate the Data Pane.

Select a signal in the Data pane. Select Source > Show Source.

The Source view displays the source code for the signal.

Using the Hierarchy and Data Panes 3-21

Using the Hierarchy and Data Panes 3-22

4
Using Source Views 4
The Source view displays the HDL, any foreign language (C, C++, SystemC or OV) or assertion source code of your design. You can open as many Source views as you need to perform your analysis by choosing Window > New > View > Source View. You can also set the number of Source views that DVE should display in the TopLevel window. This section covers the following topics: Loading Source Code on page 4-2 Using the Mouse in the Source view on page 4-6 Working with the Source Code on page 4-7 Navigating the Design from the Source view on page 4-10 Navigating Code in Interactive Simulation on page 4-12

Using Source Views 4-1

Managing Breakpoints in Interactive Simulation on page 4-13 Annotating Values on page 4-25

Loading Source Code


This section covers the following topics Loading a Source view from the Hierarchy Browser Loading a Source view from the Assertion View Displaying Source Code from a File

Loading a Source view from the Hierarchy Browser


To load HDL data into a Source view or from the Hierarchy Browser 1. Make sure a database is currently loaded in the Hierarchy Browser. 2. In the Hierarchy Browser, do either of the following: - Select a scope, then select Scope > Show Source. - Select a scope, right-click and then select Show Source. - Double-click on a scope icon. - Drag and drop scope from Hierarchy pane to Source View. The Source view loads the data corresponding to the selected scope. See Figure 4-1.

Using Source Views 4-2

Figure 4-1

Loading the Source view

Double-click a scope in the Hierarchy Browser

Corresponding data loads into the Source view

Loading a Source view from the Assertion View


To load assertion code into a Source view via the Assertion view 1. Make sure the Assertion view is loaded with data.

Using Source Views 4-3

If your design contains assertions, the Assertion view loads results when you open the simulation database. 2. Do one of the following: - Select an assertion in either tab, then select Scope > Show Source. - In the Assertion Failure Summary tab or the Assertions tab, double-click the variable or assertion you want to display in the Source view. - In the Assertion Failure Summary tab or the Assertion tab, drag and drop the item to the Source view. - Select File > Open File, then select an assertion file.
DVE loads and displays the source file.

Using Source Views 4-4

Figure 4-2

Displaying Assertion Source Code

Double-click an assertion in the assertion window

or

Select the assertion file in the Open Source File dialog box

The assertion source displays in the Source view

Using Source Views 4-5

Displaying Source Code from a File


You can open a source file in the existing Source view or you can open new window by following these steps: 1. Select File > Open File The Open Source File dialog box appears. 2. Select the name of the HDL file you want to display from the browser, and then click Open.
DVE loads and displays the selected HDL source file.

Using the Mouse in the Source view


The table below describes mouse action in the Source view.
Mouse Action Left-click Drag-left Click on the line number Command Operations Deselects the current selection and select a signal or an instance. Selects area for multiple selection. Selects the whole line.

Double-click on a signal name Traces the signal's drivers. Double-click on an instance Pushes down into the instance's definition module.

Using Source Views 4-6

Double-click on a module name Double-click on an architecture Double-click on an entity (After double-clicking on an architecture) Right-click on a signal name or anywhere in the Source view Position the mouse cursor on any signal name.

Displays the upper hierarchy and locate the module's instantiation. Jumps to the entity definition of selected enity_name or jump to instance definition of the entity. Jumps to the architecture that was double-clicked previously. Displays a context-sensitive menu or Source view menu. Displays tool tip with the current value.

Working with the Source Code


This section describes how to use the Source view to examine the source code while debugging it. It allows you to expand and collapse required portions of the code, display line attributes for specific lines, and edit the source code using a text editor. The following topics are covered: Expanding and Collapsing Source Code View Editing Source Code Selecting and Copying Text to the Clipboard Displaying Line Attributes

Using Source Views 4-7

Expanding and Collapsing Source Code View


To expand or collapse the source code view 1. Click in the Line Attribute area, or right-click and select Expand Source to view code that is folded. 2. Click in the Line Attribute area, or right-click and select Collapse Source to hide code.

Editing Source Code


To edit source code 1. Choose the text editor by setting the $EDITOR environment variable to set your default text editor.
%>setenv EDITOR vi [OR]

2. Select Edit > Preferences, then select Source view and choose the editor you want and save from the editor pulldown menu. 3. In the source code area, right-click and select 'Edit Source' or 'Edit Parent' to open the source code in default editor and edit the same.

Selecting and Copying Text to the Clipboard


You can select some or all text displayed in a Source view, and copy it to your clipboard. To select a portion of text in a Source view, drag your mouse across the text you want to select.

Using Source Views 4-8

DVE highlights the selected text.

Figure 4-3

Selecting a portion of text

To select all text or copy text in a Source view 1. Select the text in the Source view. 2. Right-click and hold down the right mouse button in a Source view. A context-sensitive menu (CSM) appears. 3. Select Copy. Figure 4-4 Selecting and copying text

Displaying Line Attributes


Use the line attribute area to toggle line numbering and control line breakpoints when running interactive simulation.

Using Source Views 4-9

Toggle Line Numbering.


Right-click in the line attribute area, then select Line Number to toggle line numbering. Figure 4-5 shows the line attribute menu. Figure 4-5 Source view Line Attributes

Line at which simulator is currently stopped

Line breakpoint enabled

Line breakpoint disabled

Navigating the Design from the Source view


Use the Source view to navigate through the design and view results in other DVE windows by dragging and dropping signals, scopes, and objects into other windows or right-clicking and selecting a menu command as shown below.

Using Source Views 4-10

Figure 4-6

Source view context-sensitive menu

Right-click in code area to display Source view menu options.

To navigate from the Source view 1. Select an object in the Source view and right-click to display the context-sensitive menu or drag your mouse across the text you want to select or double-click on a token (word).
DVE highlights the selected text.

Using Source Views 4-11

2. Select a window from the context-sensitive menu or left-click, drag the code into the right pane of a DVE window, then release the mouse button to drop the code into the window. The selected code displays graphically.
Drag and drop selected code to a DVE window (Wave view is shown).

Navigating Code in Interactive Simulation


When you run a simulation interactively, the line where the simulation stopped is marked by a yellow arrow in the Source view. However, you can search and review any code in the design during a pause in the simulation. You can return to the line where the simulation paused by clicking the yellow arrow at the bottom of the Source view as shown in the following figure.

Using Source Views 4-12

Figure 4-7

Navigating an interactive simulation

Simulation stopped at line 67.

Click to return to line where simulation paused.

Breakpoint enabled

Managing Breakpoints in Interactive Simulation


DVE allows setting breakpoints that cause the tool to stop when stepping or running during interactive simulation: Line breakpoints execute each time a specified line is reached during simulation (see the section Displaying Line Attributes and Managing Breakpoints from the dialog box for more information) about line breakpoints. You can also specify an instance to have the tool stop only at the line in the specified instance. Time breakpoints stop at a specified absolute or relative time in the simulation. Signal breakpoints trigger when a specified signal rises, falls, or changes. Assertion breakpoints stop at a specified assertion event. Task/Function breakpoints stop at the specified task or function.

Using Source Views 4-13

Controlling Line Breakpoints from the Source view


You can control line breakpoints in the Source view attribute area using your mouse. To set a breakpoint 1. Left-click in the attributes area of the Source view next to an executable line. A solid red circle displays to indicate a line breakpoint is set. Note: A line breakpoint can only be set on an executable line. If a line is not executable, no breakpoint will be set when you right-click next to it. 2. Right-click in the attributes area of the Source view, then select Set Breakpoint from the context-sensitive menu. A solid red circle displays to indicate a line breakpoint is set. 3. To disable a line breakpoint, left-click the solid red breakpoint circle. The circle is no longer solid, indicating the breakpoint is disabled. 4. Right-click on an enabled or disabled breakpoint, then select Disable Breakpoint or Enable Breakppoint, Delete Breakpoint, or Delect All Breakpoints. You can also delete all breakpoints from anywhere in the attribute area.

Using Source Views 4-14

The following table describes the breakpoint icons and ways to control them:
Breakpoint Icon Description Action

Enabled Breakpoint

Denotes a line breakpoint was set Click the red circle to disable on this line, and it is enabled. Line the line breakpoint. stepping and simulators will stop on execution of this line.

Denotes a line breakpoint was set Click on the red circle to on this line, and it is disabled. Line delete it. stepping and simulators will not Disabled Breakpoint stop on execution of this line.

Creating Conditional Breakpoints from Source View


You can quickly create condtional Line, Time, Signal, and Task/ Function breakpoints from the source window. To set a breakpoint 1. Left-click in the attributes area of the Source view next to an executable line. A solid red circle displays to indicate a line breakpoint is set. Note: A line breakpoint can only be set on an executable line. If a line is not executable, no breakpoint will be set when you right-click next to it. 2. On the red circle, right-click and select Properties from the menu. The Breakpoints dialog box appears. 3. Enter the condition in the Condition field. 4. Click Update.
Using Source Views 4-15

The breakpoint is set to stop simulation on the condition.

Managing Breakpoints
You can manage all types of breakpoints in an interactive simulation from the Breakpoints dialog box.

Line Breakpoints
To create a line breakpoint 1. Right-click in the Source view line attribute area or pull down the Simulator menu, then select Set Breakpoints. The Breakpoints dialog box appears.

Using Source Views 4-16

Figure 4-8

Creating Breakpoints

2. With the Line tab selected, enter the file name, or browse to the file where you want to create the breakpoint. 3. Enter the line number for the breakpoint. 4. Enter the instance where the breakpoint will fire. 5. If you want the breakpoint to fire only once, select Once for the Frequency, otherwise select Repeat. 6. You can optionally enter a condition for VHDL objects to be met for the breakpoint to fire. Note that condition is not supported for Verilog objects. 7. Click Create. The breakpoint is created and appears in the breakpoint list box.

Using Source Views 4-17

Time Breakpoint
To create a time breakpoint 1. Right-click in the Source view line attribute area or pull down the Simulator menu, then select Breakpoints. The Breakpoints dialog box appears. 2. Click Define to display the breakpoint creation tabs. 3. Select the Time tab. 4. Select Absolute or Relative time reference, then enter the time at which to set the breakpoint. Figure 4-9 Breakpoint dialog box Time tab

5. (Optional) Enter a condition for VHDL objects to be met for the breakpoint to fire.
Using Source Views 4-18

Note that condition is not supported for Verilog objects. 6. Click Create. The breakpoint is created and appears in the breakpoint list box.

Signal Breakpoint
To create a signal breakpoint 1. Right-click in the Source view line attribute area or pull down the Simulator menu, then select Breakpoints. The Breakpoints dialog box appears. 2. Click Define to display the breakpoint creation tabs. 3. Select the Signal tab. 4. Enter the desired signal in the Break on signal text.

Using Source Views 4-19

Figure 4-10 Breakpoint dialog box Signal tab

5. Select Any, Rising, or Falling Edge to define the breakpoint event. 6. Specify the Frequency. 7. (Optional) Enter a condition for VHDL objects to be met for the breakpoint to fire. Note that condition is not supported for Verilog objects. 8. Click Create. The breakpoint is created and appears in the breakpoint list box.

Using Source Views 4-20

Assertion Breakpoint
To create an assertion breakpoint 1. Right-click in the Source view line attribute area or pull down the Simulator menu, then select Breakpoints to display the Breakpoints dialog box. 2. Click Define to display the breakpoint creation tabs. 3. Select the Assertion tab. 4. Enter the full path to the Assert in the Break on Assertion text field. Figure 4-11 Breakpoint dialog box Assertion tab

5. Select an event type to trigger the breakpoint from any, start, end, failure, or success.

Using Source Views 4-21

6. Click Create. The breakpoint is created and appears in the breakpoint list box.

Task/Function Breakpoint
To create a Task/Function breakpoint 1. Right-click in the Source view line attribute area or pull down the Simulator menu, then select Breakpoints. The Breakpoints dialog box appears. 2. Click Define to display the breakpoint creation tabs. 3. Select the Task/Function tab. 4. Enter the full path to the task or function in the Break in Task/ Function field.

Using Source Views 4-22

Figure 4-12 Breakpoint dialog box Assertion tab

You can optionally enter a condition for VHDL objects to be met for the breakpoint to fire. Note that condition is not supported for Verilog objects. 5. Select the Frequency by choosing Once or Repeat. 6. Click Create. The breakpoint is created and appears in the breakpoint list box.

Using Source Views 4-23

Edit Breakpoints
To edit a breakpoint 1. In the Source view line attribute area or from the Simulator menu, right-click and select Set Breakpoints to display the Breakpoints dialog box. Figure 4-13 Breakpoints dialog box

2. To work with defined breakpoints, do one of the following: - To enable or disable a breakpoint, select or clear the Enable box or select the breakpoint in the list and click Enable All or Disable All. - To delete a breakpoint, select the breakpoint in the list and click or click Delete All to delete all breakpoints. - To view the source code of a breakpoint, click .

Using Source Views 4-24

Annotating Values
To enable value annotation for variables/signals in the Source view

1. Click the Annotate Values Icon 2. Select Scope > Annotate Values.

in the tool bar.

3. In the Source view, right-click and select Annotate Values. The annotated values are shown in the Source view. Figure 4-14 Values annotated in the Source view

Using Source Views 4-25

Using Source Views 4-26

5
Using Wave Views 5
The Wave view displays waveforms for signals, traced assertions, and signal comparison. You can also create notations of times of interest using named markers or cursors. This chapter covers the following topics: Viewing Waveform Information on page 5-2 Using the Signal Pane on page 5-7 Using User-Defined Radices on page 5-11 Using the Waveform Pane on page 5-13 Printing Waveforms on page 5-37

For information about using the Wave view to view and debug assertions, see Working with Assertions and Cover Properties.

Using Wave Views 5-1

Viewing Waveform Information


To view waveform information in the Wave view, you need to set the target window, and choose the waveform you want to view. You can customize the way DVE displays the waveform by changing the settings in the Wave view.

Set the Target View


The default setting is to open a waveform in a new TopLevel window. You can accept the default or use the target window controls in the status bar to display a waveform in the current TopLevel window. The target window controls toggle new TopLevel window creation as follows: Untargeted (default) When the Waves icon has no dart in it, as shown in Figure 5-1, an action that requires a new pane creates a new TopLevel window that contains that pane Target window controls

Figure 5-1

Targeted When the icon has a dart in it, an action that requires a new Wave pane, creates that pane in the current TopLevel window frame. If you open a waveform in the current TopLevel window, you can change the display to a TopLevel window by selecting Windows > Undock from the menubar.

Using Wave Views 5-2

Viewing a Waveform
To view waveform information for signals in the Wave view 1. Select a scope or object of interest from the Hierarchy Browser, Variable pane, Source view, List view, Schematic view, or Assertion window, then click the Add to Waves icon in the toolbar . 2. Add the selected signals to the new waveform window or to the recently used waveform window. Just clicking on this icon will add signals to the recently used waveform window. 3. Right-click the scope in the Hierarchy Browser and Variable pane, and select Add to Waves from the context-sensitive menu. Figure 5-2 shows the Wave view with signal information.

Using Wave Views 5-3

Figure 5-2

The Waveform View

Signal Pane Waveform Pane

Setting Wave view Preferences


Use the Application Preferences dialog box to customize signal, marker, and wave display. To set Wave view preferences 1. Select Edit > Preferences. The Application Preferences dialog box displays. 2. In the Categories pane, select Waveform View.

Using Wave Views 5-4

Figure 5-3

Wave Application Preferences dialog box

3. Set preferences as follows: - Show grid Show signal name by level, and justify text preferences for the signal pane. These settings are similar to data pane preferences. - Seek next can advance simulation Valid for interactive simulation only. Controls whether or not searching (seek) for a value or edge with the Seek Next functionality advances the simulation to complete the requested seek. - Show marker values Markers can show 1, 2, or 3 values, This preference controls which values (can be any combination or all) are displayed. Absolute The time the marker is set at.

Using Wave Views 5-5

Adjacent The time between the marker than the next closest marker on either side. Relative Time to the reference marker (usually C1) as shown below.

- Analog values change within one pixel - Chooses number of values to plot. Rough plot can speed up performance. Plot All Values can be slower. Rough plot Smooths plot value display. Plot All Values Displays all values. This option can be slower. - Label Assertion attempts with start time Chooses when to annotate assertion attempt waveform (up arrow) with the time the assertion started. This is useful to see start and end time in one location but in the case of short duration assertions can add clutter to the waveform display. Failures only Annotates failures. Always Shows start and end time of all assertions. Never Does not annotate assertions. 4. Click Apply to view your changes and keep the dialog box open, or click OK to apply your changes and close the dialog box. 5. Click Reset to reapply the defaults.

Using Wave Views 5-6

Using the Signal Pane


The Signal pane displays signals in groups: Scalar signals have their value displayed in binary radix. Vector signals have their values displayed in hexadecimal radix. Integers, real numbers, and times are displayed in the floating point radix.

The components of the Signal pane are as follows: The header allows filtering of signals displayed in the Waves View. The Name column displays signal names The Value column displays the value of signals at the simulation time selected by the C1 cursor (which is also the value in the Top Level Window Time field).

See Figure 5-3 for an example of the Signal pane.

Using Wave Views 5-7

Figure 5-4

The Signal Pane


Click to signals filter

Name of signal group

Click + expand

to

Expanding Verilog Vectors, Integers, Time and Real Numbers


Vector signals can be expanded to their individual bits by clicking the plus icon to the left of the signal name. After you expand the display, each bit is added to the Signal Pane and waveforms for these bits are added to the Wave view. DVE represents integers in 32 bits, so you can expand an integer in the Signal pane to display separate waveforms for each of these bits. Similarly, DVE represents the time data type with 64 bits, and you can expand a time to display a waveform for each of these 64 bits. You cannot expand a real data type.

Using Wave Views 5-8

Assertions can also be expanded. Upon expanding an assertion, its children will include the assertion clock and the signals and events (or sequences and properties for SVA) that make up the assertion.

Renaming Signal Groups


To rename a signal group, left-click on the signal in the Hierarchy pane to select the signal group, then left-click again to select the name. Enter the new signal name.

Filtering Signals
Use the drop-down menu in the upper right of the Signal pane to filter signal display in the Signal pane. Clear a signal to hide its display; select the check box to redisplay it.

Using Wave Views 5-9

Figure 5-5

Filter signal display menu

Adding Signal Dividers


To separate signals in the Wave view, you can add dividers between signals by selecting Signal > Insert Divider. You can add as many dividers between signals as you want. A divider inserted into a Signal Group displays in all instances of that signal group opened in Wave views. Dividers are saved in the session TCL file and are restored when the session is opened.

Customizing Duplicate Signal Display


When displaying duplicate signals, you can customize the display of an instance of a signal without affecting the display of any duplicates. To customize the signal display 1. Select a signal, then toggle Signal > Default Properties off. 2. Select Signal > Properties and make any changes to the signal scheme, or color.

Using Wave Views 5-10

Note: You can also right-click and select Properties from the contextsensitive menu. Changes are made to the selected signal without affecting the display of duplicate signals. Note: If you do not toggle Default Properties off, the changes will become the default and duplicate signal display will also change. If a signal group is in two Wave views, changing a signal will change the signal in the other Wave view if it is the same instance.

Using User-Defined Radices


This section describes how to create, edit, import, and export userdefined radices.

Creating a User-Defined Radix


You can define a custom mnemonic mapping from values to strings for display in the Wave view. To create a user-defined radix 1. Select Signal > Set Radix > User Defined > Edit. The Edit User-Defined Radix dialog box opens. 2. Click New, enter a radix name, then click Return.

Using Wave Views 5-11

3. Click Add Row to activate a row for the user-defined radix. For each row entry, select the text and background colors.

4. Click OK or Apply to save the user-defined radix. 5. To apply the user-defined radix to a signal, select the signal in the Wave view, select Signal > Set Radix, then select the userdefined radix from the list.

Managing User-Defined Radices


To edit or delete a user-defined radix 1. Select Signal > Set Radix > User Defined > Edit to display the Edit User-Defined Radix dialog box. 2. To delete a user-defined radix, select the radix from the UserDefined Radix pull-down menu, then click Delete. 3. To edit a user-defined radix, select the radix from the UserDefined Radix pull-down menu, click a cell in the Value or Display table, then enter your change.

Using Wave Views 5-12

4. Click OK or Apply to save the change.

Importing and Exporting a User-Defined Radix


To import or export a user-defined radix 1. Select Signal > Set Radix > User Defined > Edit to display the Edit User-Defined Radix dialog box. 2. To import a radix, click Import, then browse to and select the desired radix. 3. To export a user-defined radix, click Export. Select the radix from the User-Defined Radix pull-down menu, then enter a radix name. 4. Click OK or Apply.

Using the Waveform Pane


The Wave view displays the value transitions of signals and the real and vacuous successes and failures of assertions.

Using Wave Views 5-13

Figure 5-6

The Wave view


Cursors

Upper timescale Marker header area

Lower timescale

Cursors and markers are explained in Cursors and Markers on page 5-18. The Wave view has an upper and a lower timescale. The upper timescale displays the range of simulation times currently on display in the Wave view. The lower timescale displays the range of simulation times throughout the entire simulation.

Using Wave Views 5-14

Customizing Waveforms Display


To customize the display of waveforms 1. Select a signal in the Wave view, then select Signal > Properties or right-click and select Properties from the context-sensitive menu to display the Signal Properties dialog box.

2. In the Waveform Style section, set a height and custom color for the waveform. 3. Set the Style Scheme:

Using Wave Views 5-15

- For a scaler waveform, click the arrow and select from a scaler scheme as shown below:

- For an analog waveform, click the arrow and select from a vector scheme, an analog scheme, or an interpolated scheme as shown below:

The default display is a vector scheme. Variant vector schemes alter the color and values displayed. The analog option displays an analog waveform as a stairstep scheme, that stays at the value until the next reported value change.

Using Wave Views 5-16

- The interpol option displays an analog waveform interpolated between each reported value change.

4. If you are displaying the analog option, set the Y Range values by choosing to: - Display the full range the data type can represent - Auto adjust the display to the minimum and maximum of available values - Display a user-defined minimum and maximum range 5. Choose whether to mark samples and the marking symbol and size. 6. Select Y-axis scaling from Linear, Log_10, or decibel (dB). 7. Set the axis display. 8. Click OK to apply the settings and close the dialog box, Apply to apply changes and keep the box open, or Cancel to close the dialog box and disregard changes.

Overlapping Analog Signals


There are three ways to combine analog signals waveforms to visualize relationships between signals.

Using Wave Views 5-17

You can drag and drop one or several analog signals onto an analog signal. DVE creates a overlaying group as shown.

Use context sensitive menu by selecting analog commands to overlay, then right-click and select Analog Overlay from the menu. The results are the same as above. Convert a group by selecting a signal group with two or more analog signals, then right-click and select Analog Overlay from the context-sensitive menu. DVE overlay all signals in the group. as shown as above.

Use Unoverlay from the context-sensitive menu to restore the overlaid group back to a regular signal group.

Cursors and Markers


In the graphical display, you can insert markers and cursors.

Using Cursors
To insert cursors 1. Click the left mouse button to deposit cursor C1 in the graphical display. The C1 cursors default position is at time 0. Left-click somewhere else in the graphical display and cursor C1 moves to this new location.

Using Wave Views 5-18

2. Click the middle mouse button to deposit cursor C2 in the graphical display. Similar to cursor C1, middle-click somewhere else in the graphical display and cursor C2 moves to this new location. 3. To move cursors, place the mouse cursor on the round cursor handle in the cursor area, hold down the left mouse button and drag the cursor to the desired location. You can click either the left or the middle mouse button in the waveform or cursor area to move C1 or C2 respectively. The interval between the two cursors is always displayed in the marker header area. Figure 5-7 graphical display Cursors

In the Figure 5-7, the simulation time and the delta between the reference cursor (C1) and cursor C2 is shown in the marker header area.

Using Wave Views 5-19

Creating Markers
Markers differ from cursors in the way you insert and move them. Like cursors, markers display the delta between the reference cursor (C1) and the marker. The Markers dialog box allows you to create, move, hide, and delete markers, set the reference marker, and to scroll the graphical display until it reveals a marker. To create a marker 1. Right-click in the Waveform pane, and select Create Markers from the context-sensitive menu (CSM).

Using Wave Views 5-20

Figure 5-8

graphical display CSM

This inserts a dotted line on your mouse cursor in the graphical display.

Using Wave Views 5-21

Figure 5-9

Dotted Line For Positioning Marker

The dotted line tracks the mouse cursor as you move the mouse in the waveform or marker header area. 2. Position the marker in the graphical display then left-click to position the marker. Note that the marker annotation displays marker position and the delta between the marker and cursor C1.

Using Wave Views 5-22

Figure 5-10 New Marker

As you insert markers, DVE names them M1, M2, M3 and so forth. You can rename them using the Markers dialog box.

Using Wave Views 5-23

Figure 5-11 The Markers Dialog Box

The C1 marker is the default reference marker. To set another marker as the reference marker, select the marker in the reference column. 3. Click the Tips button to expand the dialog box to show contextsensitive help about the dialog box.

Drag Zooming
There are two ways to zoom in and out in the graphical display: Use the menu commands that cascade after the View > Zoom menu command in the Top Level Window: Zoom In, Zoom out, Zoom Full, Zoom to Time Range, and Zoom to Cursors, or use their corresponding toolbar icons. There is also a Zoom command in the CSM for the graphical display. Drag zoom in the graphical display. Drag zooming is described here.

Using Wave Views 5-24

To drag zoom, move the mouse cursor to any point in either of the timescales or in the waveform display area, hold down the left mouse key and drag a region of the timescale. The selected region turns light blue. When you release the mouse key the graphical display changes its display to only those transitions in the selected region of the timescale.

Expanding and Contracting Wave Signals


You can expand and contract the height of wave signals. Select View, then select Increase Row Height or Decrease Row Height. You can also right-click and select Properties and use the Signal Properties dialog box to increase or decrease row height.

Searching in the Graphical Panes


When searching graphical panes, if any signals are selected in the Wave view, searching will search only in the waveforms for the selected signals. If no signal is selected, it searches all the signals. You can have the C1 cursor move from its current location to the next using the search forward and search backward arrows in the toolbar. To set the search criteria, click the down arrow in the toolbar and select one of the following: Any Edge Rising Falling Match

Using Wave Views 5-25

MIsmatch Value...

Comparing Signals, Scopes, and Groups


You can compare individual signals with the same bit numbers, scopes (for comparing variable children), buses, or groups of signals from one or two designs. To view a comparison 1. Select one or two signals, signal groups, scopes, or buses from the Signal Pane of the Wave view. 2. To display the Compare Signals dialog box, right-click in the Signal Pane, then select Compare from the context-sensitive menu.

Using Wave Views 5-26

Figure 5-12 .Waveform Compare dialog box

3. Click Load Reference Signals/Scopes, then select the text file with the signals and scopes to reference. Note: If you are comparing two designs from root, then the reference region and test region can be empty. 4. In the Test Waveform area, select the test design and the test region. If you are comparing two designs from root, then Reference Region and Test Region can be empty. 5. Select Only Display Differences to display only those results that do not match in the Wave view.

Using Wave Views 5-27

6. In the Options section, you can choose one or both Ignore X and Ignore Z to ignore. For example, if you select Ignore X, if the reference signal value is X, there is always a match, whatever the values of the Test Signal. 7. Choose signals to compare by selecting one or all of In Port, Out Port, Inout Port, and Signals. 8. Enter a Time Tolerance to filter out mismatch values that have time ranges smaller than the tolerance range. 9. Enter mismatch settings for maximum mismatches per signal and maximum total mismatches to report. 10. Click Apply to start the comparison and keep the dialog box open. Or Click OK to start the comparison and close the dialog box (you can open it at any time from the Signal Pane context-sensitive menu). Results are displayed in the current Wave view.

Using Wave Views 5-28

Figure 5-13 Compared Signal Groups in the Wave view

11. To review comparison information, select a result in the Wave view, right-click and select Show Compare Info. The Results Summary Report displays in the Waveform Compare dialog box. Figure 5-14 Waveform Compare Summary Report

You can change the options, then recompare.

Building Buses and Setting Expressions


Use the DVE Bus Builder function to create and edit buses or expression using the signals from the opened designs. You can also create buses and expressions under a user specified scope.

Using Wave Views 5-29

To display the Bus/Expression dialog box ,right-click and select Set Bus from the context-sensitive menu or select Signal > Set Bus. You can include component signals by selecting signals in the signal pane of the Wave view or by dragging or copying signals from the Hierarchy Browser into the Bus Builder dialog. You can add and delete signals or change their order in the bus. You can drag components to the List view to view values. After you create a bus, you can use it as you would any other signal in the design. By default, it will reside in the highest level signal group common to its components.

Using the Bus/Expression Dialog


Figure 5-14, shows the Bus/Expression dialog box.

Using Wave Views 5-30

Figure 5-15 Bus Builder Dialog

Bus/Expression List Box The list box displays buses and expressions. Show/Hide the Detail Form Click the Define button to show or hide the tabs of bus or expression. The Bus Tab Name - Name of the signal bus. You can give any legal name to the buses for the language (e.g., Verilog, VHDL). When opened in Edit mode, this field is inactive. Scope - Name of user-specified scope. When opened in Edit mode, this field is inactive.

Using Wave Views 5-31

Bit Range - Bit range is 0 to N, where N is the number of components in the bus. Vectors and structures are expanded to their bits. For example, if top.risc.pc[3..0] is added to the list, it is added as four items. The Toolbar allows you to build and edit a bus. The following describes the Bus Builder toolbar commands.
Action Cuts the selection from the component list.

Toolbar Item

Copies the selection from the component list.

Pastes a copied component or components.

Deletes the selection.

Adds a 1'b1 constant signal to the bus.

Adds a 1'b0 constant signal to the bus.

Moves the selection down in the component list.

Moves the selection up in the component list.

Reverses the order of the selected components..

Components - Lists the elements of the currently selected bus. You can also use the toolbar commands to modify the components and their order.

Using Wave Views 5-32

Creating a Bus To create a bus 1. In the Wave view Signal Pane, you select signals and buses to include in the new bus. Or Select no signals. You can choose components later. 2. Right-click in the Signal Pane or select Signal from the menu, then select Set Bus. The Bus/Expressions dialog box is displayed. 3. Enter a name for the new bus. 4. To create the bus under a user-specified scope, enter a scope name. 5. (Optional). Add constant +1 or constant +0 signal to the bus. 6. To add signals and busses to the component list: - Drag and drop components from the Wave view Signal Pane or the Hierarchy Browser. - Select components in the Signal pane, click in the Bus/Expressions toolbar. 7. Click OK to save the bus and display it in the Wave view. Modifying Bus Components You can edit an existing bus or modify the components and their order in a new bus using the Bus Builder toolbar. , then click

Using Wave Views 5-33

To modify bus components 1. Select the bus in the Wave view signal pane, then right-click in the Signal pane or select Signal from the menu, then select Set Bus. 2. To add signals and buses to the component list: - Drag and drop components from the Wave view Signal pane or the Hierarchy Browser. - Select components in the Signal pane, select in the Bus Builder toolbar. 3. To delete components, select the components in the component list, then click in the Bus Builder toolbar. , then click

4. To move components up or down in the list, select one or more components in the component list, then click Bus Builder toolbar. or in the

5. To reverse the order of components relative to each other, select two or more components from the component list, then click in the Bus Builder toolbar. 6. Click OK to save the bus and display it in the Wave view. Using the Expressions Tab Use the Expressions tab to create and modify expressions. Note that Complex SystemVerilog data types are not supported.

Using Wave Views 5-34

To use the Expressions tab 1. Right-click in the Signal pane or select Signal from the menu, then select Set Expressions. The Bus/Expressions dialog box opens. Figure 5-16 Expression tab

2. To create an expression, enter a name for the expression. 3. To modify an expression, select an expression from the list and select an expression type. 4. Click operators to insert them into the expression.

Using Wave Views 5-35

5. Click Create or Update to save the expression.

Viewing Bus Values


View a tooltips for bus values in waveforms (with transitions on edges) by positioning the cursor on the waveform. Figure 5-16 shows a tooltip at a transition displaying the transition values. Figure 5-17 Viewing a bus value at a transition

Shifting Signals
You shift a signal by creating a new signal based on a time shifted signal. To shift a signal 1. Select a signal in the Signal pane. 2. Select Signal > Shift Time to display the Shift Signal dialog box.

Using Wave Views 5-36

3. Enter a positive Time Offset to shift the signal to the right or a negative number to shift to the left in the Waveform pane.

The signal displays with the original signal name followed by the time offset. In the above figure that is test1.risc.daata(7:0)->>10.

Printing Waveforms
You can print waveforms to a file or printer from an active Wave view selecting time range and signals to print.

Using Wave Views 5-37

1. From an active Wave view, select File > Print or click the print toolbar button to display the Print Waveform dialog box.

2. Click the set up button to set printing options: - Printer or print to file - Print in color or grayscale - Print orientation and paper size - Print options such as range and number of copies 3. Select the total time range to print and the time range to print per page. 4. Select whether to print All, Displayed, or Selected signals.

Using Wave Views 5-38

5. Select the page margins. 6. Choose Landscape or Portrait orientation. 7. Click OK to print.

Using Wave Views 5-39

Using Wave Views 5-40

6
Using the List View 6
The List view displays simulation results in tabular format. For Verilog, the List view supports nets and register variables. For VHDL, it displays signals and process variables. This chapter covers the following topics: The List View on page 6-2 Displaying Data on page 6-3 Navigating Simulation Data on page 6-5 Customizing the Display on page 6-7 Comparing Signals on page 6-9 Saving a List Format on page 6-13

Using the List View 6-1

The List View


The List view is comprised of three sections: The Signal pane displays signal names as headers above the simulation data. The Data pane displays simulation results in tabular format. The Simulation Time pane.

Using the List View 6-2

Figure 6-1 The List view Time Pane Signal Pane Data Pane

Displaying Data
The List view displays results similar to the Wave view, but it displays the results in tabular form. You can display data in the List view the same way you display data in the Wave view as follows: Dragging and dropping signals or assertions from another DVE window.

Using the List View 6-3

Using File > Open to open a database. Selecting File > Load Session, then selecting a saved session.

Dragging and Dropping Signals into the List view


To populate the List view with data from other DVE windows

1. Open a List view by selecting View > List view.

in the toolbar or

2. Drag and drop into the List view a scope or assertion of interest from the Hierarchy Browser, the Source pane, the Wave view, or from either tab of the Assertion window. The data is displayed in the default format.

Opening a Database
To open a database

1. Open a List view by selecting View > List view.

in the toolbar or

2. Choose Edit > Open Database and select the .vcd, .vpd, or .dump database file to open the saved session. The data is displayed in the default format.

Using the List View 6-4

Loading a Session
To open a previously saved session

1. Open a List view by selecting View > List view.

in the toolbar or

2. Select Edit > Open Session and select the .vcd, .vpd, or .dump database file to open or the saved session. The data is displayed in the default format.

Navigating Simulation Data


This section covers the following topics: Viewing Data in the List view Using Markers

Viewing Data in the List view


To view simulation data in the List view Use the bottom scroll bar to move left and right and view signals and their values. Use the right scroll bar to move up and down through simulation time. Select a signal in the signal pane to highlight the signal values as shown in Figure 6-2.
Using the List View 6-5

Figure 6-2 List view Simulation time

Selected signal

Results

Scroll bar

Using Markers
To set markers in the List view to speed navigation 1. Select View > Set Markers to display the Markers.List dialog box. 2. Click New to create a new marker in the list table.
Using the List View 6-6

3. Select the Time cell for the new marker, enter the time at which to set the marker, click Hidden if you dont want to display the marker in the Data Pane, then click Return. 4. Repeat steps 2 and 3 to create more markers. 5. Select a marker from the list in the Marker.List dialog box, then press Jump to move the data display to the selected marker. or Select View > Goto Marker, then select a marker from the list. 6. To remove a marker, select Delete in the Marker.List dialog box. or Select View > Delete Marker, then select the marker from the list.

Customizing the Display


This section covers the following topics: Setting Signal Properties

Setting Preferences
You can customize the list display to: Turn on/off grid lines Truncate signal names Display signals by levels

Using the List View 6-7

Specify the space between columns

To customize the display 1. Select Edit > Preferences. The Application Preferences dialog box opens. 2. In the Categories pane, select List Settings. Figure 6-3 Application Preferences dialog box

3. Select or deselect Show Grid, Full Name, or Left Justify checkboxes, as appropriate. 4. Click Apply to view your changes and keep the dialog box open, or click OK to apply your changes and close the dialog box. 5. Click Reset to reapply the defaults.

Using the List View 6-8

Setting Signal Properties


To customize signal display, you set signal properties for individual signals. To set the signal properties 1. Select a signal in the Signal pane. 2. Select Signal > Signal Properties to display the Signal Properties dialog box. 3. Enter the number of characters for the selected signal value column width. 4. Select whether a signal value change triggers a new line of values in the Data pane. 5. Click Apply to make the change and keep to dialog box open to select and set more signal column widths. Or Click OK to apply the changes and close the dialog box.

Comparing Signals
You can compare signals in the List view similar to the way you compare signals in the Wave Wndow. To view a comparison 1. Select one or two signals, signal groups, scopes, or buses from the Signal pane of any DVE window.

Using the List View 6-9

2. To display the Compare Signals dialog box, right-click in the Signal pane, then select Compare from the context-sensitive menu. Figure 6-4 .Waveform Compare dialog box

3. In the Reference Waveform area, if you did not select the reference design and signal in Step 1, select the reference design, then enter the reference region (signal, scope, or bus) to compare.

Using the List View 6-10

Note: If you are comparing two designs from root, then the reference region and test region can be empty. 4. In the Test Waveform area, select the test design and the test region. If you are comparing two designs from root, then Reference Region and Test Region can be empty. 5. Select Only Display Differences to display only those results that do not match in the Wave view. 6. In the Options section, you can choose one or both Ignore X and Ignore Z can be selected to ignore. For example, if you select Ignore X, if the reference signal value is X, there is always a match, whatever the values of the Test Signal. 7. Choose signals to compare by selecting one or all of In Port, Out Port, Inout Port, and Signals. 8. Click Apply to start the comparison and keep the dialog box open. Or Click OK to start the comparison and close the dialog box (you can open it at any time from the Signal pane context-sensitive menu). Results are displayed in the current Wave view.

Using the List View 6-11

Figure 6-5

Compared Signal Groups in the List view

9. To review comparison information, select a result in the Wave view, right-click and select Show Compare Info. The Results Summary Report displays in the Waveform Compare dialog box. Figure 6-6 Waveform Compare Summary Report

10. You can change the options, then recompare.

Using the List View 6-12

Saving a List Format


After you have customized the display in the List view, you can save the format for future use. To save the List Format 1. Select File > Save List Format to display the Save List Format dialog box. 2. Enter a filename with a .tcl extension for your format file. 3. Select Save.

Using the List View 6-13

Using the List View 6-14

7
Using Schematics
This chapter contains the following topics. Overview Managing Schematic Display Opening a Design Schematic View Opening a Path Schematic View Finding Signals in a Schematic View Following a Signal Across Boundaries Tracing X Values in a Design Printing Schematics

Using Schematics 7-1

Overview
Schematic views provide a compact, easy-to-read graphical representation of a design. You can view a design, scope, signal, or group of selected signals and select ports to expand connectivity in relevant areas. Explore the design behavior by analyzing the annotated values for ports and nets. There are two types of schematic views in DVE: design and path. A design schematic shows the hierarchical contents of the design or a selected instance and lets you traverse the hierarchy of the design. A path schematic is a subset of the design schematic displaying where signals cross hierarchy levels. Use the path schematic to follow a signal through the hierarchy and display portal logic (signal effects at ports).

Note: Your design must be compiled in the same version of VCS that you are currently pointing to in your session.

Managing Schematic Display


This section describes toolbar and menu commands for Managing schematics.

Using Schematics 7-2

Selecting and Zooming Graphics


When viewing the schematic, you use the scroll bars to move up and down and left and right in the displayed graphics. You can also use toolbar and menu commands to select parts of the design to zoom in or to copy or drag and drop into another DVE window. The following table describes toolbar and menu commands.
Toolbar Command View Menu Command Selection Tool Zoom In Tool Action Prepares the cursor for selecting objects (the default cursor). Prepares the cursor for zooming in. The cursor becomes a magnifying glass. Drag a bounding box around the area to enlarge. Prepares the cursor for zooming out. The cursor becomes a magnifying glass. Drag a small box to zoom out by a large amount, or a large box to zoom out by a small amount. Prepares the cursor for panning the window view. The cursor becomes a hand shape. Point and drag to pan the view. Zooms out to display entire design. Zooms in 2x. Zooms out 2x.

Zoom Out Tool

Pan Tool

Zoom Full Zoom In Zoom Out

Zoom to Selection Zooms to area selected with the Selection Tool.

Customizing the Display


To customize the schematic display, you can perform the following tasks:

Using Schematics 7-3

Set the maximum number of cells in the schematic. Change the text style and size displayed on your schematics. Change the visibility and colors of cells, hierarchical crossings, nets, busses, ports, pins, and rippers.

To customize the schematic display 1. Select Edit > Preferences, then in the Category pane, select Schematic view. 2. Click the up and down arrows to set the maximum number of cells as shown in Figure 7-1. Figure 7-1 Setting Application Preferences

3. Specify display characteristics for number of cells and text size. 4. Check or clear the Visibility checkboxes to filter the display of design elements. 5. In the Line column, select colors for design elements.

Using Schematics 7-4

6. To customize value annotations, click '+' in the categories pane next to Schematic view and select Value Annotation.

7. Select the Port/Pin visibility and color. 8. Do one of the following: - Click OK or Apply to display your changes and close or keep the dialog box open. - Click Cancel to ignore your changes and close the dialog box. - Click Reset and choose Reset Current Category, Reset All Categories, or Refresh Dialog.

Using the Context-Sensitive Menu


A context-sensitive menu displays when you right-click in the graphics area of a schematic or path schematic view. The following table describes the commands.
Command Copy Show Source Action Copies the selection to the clipboard. Displays the source code for the selection.

Using Schematics 7-5

Show Path/ Schematic view Add to Waves

Opens a new Path or Schematic showing the currently selection. Adds the selected signal set from the active pane and adds the signal to the default Wave view. If there is no Wave view, DVE creates one and adds the signals under the insertion bar. Adds to Waves but for the List view. Selects New Group to create a new signal group. The name will be Group<n>, where n is one more than the highest numbered existing signal group. The new signal group is created at the top of the signal list. Displays the path of a selected signal across boundaries in a path schematic view. Displays the Add Fanin/Fanout to adds the fanin logic to or fanout logic from a specified object in an currently active path Displays a higher-level schematic view of the parent design in the active schematic view.

Add to Lists Add to Group

Expand Path Add Fanin//Fanout Move Up to Parent

Move Down to Definition Displays a design schematic for the selected design instance in the active schematic view. Back> Forward> Selection Tool Zoom In Tool Displays the previous schematic from the history. Displays the next schematic in the history. Used for schematic views. Changes the mouse behavior, so left-clicking and dragging selects the object. Used for Schematic views. Changes the mouse behavior, so left-click zooms in. Left-click drag creates a box that will become the new view extents for the schematic. Used for Schematic views. Changes the mouse behavior, so left-click zooms out. Used for schematic views. Changes the mouse behavior so left-clicking and dragging spans all the objects in the schematic view. For example, left-click drag down, moves all the objects down in the view. Choosing this menu item also changes the cursor to a hand. Click the toolbar selection arrow to change the cursor back to normal. Creates a sub menu for all zoom operations. These menu items are only applicable for Schematic and Wave panes. Displays values at the pins.

Zoom Out Tool Pan Tool

Zoom> Annotate Values

Using Schematics 7-6

Set Radix >

Creates a submenu giving reasonable choices for radix changes for the selected signal. Changing radix on a signal is global and will change the radix wherever the signal is displayed in the debugger. User Defined - Creates a sub-submenu that allows you to choose user-defined types if any and allows you to specify user-defined types from a dialog box. Edit ... - Displays the user defined radix dialog box. See Using User-Defined Radices on page 5-12. This menu item will be active if the object selected in the currently active pane is a variable or signal. For this capability to work, the design must be compiled with one of the -debug options and an mdb library must exist. Finds the active driver of the object, shows the driver in the drivers/loads pane and shows the driver in the reusable source pane in the current window. If no window is present, DVE creates one. If a drivers pane already exists, the new trace information is added to it. Same as above except for loads of the signal. Creates a dynamic submenu that allows you to navigate and manage drivers/loads displays. See Tracing Active Drivers and Loads on page 1. Traces the X value. Brings up the Dump Values dialog box to specify signals to dump value change information starting at the current time. See Dumping Signal Values on page 3-14. Turns on value change dumping at the current time for any selected signal in the active pane. Brings up the Force Values dialog box to allow you to interactive change the value of a signal. See Forcing Signal Values on page 3-15.

Trace Drivers

Trace Loads Drivers/Loads

TraceX Add Dump . . .

Dump Add Force

Opening a Design Schematic View


To view a schematic of an open design in DVE, you must generate your simulation on the same platform you run DVE from and use the -debug command line option to compile.

Using Schematics 7-7

To open a display design schematics 1. To choose between opening the schematic in the current active DVE window or in a new window, click toggle a new window on or current window. in the status bar to

to view the schematic in the

2. Select an instance from the Hierarchy Browser, right-click and select Show Schematic from the context-sensitive menu. The Schematic view displays the connectivity in the selected instance. Figure 7-2 shows an example of a hierarchical schematic.

Using Schematics 7-8

Figure 7-2

. Design Schematic

Using Schematics 7-9

Selecting a Signal in the Schematic


1. Click on a signal in the schematic or, to find the signal in the schematic, enter the signal name in the Find toolbar box in the Schematic view, then click the Find Next toolbar button. The signal is highlighted in the schematic. 2. With the signal selected, click the Trace Drivers toolbar button, or select the Trace-Drivers menu item. Now the signal is highlighted in purple. Figure 7-3 Highlighted signal in Schematic view

Using Schematics 7-10

Annotating Values
To view the annotated values of a signal, select Schematic > Annotate Values.

Note: If you hold the cursor on a signal, a tooltip identifies the signal as shown above.

Opening a Path Schematic View


A path schematic is a subset of the design schematic displaying connections that cross hierarchical boundary.

Using Schematics 7-11

To open a path schematic view 1. Open a design schematic view of an instance containing the hierarchical crossings of interest (See the section, Opening a Design Schematic View on page 7-7). 2. When you have identified the instance to display, click it to select. The color change indicates that it is selected, as shown in Figure 7-4. Figure 7-4

Note: You can also drag the selection cursor over multiple objects to select multiple items.

3. Right-click and select Show Path Schematic or click toolbar to view a path schematic in a new window.. The path schematic for the selection is displayed.

in the

Using Schematics 7-12

Figure 7-5 shows a path schematic. Figure 7-5 Path Schematic

Displaying Connections in a Path Schematic


With a path schematic displayed, you can add the logic fanin to, or logic fanout from, specified objects in the schematic across specified levels or the entire design. To display connections 1. Select an object or objects in the path schematic. Your selection changes color confirming selection. 2. Select Scope > Add Fanin/Fanout. The Fanin/Fanout to Path Schematic dialog box is displayed as shown in Figure 7-6.

Using Schematics 7-13

Figure 7-6

Add Fanin/Fanout to Path Schematic dialog box.

3. Click Set Selected to add the selected objects to the list box. You can optionally select more objects and use the Add Selected button to add them to the list. 4. Set the other options, such as the number of logic levels to be added and the Reuse Windows Options. 5. Click OK to update the schematic with the additional fanin or fanout logic. The schematic displays as shown in Figure 7-7.

Using Schematics 7-14

Figure 7-7

Path schematic with fanin logic

6. Select Signal > Annotate Values to view signal values. Figure 7-8 Path Schematic with values

Finding Signals in a Schematic View


Manually Tracing Signals
You can select one or more signals to trace in a Schematic or Path Schematic view. With this option, the selected signals are highlighted based on specified line colors you select. To highlight signals 1. Select Trace > Highlight, then select Set Current Color.
Using Schematics 7-15

2. Select a color for the highlight. 3. Click OK.

Searching for Signals


You can use the Find toolbar option to locate signals. To locate signals 1. Click on a signal in the schematic or, to find the signal in the schematic, enter the signal name in the Find toolbar box in the Schematic view, then click the Find Next toolbar button. The signal becomes highlighted in the schematic. 2. With the signal selected, click the Trace Drivers toolbar button, or select the Trace-Drivers menu item. Now the signal is highlighted in purple.

Using Schematics 7-16

Figure 7-9

Highlighted signal in Schematic view

Following a Signal Across Boundaries


You can select a signal and follow it across hierarchical boundaries in the Path Schematic view. To follow a signal 1. Select a signal or signals in any DVE list, then right-click and select Show Path Schematic. 2. In the Path Schematic, select a signal.

Using Schematics 7-17

Figure 7-10 Signal selected

3. Right-click and select Expand Path from the context-sensitive menu. The signal is highlighted in the path view.

Using Schematics 7-18

Tracing X Values in a Design


You can trace an X value through a design, for example, across gates, to identify the signal that caused the X value. To trace an X value 1. Select an instance from the Hierarchy Browser, then right-click and select Show Schematic. By default, a new Schematic view opens in the main window as a tabbed window. 2. Zoom schematic to fit window.

Using Schematics 7-19

3. Click the Annotate Values toolbar button in the Schematic view.

4. Select Schematic view category. 5. Select the signal with an X value. The signal wire turns white when selected. 6. Select Trace > Trace X.

Using Schematics 7-20

The x value is traced to its source signals making it easy to identify the signals that caused the X value.

Printing Schematics
You can print schematics to a file or printer from an active Schematic or Path Schematic view selecting time range and signals to print.

Using Schematics 7-21

1. From an active Schematic or Path Schematic view, select File > Print or click the print toolbar button Schematic dialog box. to display the Print

2. Click the Setup button to set printing options: - Printer or print to file - Print in color or grayscale - Print orientation and paper size - Print options such as range and number of copies 3. Select whether to print All, Displayed, or Selected signals.

Using Schematics 7-22

4. Select the page margins. 5. Choose Landscape or Portrait orientation. 6. Click OK to print.

Using Schematics 7-23

Using Schematics 7-24

8
Working with Assertions and Cover Properties 8
This chapter describes viewing and working with assertion results. The following topics are covered: Compiling SystemVerilog Assertions on page 8-1 Viewing Assertion Results on page 8-2 Debugging Assertions on page 8-5

Compiling SystemVerilog Assertions


Use the -assert dve flag on the VCS command line when compiling SystemVerilog assertions (SVA) for debugging with DVE.

8-1

Note: The link step can take a long time if you use a Solaris linker prior to version 5.8. To avoid linking delays when using DVE to debug designs compiled on Solaris, do either of the following: Make sure your Solaris C compiler is version 5.8 or above. To check your compiler version, enter the following on the command line:
ld -V

The system returns your linker version, for example:


ld: Software Generation Utilities - Solaris Link Editors: 5.8-1.283

Use the gcc C compiler when compiling your design. For example:
vcs -assert dve -PP -sverilog a.v -ld gcc

Viewing Assertion Results


The Assertion Pane displays SVA and OVA assertion and cover property results. DVE displays assertion results by instance include start and end times of assertion events, the delta, the offending string in assertion failures, and totals for failures, real successes, vacuous successes, incompletes and attempts. Successful assertions are displayed in green, vacuous successes in brown, and failed assertions in red.

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Figure 8-1

Assertion results

Note: Use the VCS -assert DVE command line switch with the -PP flag to enable SVA tracing in DVE. If you do not enable SVA tracing, assertion value changes will still be dumped into the VPD file and be visible in the Wave view, but assertion attempts cannot be traced. Cover properties results, shown in Figure 8-2, display instance include start, end time, and the delta, and the total number of matches, mismatches, incompletes, and attempts. Cover properties

Figure 8-2

Setting Display Criteria


You use the Assertion pane navigation bar to display results based on selected criteria, as shown in Figure 8-3.

8-3

Figure 8-3

Assertion and cover properties displayed.

Click to display assertion or cover properties results.

Specify display criteria by starting and ending time.

Select a condition for the results display.

To set display criteria by starting ending time 1. Click the arrow in the display control bar and select all, starting, ending, or starting and ending. The display criteria selections become active. 2. Select at time or from, then select begin, current, or end to specify the window. 3. Specify the condition as follows:

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- For assertions, select failures, incompletes, successes, vacuous successes, or all. - For cover properties select uncovered, covered or all. Note that the default is to display uncovered.

Debugging Assertions
When you open a design that contains assertions, DVE displays the Assertion Pane even if all the assertions pass. The default is to display failed assertions. To display the first 10 failures and successes, click the "+" next to an assertion of interest. Figure 8-4 shows the attempt list. Figure 8-4 Assertion attempt list

The Assertion Pane is interconnected with other DVE windows and panes. To display a assertion in the Hierarchy and Variable panes, the Source view and the Wave view, double click an assertion instance in the Assertion Pane. Figure 8-5 shows the panes.

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Figure 8-5

Populated panes

The following occurs: The Hierarchy pane displays the associated unit or HDL scope that contains the assertion. The Variable pane displays the HDL variables corresponding to the unit or scope. This is not specific to the assertion (i.e., it may contains more signals that are used in the assertion). Up to three Source views may be displayed: one for the HDL source, one for the bind source and one for the OVA definition source. The Wave view opens and displays the selected assertion centered on the failure. The cursors mark the start and end time of the selected assertion with the area between the cursors grayed.

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A green circle indicates a signal value at a specific time that contributed to successful sub-expression in the assertion. A red circle indicates a signal value at time that caused a subexpression to fail. A sub-expression failing may result in the overall assertion failing.

Viewing an Assertion in the Wave view


Figure 8-6 shows an assertion with no delta between start and end time. Figure 8-6 Assertion in Wave view

In Figure 8-7:

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The C1 and C2 cursors are automatically placed at the start and end of the assertion. In this assertion, there is no time component (sequence), so C1 and C2 are at the same time. In Signal Group 1, the assertion RESET_CHECKER is listed first in the tree view. This is the assertion result signal. The waveform consists of red and green arrows. Green shows where the assertion was determined to be a success, red shows where it failed. The red arrow indicates the first failure. RESET_CHECKER is expanded into components. - The first component is clk_event. Each clock event shows you when the assertion fired and the clock ticks that happen for sequences. - The rest of the signals are the signals that contributed to the success or failure. The signals are clk, rst, hour, min, sec. - The green dots on the waveform show you that the signal was OK at that clock tick. The red dots show you that the signal contributed to the failure of the assertion at that clock tick.

Viewing an Assertion Failure Time Delta


When there is a delta for an assertion failure, the Wave view opens and displays the selected assertions centered on the failure. The cursors mark the start and end time of the selected assertion with the area between the cursors grayed. A green circle within a signal indicates a successful signal or value, while a red inverted circle and the C1 cursor indicates a failure.

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Figure 8-7

Assertion failure time delta in the Wave view

If you hold the mouse cursor over a green or red circle, an infotip pops up and shows details on the impact of the signal. - If a green arrow, the infotip tells why this signal contributed to a success so far. - If red arrow, the infotip tells why this signal contributed to a failure.

A white arrows indicate assertion clock events in the window. If you hold the mouse cursor over the attempt failure, an infotip pops up and shows details on the failure. The infotip contains (for each attempt ending at this time): - Start time

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- End time - Delta - Instance - Offending/Reason

Navigating Assertions in the Wave view


Use the Search toolbar item to move to the next or previous assertion success or failure in the Wave view. To navigate assertions in the Wave view 1. With an assertion selected, select Success or Failure from the Search pulldown menu (see Figure 8-9). Figure 8-8 Navigate assertion successes and failures

2. Click the back or forward arrow to move to the previous or next success or failure of the selected assertion. Note: The Match and Mismatch items in the Search pulldown menu are used for signal comparisons, not for assertion cover property match and mismatch display in the Wave view.

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Local variables are inserted into the signal list in the hierarchy pane as shown by the local variable count.Navigating Source Code To display code related to an assertion attempt 1. Double-click an assertion attempt in either Assertion View tab (see Figure 8-9). Figure 8-9 Select an assertion attempt

Code is displayed as follows: - The Source Pane displays the HDL code where the assertion is inlined or bound. - A Source view displays the assertion code with the assertion highlighted (see Figure 8-10).

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Figure 8-10 Assertion source code

2. To edit the assertion in your default text editor, select Edit > Edit Source.

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9
Tracing Active Drivers and Loads 1
Note: This is a limited-customer-availability (LCA) feature. You can use LCA features without requiring a special license from this release onwards. To enable the LCA features, you must use the following compile-time option at the VCS command prompt:
vcs -lca

This chapter describes how to use Discovery Visual Environment to trace drivers and loads of signals in your design. It contains the following sections: Overview of Tracing Functionality on page 2 Trace Drivers on page 6 Trace Loads on page 7

Tracing Active Drivers and Loads 9-1

Overview of Tracing Functionality


Use DVE to trace drivers and loads and follow connections that affect a signal value. The active driver of a signal is the driver that contributed to the value of the signal at a given time. Displaying all drivers shows all drivers that can possibly contribute to a signal value. A signal's load(s) are the input port(s), I/O port(s), and statements that read the signal's value.

Figure 9-1 shows the Drivers and Loads pane.

Tracing Active Drivers and Loads 9-2

Figure 9-1

Drivers and Loads pane


Maximum number of levels The value of the signal at the Linked windows time shown

Tree view with signal name and any driving statements

Select to add signals to the Wave view

The line number and file name of the driving statement

For tracing drivers and loads, DVE has the following functionality: Multiple driver panes are allowed as long as there are multiple top level windows to contain them. Driver panes are independent from top level to top level. Driver panes can be deleted any time by clicking on the X icon. Driver panes can be undocked or docked elsewhere at anytime.

Driver panes can be linked to at most 1 Source view in the same top level frame and one Schematic view. The Links: combo boxes, at the top of the pane show the current linked windows. By default, the first open Source pane is linked to the driver pane and no schematic (indicated by <new Schematic>).

Tracing Active Drivers and Loads 9-3

Linking a Source and Schematic view means those windows can be wired up to track the selection. That means that selecting an object in the drivers pane will cause that object to be selected and shown in the linked Source or Schematic views. Checking the Add to Waves checkbox will add any signal shown in the driver pane to the Wave view. Unchecking the Add to Waves checkbox does not delete anything from the Wave view but prevents additional signals in the drivers pane from being added to the Wave view.

Supported Functionality
All Verilog types, constructs, control path. Verilog gate and UDPs. VHDL but only down to the process statement. All drivers within a process are determined to be active.

Unsupported Functionality
SystemVerilog datatypes are not supported.

Functionality with Vera


A driver is active until proven inactive. A driver becomes inactive when ANY part of the control path to the driver evaluates to false. A driver in a looping statement (e.g. always, while, repeat) will always be active regardless of the control path evaluation.

Tracing Active Drivers and Loads 9-4

Using the Driver Pane Menu


Trace Drivers Trace Loads Show Source Show Schematic Performs a new drivers trace on the selected signal. Performs a new loads trace on the selected signal. Shows source file and line of the selected signal or first signal if more than one selected. Show design schematic for the selected signal, the signal will be highlighted in the selection color (default white). Show path schematic for the selected signal, the signal will be highlighted in the selection color (default white). Selects all items in the current view. Deselects all selected items. Deletes all selected items from the view. Toggles current active driver display on. Toggles all drivers display on. Removes the selected trace or traces from the driver pane. Removes all information from the driver pane. Toggle button On (checked) means Source view tracks selection from the driver pane. Selecting signal highlights signal port or declaration in Source view. Selecting driving statement highlights that statement. Adds the selection to the Wave view. Adds the selection to a group. Adds the trace information to the Wave view. Advances the simulation to the specified time. Toggle button On (checked) means Schematic view tracks selection from the driver pane. Selecting signal highlights the signal. Selecting driving statement shows design with scope selected.

Show Path Schematic

Select All Delete Delete All Show Active Drivers Show All Drivers Clear Trace Clear All Traces Synchronize Source view

Add to Waves Add to Group q Add Trace to Waves Go to Time Synchronize Path Schematic

Tracing Active Drivers and Loads 9-5

Trace Drivers
To trace drivers 1. Select a signal in a DVE window or pane. For example, Hierarchy Browser, Data pane, Wave view, Source view, List view, or Wave view. 2. Click the drivers toolbar icon .

3. Select a signal in any pane, then select Trace >Trace Drivers. 4. In the Wave view, double-click on a waveform. For example on a transition from 0 -> 1 or 1 -> 0. 5. In the Wave view, select a signal, right-click and select Trace Drivers. 6. In the Source view, double-click a signal. 7. In the Schematic view, select a signal, right-click and select Trace Drivers. When a driver is traced, a new driver pane will be created if none exists in the current top level. If a driver pane exists, the driver information will be added to the top of the list. Additionally, the first driver will be highlighted in the Source view and annotated with a blue node in the gutter, as shown in Figure 9-2. Note: Only one driver pane is allowed per top level frame.

Tracing Active Drivers and Loads 9-6

Figure 9-2

Select a transition in the Wave view to display driver.

Trace Loads
To trace loads 1. Select a signal in a DVE window or pane. For example, the Hierarchy Browser, Data Pane, Wave view, Source view, List view, or Wave view.

Tracing Active Drivers and Loads 9-7

2. Click the loads toolbar icon

3. Select a signal in any pane and select Trace >Trace Loads. 4. In the Wave view, select a signal, right-click and select Trace Loads. 5. In the Source view, select a signal, right-click and select Trace Loads. 6. In the Schematic view, select a signal, right-click and select Trace Loads. When a load is traced, a new driver pane will be created if none exists in the current top level. If a driver pane exists, the load information is added to the top of the list. Note: Only one driver pane is allowed per top level frame.

Functionality with Vera


A driver is active until proven inactive. A driver becomes inactive when ANY part of the control path to the driver evaluates to false.

Tracing Active Drivers and Loads 9-8

10
DVE Testbench Debugger
This chapter describes the DVE (Discovery Visual Environment) Testbench Debugger and contains the following sections: Overview on page 1 Enabling Testbench for Debugging on page 3 Using the Testbench Debugger GUI on page 3 Familiarizing with Testbench Debugger GUI on page 4

Overview
The DVE integrated testbench graphical debugger provides a common interface for debugging HDL and Testbench code simultaneously and is seamlessly integrated with the current DVE HDL debug windows.

10-1

In interactive mode, the Testbench Debugger provides you visibility into the testbench-related dynamic constructs and their values during simulation. This is done using the proven visualization of the Testbench GUI's stack pane, local pane, and watch pane combined with DVE's source window and its intuitive look and feel. Using the salient features of the new testbench debugger, you can analyze, understand, and debug the behavior of your complicated verification environment faster. You will be able to perform a comprehensive analysis using the seamless design and verification environment. The testbench debugging interface enables you to do the following: Set line breakpoints Navigate HDL or Testbench source code in a single DVE Source pane View HDL and Testbench scopes in DVE's Hierarchy pane Analyze HDL and TB signals together in the Watch pane Run HDL and Testbench-related UCLI commands all from a single application

Note: The new advanced testbench debugging features with the DVE described in this section are available with VCS 2006.06-SP2 and above.

10-2

Enabling Testbench for Debugging


To enable the debugging capabilities for the testbench, you must specify the debug_all switch along with your compilation command. Note: If you compile your design and testbench separately (NTB-OV separate compile flow), ensure that you use debug_all when compiling both your design and the testbench.

Using the Testbench Debugger GUI


You can start the Testbench Debugger from the command line and then perform your simulation run from the user interface. From your command prompt, enter the following command:
%> simv -gui

The simv is your executable in the above example. Note: If you use the -debug_all option when compiling your design that contains testbench code, the DVE provides debugging options for your testbench program automatically. However, you can disable these settings in the Preferences dialog by clearing the option Enable testbench debugging for interactive design in the Edit menu. Select a transition in the Wave view to display driver.

10-3

Familiarizing with Testbench Debugger GUI


This section describes the DVE Testbench Debugger GUI.

Testbench Debugger Panes


The top-level window of DVE contains three additional panes. The three additional panes are Stack pane, Local pane, and Watch pane as illustrated in the following diagram:
Stack Pane Local Pane Source Code Viewer

Watch Pane

Log Pane

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Note: Watch pane appears only when you add variables or signals to it for monitoring purposes. Stack Pane - Displays the testbench dynamic hierarchy tree along with all the testbench threads and their status. This pane is highlighted when the Local tab is selected. Local Pane - Displays all the testbench variables and dynamic objects with their current values based on the currently selected scope within the call stack. The testbench variables and dynamic objects will change when you select different testbench scopes in the Stack. Watch Pane - Enables you to monitor the status of your variables during simulation.

Stack Pane
This pane shares a tabbed view with the hierarchy pane. Select the Stack tab to display the Stack pane and view the status of various threads. This view is cross-linked with the Source and Local panes. Double-clicking on objects in this pane synchronizes the display in the source and local panes. The hierarchy tab displays only the static objects in your design whereas the Stack tab displays the dynamic threads created during runtime. Note: The Stack pane appears empty when you invoke the Testbench Debugger at time 0. The dynamic objects are displayed as and when they are created in the testbench during simulation.

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The following figure illustrates the Stack tab and the Hierarchy tab.

The above illustration shows the current active threads and their status. The status of a thread could be Running, Stopped, and Suspended. The following table illustrates the conventions denoted by these icons: Thread is running. Thread is stopped. Thread is suspended.

The thread column displays the unique id of the thread. It can be the same if function calls in the stack belong to the same thread.

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Using the Stack Panes Context Menu The Stack pane context menu provides various options. You can quickly access and start using these options through the context menu. To invoke the context menu, right-click your mouse from the Stack pane. The following menu options appear:

The following table explains the menu options:


Copy Show Source Add To Watches Expand All Collapse All Select All Takes copy of the object. Displays source code of your testbench program. Adds signals to monitor in the Watch pane. Expands the tree. Collapses the tree. Takes copy of all the objects.

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Local Pane
The local pane shares a tabbed view with the Data tab. The local pane displays variables in a selected scope in the stack pane. This view is tied to the stack pane and the default view shows variables of the current active thread. This pane also has a Filter feature that you can use to search or find variables.

Search/Find

Note: The Local pane displays the variables when you select an object in the Stack pane.

Watch Pane
At times, you may need to monitor the status of testbench and HDL variables throughout the simulation regardless of the active thread. You can select all the variables and objects to watch their behavior in this pane. The Watch pane displays the selected item, its value and the type for tracking, regardless of the active context.

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The Watch pane by default contains three tabs labeled Watch 1 through Watch 3. You can add as many tabs as you want. Use the Watch panes to monitor values of variables regardless of the current context. You can add variables from the Source or Local window and by drag-and-drop. To add a Watch tab, go to the menu View > Watch > Add New Page. You can also delete the watch tabs. For more information about adding signals to the Watch pane, see Signal Menu on page 10. The following figure illustrates a typical Watch pane:

The figure illustrates the variable, its value, type, and the scope. Using the check box in the scope column, you can tie the variable to a given thread throughout simulation or tie the variable to the currently selected thread in the call stack. This feature is available for all object types, including the design signals. For example, add a variable called x in the Watch pane and select the check box to tie it to a given thread. This variable is displayed throughout the simulation from the same dynamic instance of the scope (active thread) irrespective of the thread being alive or not. By default, this check box is checked. Clearing the check box evaluates the variable in the currently active thread in the call stack. For example, add a variable x from the active thread main during the beginning of simulation. Assume the

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active thread changes to some other thread at a later point of time. The variable x in the Watch pane now refers to the same variable in the dynamic instance of the scope (active thread) but not from the main.

Testbench Debugger Menu Options


A few menu options specific to debugging your testbench programs are available. These options are added to different menus in the main DVE GUI such as View menu, Simulator menu, and the Window menu. The following section explains the new options in different menus.

View Menu
This menu lets you customize your viewing options in the Watch pane. It has a new menu option Watch. Click View > Watch and select the relevant options as described below:
Add New Page Delete Current Page Rename Current Page Edit Variable Lets you add a new tab to your Watch pane. Lets you delete the Watch tab from the Watch pane. Lets you rename your Watch tab. Lets you cut, copy, and paste the variable names in Watch tab.

Signal Menu
This menu lets you add signals to the Watch tab. Go to Signal > Add to Watches > Watch to add a signal for monitoring.

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Simulator Menu
After you start the simulation, you can use menu commands to run and control the simulation. Select the following commands to control the simulation:
Step In Testbench Step Out Step in ActiveThread Stops at the next executable line in the testbench for Native Testbench (NTB), OpenVera, and SystemVerilog testbenches. Steps to the next executable line outside of the current function or a task. Stops at the next executable line in the current active thread.

Alternatively, you can use all the simulator menu options from the toolbar directly using the following icons in the interface.
Step in any testbench thread Step out

Step in active thread

Note: Hold the mouse over the button to display the tool tip.

Window Menu
This menu lets you select or clear the following panes to debug your testbench programs. To enable the panes, select Window > Pane and then select the relevant option to enable it.
Stack Local Lets you add a Stack pane to your DVE top-level window. Lets you add a Local pane to your DVE top-level window.

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Watch

Lets you add a Watch pane to your DVE top-level window.

Setting Testbench Debugger GUI Preferences


You can set your preferences to customize the interactive Testbench debugger using the Application Preferences dialog. To set the testbench debugger GUI preferences 1. Select Edit > Preferences, then select Testbench Settings to display the Testbench Preferences screen as follows:

2. Set the following preferences, as appropriate: - Watch array elements display limit - Sets the maximum number of elements that the GUI can show for a large array when it is expanded in Local pane and Watch pane. - Stack depth display limit - Sets the maximum levels of stacks for Cbug. 3. Use the checkboxes to do the following:

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- Enable testbench debugging for interactive design - By default, this option is enabled. Clear this check box to disable the Testbench Debugger panes in the DVE main window. This will disable step in testbench and the programs will not be dumped and shown in the Hierarchy pane. However, you can still open the testbench source files manually and set line break points but you cant see the testbench signals. - Share hierarchy and stack views in a dockable pane - By default, this option is enabled to make the Stack pane available to you in a dockable pane. Clearing this check box opens the Stack pane in a separate window. - Share delta and local views in a dockable pane - By default, this option is enabled to make the Local pane available to you in a dockable pane. Clearing this check box opens the Local pane in a separate window.

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A
Menu Bar and Toolbar Reference
This chapter describes the Menu bar and toolbar options and Command line options.

Menu Bar Reference


This section provides an overview of the following TopLevel window menus: File Menu Edit Menu View Menu Simulator Menu Signal Menu

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Scope Menu Trace Menu Window Menu Help Menu

File Menu
The following items comprise the File menu:
Open Database... Displays the Open Database dialog box, which enables you to select and open simulation database (VCD or VPD) files for post-processing. Displays the Close Database dialog box, which enables you to close an open simulation database (VPD) file. Loads the previously opened database. Displays the Open Source File dialog box, which enables you to select and display a source file in the Source view. Closes the source file displayed in the active Source view or window. Saves values according to the selection: Tabular List Event Based List Memory Contents Displays the Execute Tcl Script dialog box, which enables you to select and source a Tcl script. Displays the Load Session Dialog, which enables you to load a saved session. Displays the Save Session dialog box, which enables you to save the current session. Prints to printer or file the contents of an active wave, list, or Schematic view.

Close Database...

Load Waveform Updates Loads the waveforms updates. Reload Databases Open File

Close File Save Values

Execute Tcl Script... Load Session... Save Session...

Load Last Auto-Session Loads the previously saved session. Print

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Recent Databases Recent Tcl Scripts Recent Sessions Close Window Exit

Displays a list of recently opened databases to choose from. Displays a list of recently run scripts to choose from. Displays a list of recently opened sessions to choose from. Closes the currently active pane in the TopLevel window. Exits DVE.

Edit Menu
The following items comprise the Edit menu:
Cut/Copy/Paste/ Copy works on any text. If the copy function can determine the Paste From/ text to be an object, copy will copy the object, Otherwise it will Delete copy the selected text. Copied text can be pasted in any widget that supports text, for example an editor or the DVE command line. Object copies work in widgets, such as DVE panes, which support DVE objects that sort DVE objects such as any DVE panes. Note:Cut and Delete work only on DVE objects and some windows and are limited to some windows, such as the Wave, List, and Memory views. Paste From generates a list of clipboard objects copied from. Expand By Levels > Provides the following submenu: All Expands all items for all levels under the currently selected item. Note: this can take a long time if executed at the root level of a huge design. 2 Expands 2 levels of child items from currently selected item. 3 Expands 3 levels of child items from currently selected item. 4 Expands 4 levels of child items from currently selected item. 5 Expands 5 levels of child items from currently selected item. Expands all child items under all parents regardless of what item is selected.

Expand All

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Collapse Parent Collapses to the parent of the currently selected item. If no item is selected, no action is taken. Collapse All Synchronize Selection Collapses all children to the top most parent regardless of what item is selected. Selection is not global. You can have different items selected in different panes at any time. Synchronize Selection allows you to sync up all panes to one selection. For example, if you have a signal selected in the Wave window but its parent scope is not shown in the Hierarchy window, clicking on Synchronize Selection will cause the parent scope of the signal to be highlighted in the Hierarchy window and also that signal will be highlighted in the Data pane and any other pane where it exists. This functionality is particularly useful in the Schematic window.

Select by Levels Provides the following submenu: All Selects all items for all levels under the currently selected item. Note: this can take a long time if executed at the root level of a huge design. 2 Selects 2 levels of child items from currently selected item. 3 Selects 3 levels of child items from currently selected item. 4 Selects 4 levels of child items from currently selected item. 5 Selects 5 levels of child items from currently selected item. Select All Find... Find Next Find Previous Selects all objects in pane or window. Displays the Find dialog box. Active if any text exists in find dialog box or find menu line edit. If clicked, finds next occurrence of the text in the active pane. Similar to Find Next but finds previous occurrence of text.

Go To Address... Displays a dialog box in which you can enter an address. This menu option is active if the Memory view is open and populated. Search for Signals/ Instances... Displays the Search for Signals dialog box. Use this to find any object that exists in the opened and current database. If the object is not loaded, this dialog box will attempt to load it.

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Create Marker

Creates a marker in the Wave view. This is only active if a Wave pane exists in the TopLevel window for which the Edit menu is activated. If a Wave pane exists, clicking this menu option puts you in create marker mode. A white hashed marker is created and it follows the mouse in the Wave pane. The marker is placed at the location of the next left mouse-click. The marker will be placed on the next Left Mouse Click. Displays the Marker dialog box (See Cursors and Markers on page 19). Provides a dynamic submenu. The submenu contains all markers available in the current active Wave pane if present. Click on any marker shown to see the marker in the center of the Wave view. If no markers are present in the current window, the submenu will be empty. Provides a dynamic sub menu. The submenu contains all markers available in the current active Wave pane if present. Click on any marker in the submenu to delete it. If no markers exist, the submenu will be empty. Provides a dynamic submenu. The submenu contains all markers available in the current active Wave pane if present. Click on any marker shown to select the marker, then click the desired location in the Wave pane to move the marker. If no markers are present in the current window, the submenu will be empty. Sets a currently selected marker as the reference marker for displaying marker values in relation to other markers. This is useful for the next menu item. Displays Absolute, Adjacent, or Relative values for signals at a selected marker. See Cursors and Markers on page 19. Displays the Preferences dialog box (See Setting Display Preferences on page 10).

Markers... Go To Marker

Delete Marker

Move Marker

Set Reference Marker Show Marker Values Preferences...

View Menu
The following items comprise the View menu:
Selection Tool Used for schematic views. Changes the mouse behavior so leftclicking and dragging selects objects. Left-click on a single object selects it. Ctrl-Left-click adds objects to the selected set. Left-click and drag creates a box. Everything inside the box will be selected.

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Zoom In Tool

Used for Schematic views. Changes the mouse behavior so Leftclick zooms in. Left-click drag creates a box that will become the new view extents for the schematic.

Zoom Out Tool Used for Schematic views. Changes the mouse behavior so Leftclick zooms out. Pan Tool Used for schematic views. Changes the mouse behavior so leftclicking and dragging s pans all the objects in the schematic view. For example, Left-click drag down, moves all the objects down in the view. Choosing this menu item also changes the cursor to a hand. Click the toolbar selection arrow to change the cursor back to normal.

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Zoom>

Creates a sub menu for all zoom operations. These menu items are only applicable for Schematic and Wave panes. Zoom Full Fits all viewable objects into the current view. Zoom In Makes objects in current view twice as big so fewer objects will be viewable. Zoom Out Makes objects in current view twice as small so more objects will be viewable. Zoom Fit Selection Changes view to center on the selected set of schematic objects and so all selected objects are visible in the current pane. Zoom Fit Highlight Same as Zoom Fit Selection but for highlighted schematic objects. This option is available if there are highlighted objects. Pan To Selection Moves the view so the selected set of schematic objects is centered and viewable in the current pane. It does not change the zoom. Pan To Highlight Same as Pan To Selected but for highlighted schematic objects. Zoom to Cursors If the two Wave view cursors are present, this puts the area between the cursors in the view with each cursor at opposite sides of the view. Zoom to Time Range... Displays a dialog box for entering a time range, then zooms to that time range. Back in Zoom and Pan History Iterates through saved zoomed or panned views for current pane. When you change a zoom or a pan in a view, DVE stores the previous view so you can retrieve it. Forward in Zoom and Pan History If you have gone backward in zoom/pan history, this menu item provides an easy way to go to the next view. Clicking this item will eventually get to the current view. Named Zoom and Pan Settings... Displays a dialog box that allows you to choose from any views that you saved with a name. Displays a dialog box that allows you to change the timescale used in the debugger.

Set Time Scale...

List Window Displays a dialog box that allows you to change the strobe time Time Range... range in the List pane. This item is available only if a List pane is open.

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Delta Cycle >

Creates a submenu of delta cycle related options. This is available only if delta cycle information exists in the value change database. Expand Time Expands at the C1 time to show the delta cycles within that time. Collapse Time Collapses the expanded delta cycle display at C1 time. Collapse All Collapses any expanded delta cycle displays regardless of where C1 is. Associates with base.

Associate With> Go to Beginning Go to End Go to Time

Quick way to go to the start of simulation (C1) time (usually 0). This moves the C1 cursor and changes the view in the Wave pane to show the beginning of simulation time. Same as above but for the end of simulation time. Displays a small dialog box to allow you to change the C1 time in the debugger. This changes the view in the Wave pane to center at the new C1 time.

Link C1 to Sim Sets the debugger time with the current interactive simulation Time time. This item is available only in an interactive debug session. Move C1 to Sim Time Use Global Time (C1) Increase Row Height Synchronizes the debugger time with the current interactive simulation time. This item is available only in an interactive debug session. Keeps C1 in current toplevel with the global C1 marker. Increases the height of all traces in the Wave view.

Decrease Row Decreases the height of all traces in the Wave view. Height Set Default Row Height Watch Resets the height of all traces in the Wave view to the default. Add New Page Delete Current Page Rename Current Page Edit Variable

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Toolbars >

Creates a submenu of checkboxes that allows you to turn on or off any of the following toolbars. Edit File Scope Trace Window Signal Simulator Time Operations Zoom Zoom and Pan History

Simulator Menu
The following items comprise the Simulator menu.
Setup... Displays the Simulation Setup dialog box to allow modification of default simulation runtime settings. . Note, this does not allow you to control simulator compile settings. See Running a Simulation from the GUI on page 10. Rebuilds a Verilog-only simulation by executing the csrc/Makefile, then starts the simulation. This does not work for VCS MX or VHDL. Runs the simulation until a breakpoint is hit, the simulation finishes, or for the duration specified in the Set Continue Time dialog box or toolbar time entries. Stops a running simulation (same as the UCLI stop command). Moves the simulation forward by stepping one line of code, irrespective of the language of the code. This is the same as the UCLI Step command. For VHDL, Verilog, and TB code, next steps over tasks and functions. Advances in CBug code. Stops at the next executable line in the current active thread.

Rebuild and Start

Start/Continue

Stop Step

Next Next in CBug Step In Active Thread

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Step In Testbench

For Native TestBench (NTB) OpenVera and SystemVerilog testbenches, stops at the next executable line in the testbench. Steps to the next executable line outside of the current function or a task. Stops the currently running simulation and restarts it with the current simulation setup. This retains all open windows and GUI setups. If the simulation is not running it starts it. Displays C-language. SystemVerilog and NativeTestBench testbench stacks. Steps up the current stack. Steps down the current stack. Displays the Breakpoints dialog box that allows you to view, create, edit, enable, disable and delete breakpoints. See Managing Breakpoints in Interactive Simulation on page 13. Brings up a File Browser dialog box that allows the saving of the current state of the simulator as a file name. Brings up a File Browser dialog box that allows you to restore a saved simulation state. Kills a running or stopped simulation (similar to Ctrl-C). Collects all information in the hierarchy. Brings up the Dump Values dialog box to specify signals to dump value change information starting at the current time. See Dumping Signal Values on page 14. Turns on value change dumping at the current time for any selected signal in the active pane. Brings up the Force Values dialog box to allow you to interactive change the value of a signal. See Forcing Signal Values on page 15. Toggles to turn on/off delta cycle dumping starting at the current time. Note that this substantially increases the VPD file size. You should try to limit the time span for dumping delta cycle values.

Step Out Restart

Show stack Move up Stack Move down Stack Breakpoints...

Save State...

Restore State... Terminate Dump Full Hierarchy Add Dump...

Dump Add Force...

Capture Delta Cycle Values

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Continue For Time...

Displays a dialog box to enter a time. The time specifies the duration the simulation runs if no breakpoints are hit. For example, if set to 10, the simulation runs for ten time ticks when you press the Continue toolbar button. You can use the toolbar to do this as well as a shortcut. Displays a dialog box that gives the user a choice of supported periodic update of value change data while the simulator is running. This allows you to see waveforms dynamically as the simulator runs. The smaller the interval the worse the performance. Enable - Enables debugging of C, C++, and SystemC source code. Allows to step in C/C++ code, set breakpoint etc. Show External Functions - Shows user-defined external functions (PLI, DPI, Direct C).

Periodic Waveform Update Interval...

C/C++ Debugging

Signal Menu
The following items comprise the Signal menu:
Display Signal Group > Creates a dynamic submenu to allow manipulation of the visibility of signal groups. New Signal Group - Creates a new signal group. All Turns on visibility for all existing signal groups. Contains toggles for all existing signal groups, so they can be toggled on or off from the submenu. Adds the selected signals to one of the following selections: New wave view Recent (New View) Create New Group Same as Add to Waves but for the List view. New Group Creates a new signal group. The name will be Group<n> where n is one more than the highest numbered existing signal group. The new signal group is created at the top of the signal list. Adds signal to Watch pane. If the selected signal is a memory or MDA, this menu item displays that signal in the memory viewer. If there is no memory viewer, DVE creates one according to the target policy.

Add to Waves

Add to Lists Add to Groups

Add to Watches Show Memory

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Set Insertion Bar Sets the insertion bar above the selected signal in the Wave or List view. This menu item is not available in other windows. If more than one signal is selected, DVE places the insertion bar above the signal closest to the top of the signal list. Insert Divider Sort Signals Set Bus... Inserts a blank divider row in the waveform display. Displays signals by declaration, ascendingly, or descendingly. Displays the Bus/Expression dialog box for managing the bus and expression creation/deletion. See Building Buses and Setting Expressions on page 5-29. Displays the expression dialog box for managing the bus and expression creation/deletion. See Building Buses and Setting Expressions on page 5-29. Creates a dynamic submenu that controls what the Search Previous and Search Next buttons stop on. When the constraint is matched, the C1 cursor moves to that time location. Searching and therefore constraints work only on the selected set of signals. If no signals are selected, searching is not useful. The following constraints are supported: Any Edge (Default) Search stops and positions C1 cursor on the next or previous edge found. Rising Search stops and positions C1 cursor on the next or previous rising edge only. Falling Search stops and positions C1 cursor on the next or previous falling edge only. Failure Available only if the signal is an assertion; stops on next or previous assertion failure. Success Available only if the signal is an assertion; stops on next or previous assertion success. Match Available only if the signal is an assertion; stops on next or previous assertion success. Mismatch Available only if the signal is an assertion; stops on next or previous assertion mismatch. X Value Searches for any value that contains x. Signal Value... Displays a small dialog box that allows you to enter a specific value as the constraint. If the value is found, the search will stop and position C1 where the signal takes on the entered value. Values must match the radix that is currently selected for the signal. Using the constraint specified above, searches backwards in time for the constraint.

Set Expressions... Set Search Constraints>

Search Backwards

Search Forward Using the constraint specified as above, searches forward in time for the constraint.

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Compare...

Displays the Signal Compare dialog box that allows you to specify a signal compare operation. See Comparing Signals, Scopes, and Groups on page 5-26. Available only if a signal compare has been performed. Shows the results of the last signal compare. Overlay signals in an overlay signal group. Unoverlay the overlaid signals. Displays the Shift Time dialog box to specify the parameters to shift a signal in time. Creates a submenu giving reasonable choices for radix changes for the selected signal. Changing radix on a signal is global and will change the radix wherever the signal is displayed in the debugger. User Defined > Allows you to specify and edit user-defined types from a dialog box. See Managing User-Defined Radices on page 5-12. Enumerated Type ASCII Binary Octal Decimal Hexadecimal Unsigned Signed magnitude Ones Complement Twos Complement Strength Default Applies default properties to the selected signal. Displays the Signal Properties dialog box that allows you to manipulate the visual look of a signal.

Show Compare Info Analog Overlay Unoverlay Shift Time... Set Radix >

Default Properties Properties...

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Scope Menu
The following items comprise the Scope menu:
Show Source Shows the source of the object selected. If multiple objects are selected, shows the source of the first object in the selected set. If the Use checkbox is checked, the Source view used is the current open Source view. If no Source view exists, DVE creates a new Source view according to the target policy.

Show Schematic Same as above except that it shows the object in a Design Schematic pane. Show Path Schematic Move Up to Parent Same as above except that it shows the object in a Path Schematic pane. Moves the selection in the Source view up one level of hierarchy from the scope of the currently selected line. If the current line is the top of the hierarchy or no line is selected, this item is not available. Moves the selection to the start of the definition of the currently selected object. Note that in the Source view, this only works if the object itself is selected. It does not work if the entire line is selected and more than one token is selected on that line. Moves to the previous view of source information in the current Source view. DVE maintains a history of Source view views, so that it is easy to go back to a previous view of the source. This is useful for large source files and reduces the need for scrolling. Same as above but moves forward in the source view history if you have previously gone backwards.

Note: The following menu items affect the currently active Source view.

Move Down to Definition

Back

Forward

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Show >

Creates a dynamic submenu that allows navigation to certain types of relative source lines based on the selected object type. Definition Shows the definition of the selected object. Current Scope Changes the selection to the first line of the current scope. Assertion If object is an instance of an assertion, this menu item changes the source view to the definition of the selected assertion. Unit Binding For OVA assertion instances, this menu item changes the source view to the location where the assertion is bound to a module with a bind statement. Entity If the current selection is in a VHDL architecture, this menu item changes the source view to the architecture's entity. Architecture If the current selection is in a VHDL entity, this menu item changes the source view to the entitys architecture. Macro - Shows the value and information of the selected macro in a separate source window. The Source window contains all the queried macros in it. Macro Definition - Shows the definition of the selected macro in the Source window. Displays a text editor based on your Editor source preference setting (vi editor is default). DVE preloads the editor with the source file that is in the currently active DVE Source pane and positions it on the same selected line. If no file is open in the Source view or a different kind of DVE pane is active, this menu item is not available. Same as above except that the source of the parent instance is preloaded in the text editor. Expands fanin or fanout of the current path to one additional level from the selected object. Available for Path Schematic only - Displays the Fanin/Fanout dialog box in which you specify fanin/fanout parameters for the path schematic.

Edit Source

Edit Parent Expand Path Add Fanin/ Fanout...

Annotate Values Allows you to toggle signal annotation on and off for the current scope in Source/Data/Schematic/Path Schematic views. Annotation allows you to see values within the context of the display. For example in the Source view. The annotation will be below the source text for variables while in the schematic, the annotation will be on pins or nets.

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Properties

Available for Schematic and Path Schematic only - pops up a dialog box that shows all available properties for the currently selected schematic or path schematic object.

Trace Menu
The following item comprises the Trace menu:
Trace Assertion Automatically traces the assertion and displays the results in the current or a new Wave view. This menu item is active only if an assertion is selected in the currently active pane and certain conditions are met (libovadebug.so must be available). If a specific assertion attempt is selected, that attempt will be traced. If you select no specific attempt, DVE traces the first attempt. The assertion trace gives detailed debugging information for a specific assertion attempt so you can easily pinpoint the expression in the assertion that failed. Assertion Attempts... Displays the Assertion Attempts dialog box. If the selected object in the currently active pane is an assertion, the dialog box will be populated with all attempt information for that assertion. If the selected object is not an assertion, the dialog box is empty. This menu item will be active if the object selected in the currently active pane is a variable or signal. For this capability to work, the design must be compiled with one of the -debug options and an mdb library must exist. Finds the active driver of the object, shows the driver in the drivers/loads pane and shows the driver in the reusable source pane in the current window. If no window is present, DVE creates one. If a drivers pane already exists, the new trace information is added to it. Trace Loads Drivers/Loads Same as above except for loads of the signal. Creates a dynamic submenu that allows you to navigate and manage drivers/loads displays. See Tracing Active Drivers and Loads.

Trace Drivers

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Follow Signal

Creates a dynamic list of signal instances of a signal selected in the source pane. Selects an instance to go to it. Creates a dynamic submenu that allows you to highlight and manage highlighted objects in the Schematic and Path Schematic panes. Recent Color - Highlight any currently selected objects in the current view with the recently used color. Clear Selected Removes all highlight color from the selected objects in the currently active Schematic or Path Schematic pane. Clear All Remove all highlights regardless of whether the objects are selected or not in the currently active Schematic or Path Schematic pane. Clear by Color - Remove the highlights from objects highlighted with a color. (The color is selected in the sub menu.) Follows the selected signal through the design. Stops following action of the Follow Signal command. Trace the X value in the selected signal to its source signals to identify the signals that caused the X value.

Note: The following menu items are for Schematic and Path Schematic panes. Highlight >

Spot Signal Path Stop Signal Spotting Trace X

Window Menu
The following items comprise the Window menu:
New > Opens a new instance of one of the following window selections according to current target criteria: Source View Schematic View Path Schematic View Wave View List View Memory View

A-17

Set This Frame Sets the currently active frame as the target for one of the Target For > following selections: Source View Schematic View Path Schematic View Wave View List View Memory View Panes > Displays the selected pane in the active TopLevel window. Console Hierarchy Data Signal Groups DriverLoad Stack Local Watch Assertion

New Top Level Opens a new TopLevel frame displaying one of the following Frame > selections: Empty Assertion + Hierarchy Hierarchy + Data Hierarchy + Data + Console Console Load Default Layout Load Layout Returns the currently active TopLevel frame to the default layout. Loads a layout session. Reset Layout - Resets the layout to the initial layout. From File - Loads a pre-saved layout session file. Saves the current DVE layout. To default - Saves the current DVE layout as ~/.synopsys_dve_default_layout.tcl. When DVE restarts, it uses this default layout instead of the last layout when you have exited DVE. To File - Saves the current DVE layout to a layout session file. Arranges all the non-docked panes in current toplevel window. Cascade - Display windows in cascade format. Tile - Display windows in tile format. Vertical - Display windows in vertical tile format. Horizontal - Display windows in horizontal tile format.

Save Current Layout

Arrange

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Dock in New Row >

Positions the currently active window or pane in a new row of the current TopLevel frame according to one of the following selections: Left Right Top Bottom Positions the currently active window or pane in a new column of the current TopLevel frame according to one of the following selections: Left Right Top Bottom Undocks the selected window from the TopLevel window. Moves to new Top level window. Sets the title of the top level window. List of current TopLevel windows.

Dock in New Column >

Undock Move To Set Top Level Title Current Window List

Help Menu
The following items comprise the Help menu:
DVE Help A Quick Start Verilog Example A Quick Start Mixed Example About Opens the DVE documentation. Loads an example design. Loads an example design when VCS MX is running.

Tutorial for Mixed Example Loads an example design for VCS MX. Displays DVE version and copyright information.

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Keyboard Shortcuts
File Command Shortcuts
Ctrl+O Ctrl+W Ctrl+U Open database Close window Load Waveform updates

Edit Command Shortcuts


Ctrl+X Ctrl+C Ctrl+V DEL Ctrl+Y Ctrl+A Ctrl+F3 F3 Shift+F3 Ctrl+G Ctrl+H Cut Copy Paste Delete Synchronize selection Select all Fnd Find next Find prev Go to address Search for signals/ instances

View Command Shortcuts


ESC = F + O Selection tool Zoom in tool Zoom out tool Zoom full Zoom in Zoom out

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Ctrl+T Ctrl+Alt+T Ctrl+Q

Zoom fit selection Zoom fit highlight Zoom to cursors

A-21

Simulator Command Shortcuts


F5 F11 F10 Ctrl+F10 F12 Ctrl+F11 F9 Ctrl+F5 Start/Continue Step Next Next in CBug Step in active thread Step in testbench Step out Restart

Signal Command Shortcuts


Ctrl+4 Ctrl+5 Ctrl+6 Ctrl+7 < F4 Add to waves Add to lists Add to watches Show memory Search backward Search forward

Scope Command Shortcuts


Ctrl+1 Ctrl+2 Ctrl+3 F8 Shift+F8 Show source Show schematic Show path schematic Move up to parent Move down to definition

Trace Command Shortcuts


Ctrl+D Trace drivers

A-22

Ctrl+L Ctrl+E Ctrl+Shift+M Ctrl+M

Trace loads Highlight recent color Clear selected Clear all

Help Command Shortcuts


F1 Help

Toolbar Reference
This section describes all toolbar text fields, menus, and icons. You can drag and drop toolbars into any location in a TopLevel DVE window toolbar using the toolbar handles. To toggle the display of toolbars on and off, select Edit > Toolbars, then select the desired toolbar.

Edit
The following items comprise the Edit toolbar:
Icon Description

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Cut, Copy, Paste, Delete

Copy works on any text. If the copy function can determine the text to be an object, copy will copy the object, Otherwise it will copy the selected text. Copied text can be pasted in any widget that supports text, for example an editor or the DVE command line. Object copies work in widgets, such as DVE panes, which support DVE objects that sort DVE objects such as any DVE panes. Cut and Delete works only on DVE objects and some windows and are limited to some windows, such as the Wave, List, and Memory views. Displays the Search for Signals dialog box. Use this to find any object that exists in the opened and current database. If the object is not loaded, this dialog box will attempt to load it. Selects string to search for, then press Enter to search.

Search for Signals/Instances

Find
Active if any text exists in the Find dialog box or the Find menu text box. If clicked, finds the previous or next occurrance of the text in the active pane.

Find Previous/Next

File
The following items comprise the File toolbar:
Icon Description

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Open Database or File

Displays the Open Database or Open File dialog box, depending on the DVE window displayed, and enables you to select and open a VPD file. Displays the Close Database dialog box, which enables you to close an open simulation database (VPD) file. Loads waveform updates

Close Database

Load Waveform Updates


Prints to printer or file the contents of an active wave, list, or Schematic view.

Print

Scope
The following items comprise the Scope toolbar:
Icon Description

Displays the currently active scope signal values at the current time in the Source view.

Annotate Values
Moves the selection in the Source view up one level of hierarchy from the scope of the currently selected line. If the current line is the top of the hierarchy or no line is selected, this item is not available. Moves the selection to the start of the definition of the currently selected object. Note that in the Source view, this only works if the object itself is selected. It does not work if the entire line is selected and more than one token is selected on that line.

Move Up One Level

Move Down One Level

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Move Back/Forward in List of Scopes

Back or forward arrow moves to the previous view of source information in the current source view or forward in the source view history if you have previously gone backwards. DVE maintains a history of Source view, so that it is easy to go back to a previous view of the source. This is useful for large source files and reduces the need for scrolling.

Trace
The following items comprise the Trace toolbar:
Icon Description

Trace Drivers/Trace Loads

This menu item is active if the object selected in the currently active pane is a variable or signal. For this capability to work, the design must be compiled with one of the -debug options and an mdb library must exist. When clicked, this finds the active driver of the object, shows the driver in the Drivers/ Loads pane and shows the driver in the reusable Source pane in the current window. If no window is present, DVE creates one. If a drivers pane already exists, the new trace information is added to it. Finds the next or previous driver or load or the next or previous driver or load in the current instance respectively.

Find Next/Previous

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View
The following items comprise the View toolbar:
Icon Description

Opens a new Source pane and display source for the selected object.

Show Source
Opens a new Schematic pane.

Show Schematic
Opens a new Path Schematic pane.

Show Path Schematic


Opens a new Wave pane or display a previously opened pane.

Show Wave
Opens a new List pane or display a previously opened pane.

Show List
Opens a new Memory pane.

Show Memory
Adds signal to the Watch pane.

Add to Watches

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Opens the Assertion pane.

Assertion

Signal
The following items comprise the Signal toolbar:
Icon Description

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Search

Backward or forward arrow launches search in time for the constraint selected in the listbox. Any Edge (Default) Search stops and positions C1 cursor on the next or previous edge found. Rising Search stops and positions C1 cursor on the next or previous rising edge only. Falling Search stops and positions C1 cursor on the next or previous falling edge only. Failure Available only if the signal is an assertion; stops on next or previous assertion failure. Success Available only if the signal is an assertion; stops on next or previous assertion success. Vacuous - Available only if the signal is an assertion; stops on the next or previous vacuous success. Signal Value ... - Displays a small dialog box that allows you to enter a specific value as the constraint. If the value is found, the search will stop and position C1 where the signal takes on the entered value. Values must match the radix that is currently selected for the signal. Set the number of matched values to seek for one search backward/forward operation by clicking the search icon.

Set number of seeks

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Simulator
The following items comprise the Simulator toolbar:
Icon Description

Start/Continue

Runs the simulation until a breakpoint is hit, the simulation finishes, or for the duration specified in the Set Continue Time dialog box or toolbar time entries. Runs the simulation for the specified time, then stops.

Run for Specified Time


This icon is active when the simulation is running. Click to stop the simulation.

Stop
For VHDL, Verilog, and TB code, next steps over tasks and functions.

Next
Moves the simulation forward by stepping one line of code, irrespective of the language of the code. This is the same as the UCLI Step command. Steps to the next executable line in the current active thread.

Step In

Step In Active Thread


For Native TestBench (NTB) OpenVera and SystemVerilog testbenches, stops at the next executable line in the testbench.

Step In Any Testbench Thread


Steps to the next executable line outside of the current function or a task.

Step Out

A-30

Restart

Stops the currently running simulation and restarts it with the current simulation setup. This retains all open windows and GUI setups. If the simulation is not running it starts it.

Time Operations
The following items comprise the Time Operations toolbar:
Icon Description

Set Time and Precision

Displays current time of the C1 cursor. Set the current time by entering a new time in this field Displays the time units for displaying simulation data. Select View > Set Time Scale to set time units and precision.

Zoom
The following items comprise the Zoom toolbar:
Icon Description

Selection Tool

Used for schematic views. Changes the mouse behavior so left-clicking and dragging selects objects. Left-click on a single object selects it. Ctrl-Left-click adds objects to the selected set. Left-click and drag creates a box. Everything inside the box will be selected. Zoom In Makes objects in the selected area fill the pane. Zoom Out Makes objects in current view fit the selected area.

Zoom In/Out

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Pan Tool

Used for schematic views. Changes the mouse behavior so left-clicking and dragging pans all the objects in the schematic view. For example, Left-click drag down, moves all the objects down in the view. Choosing this menu item also changes the cursor to a hand. Click the toolbar selection arrow to change the cursor back to normal. Zoom Full Fits all viewable objects into the current view.

Open Database or File

Zoom In 2x Makes objects in current view twice as big so fewer objects will be viewable. Zoom Out 1/2 Makes objects in current view twice as small so more objects will be viewable. Zoom Fit Selection Changes view to center on the selected set of schematic objects and so all selected objects are visible in the current pane.

Zoom and Pan History


The following items comprise the Zoom and Pan History toolbar:
Icon Description

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Go to Zoom and Pan Settings

Back in Zoom and Pan History Back arrow iterates through saved zoomed or panned views for current pane. When you change a zoom or a pan in a view, DVE stores the previous view, so you can retrieve it. Forward in Zoom and Pan History If you have gone backward in zoom/pan history, the forward arrow provides an easy way to go to the next view. Clicking this item will eventually get to the current view. Named Zoom and Pan Settings Goes to a saved named view selected in the pulldown.

Zoom to cursors

Zooms between markers C1 and C2 in waveform.

Using Context Sensitive Menus


In any window, right-click to display a context-sensitive menu, then select a command. The Hierarchy Browser context sensitive menu is as follows:
Command Copy Add to Waves Add to Lists Show Source Expand By Levels Expand All Description Copies selected text. Displays the selected signal or signals in the Wave view. Displays the selected signal or signals in the List view. Displays source code in the Source view for the selected scope. Allows expansion by multiple levels with a single action. Expands the entire hierarchy at once. There may be a delay getting the hierarchy from the simulation when working interactively.

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Command Collapse Collapse All Select Scope By Levels Select All

Description Collapses the selected scope. Collapses all expanded scopes. Allows you to select scopes by levels. You can select more than one level at a time. Selects all that are visible in the hierarchy (does not implicitly expand)

Using the Command Line


Use the command line to enter DVE and Unified Command Line Interface (UCLI) commands. The table below describes these command. Commands marked with an asterisk (*) are UCLI commands.
Command open_db close_db open_file exit Design Query: show* drivers* loads* fanin search Simulator: open_sim start* step* next* Setup Simulator executable and arguments Starts tool execution Advances the tool one statement Advances the tool stepping over tasks and functions Displays design information for a scope or nested identifier Obtains driver information for a signal/variable Obtains load information for a signal/variable Extracts the fanin cone of the specified signal(s) Locates design objects whose names match the name specification you provide Description Opens a database file Closes a database file Opens file Exits application

A-34

run* finish* restart* Breakpoints: stop Navigation: scope* thread* stack* listing* add_schem add_source get* force* release* call* sexpr* vbus* add_group add_list add_mem add_pathschem add_watch add_wave delete_group delete_list delete_watch delete_wave compare view

Advances the tool and stop Allows the tool to finish then return control back to UCLI Restarts tool execution, and keeps the setting in the last run Adds or displays stop breakpoints Gets or changes the current scope Displays thread information or move the current thread Displays thread information or move the call stack Displays source text Shows scope in Schematic view Shows signal/scope in Source view Obtains the value of a signal/variable Forces or deposit a value on a signal/variable Releases a variable from the value assigned using 'force' Executes a system task or function within the tool Evaluates an expression in the tool Creates, deletes or display a virtual object Adds signals to Group Adds signals to the List view Adds memory to the Memory view Shows path schematic for signal(s)/ scope(s) Adds signals to Watch view Adds signals to the Wave view Deletes signals from given group Deletes signals from given list view Deletes signals from global watch view Deletes signals from given wave view Compares signal/scopes Opens, closes or lists view

Signal/Variable/Expression:

Signal Value and Memory:

A-35

dump* memory* add_mem Session Management: save* restore* save_session open_session Help Routines: help alias* unalias* config* Macro Control: do* onbreak* onerror* resume* pause* abort* status* Misc.: ace* cbug* coverage* power quit* senv* setenv* sn*

Creates/manipulates/closes dump value change file information Loads/writes memory type values from/to files Adds memory to the Memory view Saves simulation state into a file Restores simulation state saved in a file Saves session Opens session Lists basic commands. Use -all for listing all commands. Creates an alias for a command Removes one or more aliases Displays/sets current settings for configuration variables Evaluates a macro script Specifies script to run when a macro hits a stop-point Specifies script to run when a macro encounters an error Resumes execution of a macro file Pauses execution of a macro file Aborts evaluation of a macro file Displays the macro file stack Evaluates analog simulator command Debugs support for C, C++ and SystemC source files Evaluates coverage command(s) Powers measure Exits application Displays one or all synopsys::env array elements Sets the value of a system environment variable Displays the Specman prompt when used without arguments, and executes e code commands when they are entered as optional arguments. Disables/enables timingcheck upon an specified instance/port at runtime

tcheck*

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virtual

Creates, deletes or displays a virtual object

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Unified Command Line Interface User Guide


Version C-2009.06 Beta December 2008

Comments? E-mail your comments about this manual to: vcs_support@synopsys.com.

Copyright Notice and Proprietary Information


Copyright 2008 Synopsys, Inc. All rights reserved. This software and documentation contain confidential and proprietary information that is the property of Synopsys, Inc. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Synopsys, Inc., or as expressly provided by the license agreement.

Right to Copy Documentation


The license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Licensee must assign sequential numbers to all copies. These copies shall contain the following legend on the cover page: This document is duplicated with the permission of Synopsys, Inc., for the exclusive use of _________________________________ and its employees. This is copy number______.

Destination Control Statement


All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the readers responsibility to determine the applicable regulations and to comply with them.

Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.

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1
Unified Command Line Interface (UCLI) 1
The Unified Command Line Interface (UCLI) provides a common set of commands for Synopsys verification products. UCLI is compatible with TCL 8.3 and any TCL command can be used with UCLI. VCS/VCS-MX simulation in 32 bit mode uses 32 version of TCL to support UCLI, while VCS/VCS-MX simulation in 64 mode supports TCL 64 bit version. Supporting 64 bit integer arithmetic in UCLI is possible only with TCL 64 bit.

Running UCLI
UCLI can be used for debugging your design in either of two modes: In non-graphical mode, UCLI can be invoked at the prompt during runtime.

Unified Command Line Interface (UCLI) 1-1

In graphical mode, UCLI can be invoked at the command console of DVE in interactive mode only (not in post-processing). UCLI commands are interspersed with gui commands when running in graphical mode.See the Discovery Visual Environment User Guide for information

Note: UCLI is not compatible with VirSim.

UCLI with VCS, SystemVerilog, and NTB (OV and SV)


To run UCLI, you must enable it at compile time. You can use the debug or -debug_all argument to enable UCLI, or set UCLI as the default command line interface. To run VCS with UCLI, enter VCS commands with UCLI enabling command line options:
vcs (-debug | -debug_all) [-sverilog] [-ntb] [VCS_options] design.v [testbench_files] simv -ucli [runtime_options]

The following constructs are not yet supported for UCLI with an NTB (SV) core. Clocking domains are not supported. Virtual interfaces are not supported. Random constraints are not supported.
stop -event on automatic variables are not supported.

Event variables are not supported.

Unified Command Line Interface (UCLI) 1-2

UCLI with VCS MX and VHDL Pure VHDL


To run a VHDL simulation with the UCLI command line debugger, enter the VCS MX commands with UCLI enabling options:
vhdlan design.vhd vcs cfg_tb (-debug | -debug_all) simv -ucli [runtime_options]

Mixed Simulation with Verilog on Top


To run a mixed Verilog/VHDL simulation with Verilog on top and the UCLI command line debugger, enter the commands with UCLI enabling options:
vlogan Verilog_files [options] vhdlan vhdl_filename -vlib Verilog vcs (-debug | -debug_all) [options] design.v simv -ucli [runtime_options]

Mixed Simulation with VHDL on Top


To run a mixed Verilog/VHDL simulation with VHDL on top and the UCLI command line debugger, enter the commands with UCLI enabling options:
vlogan Verilog_files [options] vhdlan vhdl_filename -vlib Verilog vcs cfg_tb (-debug | -debug_all) -verilogcomp "options" simv -ucli -verilogrun "-q" [options]

Unified Command Line Interface (UCLI) 1-3

How to Enable UCLI Debugging Compile-Time Options


-debug Enables command line debugging option. This flag does not enable line stepping. -debug_all Enables command line debugging option including line stepping. -ucli Forces runtime to go into UCLI mode by default Also see the following section, Runtime Options , for more information. -gui Compile time option invokes the DVE gui when issued at runtime. -l logFilename Captures simulation output, such as user input UCLI commands and responses to UCLI commands. -i inputFilename Reads interactive UCLI commands from a file, then switches to reading from standard command line input. -k keyFilename Writes interactive commands entered to inputFilename, which can be used by a later simv as -i inputFilename

Unified Command Line Interface (UCLI) 1-4

For a complete description of command line options, see the VCS User Guide and the VCS MX User Guide.

Runtime Options
-ucli Invokes the UCLI debugger command line if issued at runtime. Also see the previous section, Compile-Time Options , for more information.

UCLI Commands
The following briefly describes commands. Note: Command names in the table below are the default alias commands supplied by Synopsys.
Command abort alias call cbug config do drivers Description Halts evaluation of a macro file Creates an alias for a UCLI command. Provides a unified interface to call both verilog/vhdl task/proc Enables debugging of VCS and VCS MX designs that include C, C++, and SystemC modules Displays default settings for users variables. Evaluates a macro script Display a list of signals that drive the indicated signal.

Unified Command Line Interface (UCLI) 1-5

dump

Specify value dump information (files, scopes/ variables, depth to dump, enable/disable dumping, etc.) over the course of the tool processing Finish/end processing in the tool. Force a value onto a variable. Activity in the tool does not override this value (deposit, freeze, clock generation). Return the current value of the specified variable. Display information on all commands or the specific command requested. List n lines of source on either side of the tool active location. If no number is entered, listing shows five lines on either side of the active location. Display the loads for the indicated signal for VCS only (no VHDL support). Loads or writes memory type values from or to files. For VHDL code, next steps over tasks and functions. For Verilog, next=step. Specifies script to run when a macro hits a stop-point Specifies script to run when a macro encounters an error Interrupts the execution of a macro file Release a variable from the value assigned previously using a force command. Restart the tool and stop at time zero. Restores simulation state previously saved to a file using the save command. Restarts execution of a paused macro file from the point where it stopped Advance the tool to a specific point. If some other event fires first then the run point is ignored. Saves the current simulation state in a specified file.

finish force

get help listing

loads memory next onbreak onerror pause release restart restore resume run save

Unified Command Line Interface (UCLI) 1-6

scope

Show or set the current scope to the specified instance. With no arguments the current scope is returned. Show information about your design. You can specify multiple arguments. Display the environment array or query an individual array element. This command displays the result of a VHDL evaluating expression. Execute Specman commands. Display stack information for the NTB OpenVera or SystemVerilog testbench process/thread. Start the tool from within the TCL shell Displays the macro file stack Move the simulation forward by stepping one line of code. step will step into task and functions. Set a stop point in the tool. Display information regarding the current NTB OpenVera or SystemVerilog testbench threads in the tool.

show senv sexpr sn stack start status step stop thread

Using a UCLI Command Alias File


You can use the default alias file supplied with your installation or create a file containing aliases for UCLI commands. This section describes the use of aliases.

Unified Command Line Interface (UCLI) 1-7

Default Alias File


The .synopsys_ucli_prefs.tcl file in your VCS installation directory contains default aliases for UCLI commands. You can edit this file to create custom aliases for UCLI commands. By default, .synopsys_ucli_prefs.tcl looks for the alias file in the following order: UCLI installation dir (for system-wide configuration) Users home directory (for user-specific configuration) Current working directory (for design-specific config)

You can create custom aliases: For all users by editing the file in the tool installation directory For your own use by copying the file and editing it in your home directory For a project by copying the file and editing it in your current working directory

Once the file is located,UCLI loads the file. The following table shows the synopsys UCLI commands and the default aliases.
UCLI Command synopsys::abort synopsys::alias synopsys::call synopsys::change synopsys::config Alias abort alias call change config

Unified Command Line Interface (UCLI) 1-8

synopsys::do synopsys::drivers synopsys::dump synopsys::env synopsys::expr synopsys::finish synopsys::force synopsys::get synopsys::help synopsys::listing synopsys::loads synopsys::memory synopsys::next synopsys::restore synopsys:onbreak synopsys:onerror synopsys:pause synopsys::release synopsys::restart synopsys::run synopsys::save synopsys::scope synopsys::show synopsys::stack

do drivers dump senv sexpr finish force get help listing loads memory next restore onbreak onerror pause release restart run save scope show stack

Unified Command Line Interface (UCLI) 1-9

synopsys::start synopsys::status synopsys::step synopsys::stop synopsys::thread

start status step stop thread

Customizing Command Aliases and Settings


You can customize the UCLI command name aliases and UCLI settings using the .synopsys_ucli_prefs.tcl resource file in the following ways: Modify aliases and settings for all UCLI users by changing default aliases and adding or removing settings in the resource file in the UCLI installation directory. Modify the aliases and settings for use in all of your projects by creating a .synopsys_ucli_prefs.tcl resource file containing new aliases and settings in your home directory. Modify the aliases for use in a specific project by creating a .synopsys_ucli_prefs.tcl resource file containing new aliases and settings in your working directory.

When you open UCLI, it first looks in the installation directory and loads the .synopsys_ucli_prefs.tcl resource file containing command aliases and UCLI settings. UCLI then looks in your home directory ($HOME) and finally in your current directory. If a resource file is found in either or both directories, it's loaded. Each file will add to or modify the previous file's definitions. You need only enter changes to aliases or new or revised settings to customize your UCLI installation.

Unified Command Line Interface (UCLI) 1-10

Creating a Custom Command Aliases


To create an alias command file: 1. Create a file named .synopsys_ucli_prefs.tcl in your home directory or working directory. 2. Enter an alias_name for each command you wish to customize as follows:
synopsys::alias alias_name UCLI_command_name

For example, some default aliases are entered as:


synopsys::alias fetch synopsys::get synopsys::alias run_again synopsys::restart

Note that you need only enter those commands you want to customize. 3. Save the file. If you have saved the file in your home directory, the file contents will add to or subtract from the installation directory file's definitions. If you have saved the file in your working directory, the file contents will add to or subtract from the installation directory file's definitions and the home directorys modifications.

Operating System Commands


To run an OS command from UCLI in post-processing mode to capture the output for processing by Tcl, enter
exec OS_command

Unified Command Line Interface (UCLI) 1-11

In interactive mode OS commands will be run automatically, for example, typing in ls will produce a listing of the current directory. Setting the "auto_noexec" variable in the .synopsys_ucli_prefs.tcl resource file tells tcl not to try to run a UNIX command when it gets an unknown command. You can still use
exec OS_command

from the ucli command prompt to run UNIX commands during a session.

Configuring End-of-Simulation Behavior


The default end-of-simulation behavior is to exit UCLI. That means the ucli process will exit when the tool runs to the end of simulation, hits $finish, or segfaults. To configure UCLI to remain open at end of simulation add the following to your .synopsys_ucli_prefs.tcl resource file: config endofsim toolexit

Using Key and Log Files


Use key and log files when debugging a design to: Record a session Create a command file of the session.

Unified Command Line Interface (UCLI) 1-12

Run a command file created in previous sessions.

Log Files
You can record an interactive UCLI or DVE session in a log file. A log session records both commands entered and system messages. To create a log file, use the -l filename command line option. Example: To record interactive command input and simulation response in a log file, enter:
simv -ucli -l filename.log

Key Files
When you enter UCLI commands (or commands in the DVE Interactive window) you can record these commands in a key file by specifying the -k filename runtime option. You can then rerun the session after modifying the design using the -i input_filename runtime option with this file as its argument. Example: To output commands entered in a session to a key file, enter:
simv -ucli -k output_filename.key

To rerun a session after modifying the design, enter:


simv -ucli -i input_filename.key

Unified Command Line Interface (UCLI) 1-13

Current versus Active Point


When debugging a design, you can use UCLI to display information about the current point in the design and the active point in the simulation. The current point is the scope in the design you have navigated to. The active point is the place the tool has stopped.

Example In the following Verilog design, instance d1 of module dev is instantiated into module top.
module top; reg ri; initial begin $stop; #10 ri=1; end dev di(ri); endmodule module dev (input in); reg r2; always@ in #5 r2=in; endmodule

After compiling, the simulation is started and a stop point is placed at absolute time 15.
user% simv -s -ucli 1 ucli% stop -absolute 15 1

Unified Command Line Interface (UCLI) 1-14

When the tool is run, the simulation stops at the $stop system task in line 6 of module top. The scope command shows that the current scope and the active scope are both top.
ucli% run top.v, 6 : $stop;

ucli% run Stop point #1 @ 15 ns;

When the run command is executed again, the stop point is triggered at time 15, the delay in module dev.
ucli% run Stop point #1 @ 15 ns;

The current scope is still top. However, the active scope is the delay in the module dev.
ucli% scope top ucli% scope -active top.d1

Capturing Output of Commands and Scripts


Use echo and redirect commands to capture the output of commands and scripts, For example:
ucli% echo [show -vars] > vars.list ucli% redirect vars.list { show -vars }

Unified Command Line Interface (UCLI) 1-15

Customizing DVE Setup


You can specify DVE setup options using the .synopsys_dve_usersetup.tcl file and DVE GUI setup options using the .synopsys_dve_gui_usersetup.tcl file during installation. You then set the DVE_USERSETUP_PATH variable during DVE installation using either global shell scripts or by setting the variable directly. You can place the setup file in the users home directory, present working directory, or specify the same components for all users in a common installation To specify DVE options: home_directory/.synopsys_dve_usersetup.tcl current_working_directory/ .synopsys_dve_usersetup.tcl $DVE_USERSETUP_PATH/.synopsys_dve_usersetup.tcl To specify the GUI setup options: home_directory/.synopsys_dve_gui_usersetup.tcl current_working_directory/ .synopsys_dve_gui_usersetup.tcl $DVE_USERSETUP_PATH/ .synopsys_dve_gui_usersetup.tcl

Unified Command Line Interface (UCLI) 1-16

2
UCLI Interface Guidelines
This chapter describes the general guidelines for specifying arguments to simulator commands in UCLI.

Numbering Conventions
Numbers can be expressed in either VHDL or Verilog style. Two styles can be used for VHDL numbers, one for Verilog.

VHDL numbering conventions


The first of two VHDL number styles is:
[ - ] [ radix # ] value [ # ]

UCLI Interface Guidelines 2-1

Indicates a negative number; optional radix Can be any base in the range 2 through 16 (2, 8, 10, or 16); by default, numbers are assumed to be decimal; optional. value Specifies the numeric value, expressed in the specified radix; required. # A delimiter between the radix and the value; the first # sign is required if a radix is used, the second is always optional Example
16#FFca23# 2#1111_1110# -23749 8#7650 -10#23749

The second VHDL number style is:


base "value"

base specifies the base; binary: B, octal: O, hex: X; required value specifies digits in the appropriate base with optional underscore separators; default is decimal; required Example

UCLI Interface Guidelines 2-2

B"11111110" B"1111_1110" "11111110" X"FFca23" O"777"

Verilog numbering conventions


Verilog numbers are expressed in the style:
[ - ] [ size ] [ base ] value

Indicates a negative number; optional size Specifies the number of bits in the number; optional base Specifies the base; binary: b or B, octal: o or O, decimal: d or D, hex: h or H; optional value Specifies digits in the appropriate base with optional underscore separators; default is decimal, required. Example
b11111110 8b11111110 Hffca23 21H1fca23 -23749 27_195_000

UCLI Interface Guidelines 2-3

16'b0011_0101_0001_1111 32'h 12ab_f001

Hierarchical Pathnames
Each of the following HDL objects creates a new level in the hierarchy: VHDL - component instantiation statement - block statement - package Verilog - module instantiation - named fork - named begin - task - function Each level in the hierarchy is also known as a "region."

MultipleLevels in a Pathname
Multiple levels in a pathname are separated by the character specified in the path separator variable that can be set by the user. Allowed path separators are "/", ".", and ":".

UCLI Interface Guidelines 2-4

"." for Verilog naming conventions ":" for VHDL IEEE 1076-1993 naming conventions The default for VHDL and MX is "/". The default for Verilog is ".".

Absolute Pathnames
In VHDL, absolute path starts with the path separator "/", but in Verilog it starts with the top module name. For more flexibility, you can use either way to specify the hierarchical name. Example
top_mod.i1.i2 or top_mod/i1/i2 or top_mod:i1:i2 .top_mod.i1.i2 or /top_mod/i1/i2 or :top_mod:i1:i2 /top_entity/i1/i2 or .top_entity.i1.i2 or :top_entity:i1:i2 top_entity/i1/i2 or top_entity.i1.i2 or top_entity:i1:i2

Note: Since Verilog designs may contain multiple top-level modules, a path name may be ambiguous if you leave off the top-level module name.

Relative Pathnames
Relative pathnames do not start with the path separator, and are relative to the current UI region or scope (the result of a scope command).

UCLI Interface Guidelines 2-5

User should be able to specify path that goes through VHDL generate, V2k generate (both FOR and IF generate), array instance etc.

bit_select/index
VHDL array signals, and Verilog memories and vector nets can be indexed or bit_selected. Verilog uses [<index>] for bit_select but VHDL uses (<index>). MX will allow both ways to specify index or bit select for a Verilog orVHDL object. Note index must be a locally static expression. Example
vlObj[0], vlObj(0), vhObj(0), vhObj[0]

part_select/slice
VHDL array signals, and Verilog memories and vector nets can be sliced or part_selected. Slice ranges may be represented in either VHDL or Verilog syntax, irrespective of the setting of the path separator. Verilog uses [<left_range>:<right_range>] for part_select but VHDL uses (<left_range> TO|DOWNTO <right_range>) for slice. Mx should allow both the syntax for both verilog and VHDL object. Example
vlObj[0:5], vlObj(0:5), vlObj(0 TO 5), vlObj(5 downto 0), vhObj(0 TO 5), vhObj(5 downto 0), vhObj[0:5], vhObj(0:5)
UCLI Interface Guidelines 2-6

vhObj(0 downto 5) is a NULL range vlObj(0 downto 5) is equivalent to vlObj[0:5]

Naming Fields in Records or Structures


For fields in VHDL record signals or system verilog structures, "." will be used as the separator irrespective of whatever path separator is used. So it will have the following form:
object_name.field_name

Generate Statements
VHDL and System Verilog generate statements are referenced in a similar way to indexing/bit-selecting arrays. Example
vlgen[0], vlgen(0), vhgen(0), vhgen[0]

Note: Mixing VHDL syntax with Verilog syntax is allowed as long as the "[" and "]", and "(" and ")" are used in pairs. If not specified in pairs, it is an error. Example
vlObj[0:5), vlObj(0:5], vlObj(0 TO 5], vlObj[5 downto 0)

The usage of "(", "and", "]" are not legal.

UCLI Interface Guidelines 2-7

More Examples on Pathnames


clk Specifies the object clk in the current region. /top/clk Specifies the object clk in the top-level design unit. /top/block1/u2/clk Specifies the object clk, two levels down from the top-level design unit. block1/u2/clk Specifies the object clk, two levels down from the current region. array_sig(4) Specifies an index of an array object. {array_sig(1 to 10)} Specifies a slice of an array object in VHDL syntax. {mysignal[31:0]} Specifies a slice of an array object in Verilog syntax. record_sig.field Specifies a field of a record. {block1/gen(2)/control[1]/mem(7:0)}

UCLI Interface Guidelines 2-8

Specifies a slice of an array object with mixed VHDL and Verilog syntax, three levels down from the current region as part of a nested generate statement. Note the braces added to the path so the square brackets are not recognized as Tcl commands

Name Case Sensitivity


Name case sensitivity is different for VHDL and Verilog. VHDL names are not case sensitive except for extended identifiers in VHDL 1076-1993. In contrast, all Verilog names are case sensitive. This will be preserved as is.

Extended/escaped identifiers
Verilog escaped identifier starts with "\" and ends with a space " ". VHDL extended identifier starts and ends with "\". So both space and "\" will be allowed as delimiter, which implies VHDL extended identifier cannot have space. MX should allow also the ability to specify a verilog escaped identifier in VHDL style (extended identifier) and vice versa.

Verilog escape name VHDL Extended Identifier


"\myvlog " "\myvhdl\"

UCLI supports the following formats for extended identifiers for any command that takes an identifier.

UCLI Interface Guidelines 2-9

{\ext_ident!\ } # Note trailing space.

\\ext\ ident\!\\ # All non-alpha characters escaped

Wildcard Characters
Wildcard characters can be used in HDL object names in some simulator commands. Conventions for wildcards are as follows: * matches any sequence of characters ? matches any single character Note: Wildcards are not supported in VCS 7.2 Beta.

TCL Variables
Global Tcl variables for simulator control variables and user-defined variables can be referenced in simulator commands by preceding the name of the variable with the dollar sign ($) character. The variable needs to be expanded first before passing it along to the simulator.

UCLI Interface Guidelines 2-10

To resolve the conflict with referencing Verilog system tasks that also use ($) sign, Verilog system tasks are to be specified with "\" or enclosed in {}.
Example cli> call \$readmemb("l2v_input", init_pat);

or
ucli> call {$readmemb("l2v_input", init_pat);}

Note: In System Verilog, $root is a keyword.

Simulation Time Values


Time values can be specified as <number><unit>, where unit can be sec, ms, us, ns, ps, fs. A white space is allowed between the number and unit. You can specify the time unit for delays in all simulator commands that have time arguments. For example:
run 2ns stop -relative 10 ns

Unless you specify timebase explicitly using config -timebase, simulation time is based on time precision. Note: UCLI does not read the synopsys_sim.setup file in VCS MX to obtain the value of timebase.

UCLI Interface Guidelines 2-11

By default, the specified time values are assumed to be relative to the current time unless the absolute time option is specified which signifies an absolute time specification.

UCLI Interface Guidelines 2-12

3
Commands
This chapter contains UCLI command definitions. It includes the following sections: Tool Invocation Commands Tool Advancing Commands Navigation Commands Signal/Variable/Expression Commands Tool Environment Array Commands Breakpoint Commands Signal Value and Memory Dump Specification Commands Design Query Commands Macro Control Routines

Commands 3-1

Coverage Command Helper Routine Commands Specman Interface Command

Note: Command names used are the default aliases supplied by Synopsys.

Tool Invocation Commands


This section contains the tool invocation commands. The tool invocation commands are used for invoking the tool.

start
This command is used to start a new simulation from the UCLI prompt. You can use this command to start different tool (see example following this section). This command starts the simulation from time '0'. The optional tool specific command line arguments can be given after the tool name. When executed, this command, Resets all the UCLI configuration values to their default state. Removes all previously set Break Points. Resets all the previously forced variables to default values.

Note:

Commands 3-2

The default end-of-simulation behavior is to exit UCLI shell i.e. UCLI process will exit when the tool (e.g. simv) reaches end-ofsimulation, $finish (in Verilog) or tool dies (simulation crashes or segmentation fault). To prevent this, you need to set 'endofsim' configuration parameter to noexit. For more information, see the configuration commands. Syntax
start <tool_name> [tool related arguments]

tool This is typically a VCS executable name i.e. simv. This option is mandatory. [tool related arguments] All the arguments which simv (or any other tool) supports. Examples
ucli% start simv

Starts tool simv from simulation time '0'. This command displays no output.
ucli% start simv -l simv.log

Starts simv from simulation time '0' with tool related argument '-l'. This command displays no output. //Flow Example
//To start another tool while already in the UCLI TCL shell of one tool ucli% config endofsim noexit ucli% run ucli% start simv_1 ucli% config endofsim noexit ucli% run
Commands 3-3

ucli% ucli% ucli% ucli% ucli%

start ../simv config endofsim noexit run start simv run

Related Commands restart restore

restart
This command is used to restart the existing tool (e.g. simv) from simulation time '0'. This command doesn't take any arguments. Always this command restarts the tool with the same set of command line arguments it was originally invoked. This command can be executed at any time during simulation. When executed, this command Retains all the previous UCLI configuration values. Retains all previously set Break Points.

Note: The default end-of-simulation behavior is to exit UCLI shell i.e. UCLI process will exit when the tool (e.g. simv) reaches end-ofsimulation or $finish (in Verilog) or tool dies (crashes or segmentation fault). To prevent this, you need to set endofsim configuration parameter to noexit. Syntax
restart

Commands 3-4

Examples
ucli% restart

Starts tool simv from simulation time '0'. This command displays no output. //Flow Example //To restart simulation multiple times
ucli% config endofsim noexit

Sets end of simulation criterion to noexit i.e. UCLI TCL shell is not exited after reaching end of simulation. The output of this command is the value of configuration variable endofsim which in this case is noexit.
Noexit ucli% run

May display simulation output. Once the simulation is stopped, UCLI TCL shell is not exited and you may give additional debugging commands and restart the simulation.
ucli% restart Starts tool simv from simulation time '0'. ucli% config endofsim noexit ucli% run ucli% restart

Commands 3-5

Related Commands

start cbug
This command is used to enable debugging C, C++, or SystemC modules included in the VCS and VCSMX designs. Alternately, the C debugger starts automatically when a break point is set in a C/ C++/SystemC source code file. For more information, see the chapter "Using the C, C++, and SystemC Debugger ". Note: The tool (e.g. simv) should be started before starting C debugger. This feature is a Limited Customer Availability (LCA) feature. Syntax
cbug [-detach]

-detach This option detaches (disables) the UCLI C debugger. Examples


ucli% cbug The above command attaches (enables) C Debugger. This command displays the following output. Information: CBug is an LCA feature CBug - Copyright Synopsys Inc 2003-2007 Please wait while CBug is loading symbolic information ... ... done. Thanks for being patient!

Commands 3-6

ucli% cbug -detach

This command detaches (Disables) C Debugger. This command displays the following output.
CBug detaches Stopped

Session Management Commands


save
This command is used to store the current simulation snapshot in a specified file. This command saves the entire simulation state including break points set at the time of saving the simulation. Relative or absolute path can be given where you want the specified file to be kept (see example that follows). This command also creates (along with specified file) a file called <filename>.ucli in the directory where specified file is saved. This file has the record of all the commands that have been executed (including this command). Multiple simulation snapshots can be created by using this command repeatedly. Before executing this command, you need to do the following: Detach the UCLI C Debugger (if attached). Close any open files in PLI or VPI.

When saving and restoring, two different interface technologies should not be mixed i.e. Save using UCLI and restore using UCLI. Do not use DVE, SCL, or CLI to restore.

Commands 3-7

Save using DVE and restore using DVE. Do not use UCLI, SCL, or CLI to restore. Save using SCL and restore using SCL. Do not use DVE, UCLI, or CLI to restore. Save using CLI and restore using CLI. Do not use DVE, SCL, or UCLI to restore.

Syntax
save <filename>

filename The name of the file to which simulation snapshot will be written. Example
ucli% save sim_st

Saves current state of simulation in file sim_st. This command displays the following output.
$save: Creating sim_st from current state of./simv... ucli% save /tmp/scratch1/sim_st

Saves current state of simulation in the file called /tmp/scratch1/ sim_st. This command displays the following output.
$save: Creating /tmp/scratch/sim_st from current state of./simv...

Related Commands restore

Commands 3-8

restore
This command is used to restore the saved simulation state from a specified file. This command restores the entire simulation state including break points set at the time of saving the simulation. Relative or absolute path can be given from where you want the specified file to be read. Multiple times a simulation can be restored by using different (or same) simulation snapshots (of same tool). Before executing this command, you need to do the following tasks: Detach the UCLI C Debugger (if attached). Close any open files in PLI or VPI.

When saving and restoring, two different interface technologies should not be mixed that is Save using UCLI and restore using UCLI. Do not use DVE, SCL, or CLI to restore. Save using DVE and restore using DVE. Do not use UCLI, SCL, or CLI to restore. Save using SCL and restore using SCL. Do not use DVE, UCLI, or CLI to restore. Save using CLI and restore using CLI. Do not use DVE, SCL, or UCLI to restore.

Syntax
restore <filename>

filename The name of the file from which to restore simulation state.

Commands 3-9

Example
ucli% restore sim_st

Restores state of simulation from the snap shot stored in the file sim_st. This command displays the following output.
Restart of a saved simulation ucli% restore /tmp/scratch1/sim_st

Restores state of simulation from the snap shot stored in the file /tmp/scratch1/sim_st. This command displays the following output.
Restart of a saved simulation

Related Commands save

Tool Advancing Commands


step
This command is used to move the simulation forward by one executable line of code irrespective of the language of the code. The step command steps into tasks functions and VHDL Procedures when called, that is, steps through the executable lines of code in the task/function/VHDL Procedure. This command when executed:
Commands 3-10

Displays source file name. Line number.

Source code at that line.

Note: If the source code is encrypted, then only source file name is displayed. Syntax
step step [-thread [thread_id]] step [-tb [instanceFullName]] step [-prog [instanceFullName]]

-thread [thread_id] This option is for NTB-OV and SystemVerilog test benches only. When this option is specified, step stops at the next executable statement in the thread specified by thread_id. If thread_id is not specified, then simulator stops at the next executable statement in the current thread. If the thread_id doesn't exist when step is executed, simulator reports an error. -tb [instanceFullName] This option is for NTB-OV and SystemVerilog test benches only. When this option is specified, tool skips the test bench portion of the code (that is, skips any program instances and any module instances that contain test bench constructs). The instanceFullName should be a program instance or any module instance that contains test bench constructs. If instanceFullName is not specified, then step skips all program instances and module instances that contain test bench constructs. -prog [instanceFullName]

Commands 3-11

This option is for NTB-OV and SystemVerilog test benches only. The functionality of this option is same -tb. This option is for backward compatibility. Example
ucli% step

Stops at the next executable line in the source code. This command displays source file name, line number and source code at that line number as output.
t1.v, 12 : $display("66666666");

ucli% step -thread 1

Stops at the next executable line of thread 1 in the testbench source code. This command displays source file name, line number and source code at that line number as output.
step2.vr, 14 : delay(10);

Related Commands run next

next
This command is used to move the simulation forward by one executable line of code irrespective of the language of the code. For VHDL, NTB-OV, SVTB, and MX designs, next step over tasks and functions i.e. doesn't go into task/function when called. For pure Verilog and System Verilog designs, this command is same as step command.

Commands 3-12

This command when executed, Displays source file name. Line number. Source code at that line.

If the simulator is already executing a statement inside task or function, then next command does not step over, that is, it behaves same as step. If the code source code is encrypted, only source file name is displayed. Syntax
next next [-end] next [-language <tool_lang>]

-end This option is for NTB-OV and SystemVerilog testbenches only. When this option is specified, the next command finishes the execution of task/function and returns to caller. -language <tool_lang> When this option is specified, the tool stops at next executable line in the language specified by the tool_lang option. You can use this option to change the control of execution from one language to another. Currently only Verilog is supported. Example
ucli% next

Commands 3-13

Stops at the next executable line in the source code. This command displays source file name, line number and source code at that line number as output.
asb_core.v, 7 : if(cmd == 4'ha)

Related Commands stop step run

run
This command advances the tool until a breakpoint, $stop, or $finish is encountered or the specified simulation time is reached. Syntax
run run run run run run run run run run run run run [time] [time [unit]] [-absolute|relative time [unit]] [-line <lineno>] [-line <lineno> [-file <file>]] [-line <lineno> [-instance <i_nid>]] [-line <lineno>][-thread <tid>] [-posedge | rising <nid>] [-negedge | falling <nid>] [-change | event <nid>] [-delta] [-0]

Note: Options -posedge, -negedge, and -change will be deprecated.

Commands 3-14

<nid> Nested identifier (Hierarchical path) of a single signal, port, or variable. Multiple objects cannot be specified. <lineno> Line number in the file mentioned by -file or line number in the module instance mentioned by -instance. This line should be a breakable line. <i-nid> Nested identifier (Hierarchical path) of an instance. Multiple objects cannot be specified. <unit> This is the time unit. This could be [s | ms | us | ns | ps | fs]. By default this unit is time unit of simulation. <tid> Thread id. If not specified current thread is assumed. The run -delta command advances delta cycle time. The run -delta command is useful for delta cycle level debugging especially when it comes to viewing values instantaneously due to forces and values propagation or debugging races. This feature is currently supported only in VCSMX (Mixed-HDL (MX), pure VHDL) flows. <-delta>

Commands 3-15

Advances one delta time. For MX/VHDL, the simulation advances to the next delta and return to UCLI soon after the signal update phase (before process execution). You can inspect values of newly deposited signals/variables at that time. If there are no more events, the simulation advances to the next time step and stops at the end of the first delta of the new time step. <0> Advances to the end of current time before advancing time. For MX/VHDL, the simulation stops after signal update phase, before process execution for the last delta. If UCLI generates more events by forces or release etc., all such events are processed until things stabilizes at the end of current time. Example
ucli% run

Runs until a break point is reached or end of simulation is reached. This command's output varies depending on the simulation.
ucli% run 10ps

Runs the simulation 10ps relative to the current simulation time. If the current simulation stops at 1390ps, this command runs the simulation 10ps more and stops at 1400ps. This command is same as run -relative 10ps.The output of this command indicates the time at which simulation is stopped. 1400 PS ucli% run -relative 10ps

Commands 3-16

Runs the simulation 10ps relative to the current simulation time. If the current simulation stops at 1400ps, this command runs the simulation 10ps more and stops at 1410ps. This command is same as run 10ps. The output of this command indicates the time at which simulation is stopped. 1410 PS ucli% run -absolute 10ps Runs the simulation 10ps relative to the simulation time '0'. The time specified should be greater than the current simulation time. In this example the time specified is greater than the current simulation time. The output of this command indicates the time at which simulation is stopped. 10 PS ucli% run -absolute 10ps Runs the simulation 10ps relative to the simulation time '0'. The time specified should be greater than the current simulation time. In this example the time specified is less than the current simulation time. The output of this command indicates saying time specified is less than the current simulation time.
the absolute time specified '1' is less than or equal to the current simulation time '210 ps'

ucli% run -line 15 Runs the simulation until line number 15 in the current opened file is reached. The output of this command indicates the time at which simulation is stopped. 1576925000 PS

Commands 3-17

ucli% run -line 15 -instance IST1 (NOT WORKING) Runs the simulation until line number 15 in the module instance is reached. The output of this command indicates the time at which simulation is stopped. 1576925000 PS ucli% run -line 15 -file level9.v Runs the simulation until line number 15 in file level9.v is reached. The output of this command indicates the time at which simulation is stopped. 1476925000 PS ucli% run -posedge clk Runs the simulation until posedge of signal clk event occurs. The output of this command indicates the time at which simulation is stopped. 100000 ps ucli% run -change clk Runs the simulation until posedge or negedge of signal clk event occurs. The output of this command indicates the time at which simulation is stopped. 500000 ps ucli% run -event clk

Commands 3-18

Runs the simulation until posedge or negedge of signal clk event occurs. The output of this command indicates the time at which simulation is stopped. 600000 ps Related Commands stop

finish
This command is used to end processing in the tool. Syntax
finish

Note: The default end-of-simulation behavior is to exit UCLI shell, that is, UCLI process will exit when the tool (e.g. simv) reaches end of simulation, or $finish (in Verilog), or dies (crashes or segmentation fault). To prevent this, you need to set endofsim configuration parameter to noexit. Example
ucli% finish

Finishes the simulation. The VCS banner is displayed as output of this command.
V C S S i m u l a t i o n Time: 00 ps CPU Time: 0.040 seconds; 2.4Mb Mon Mar 17 16:10:45 2008 R e p o r t Data structure size:

Commands 3-19

Related Commands start

Navigation Commands
scope
This command is used to display the current scope or set the current scope to a specified instance. Syntax
scope scope [nid] scope [-up [number_of_levels] scope [-active]

nid Nested identifier of the instance. scope Displays the current scope when executed without any options. scope [nid] Sets the current scope to the hierarchical instance specified by nid. scope [-up [number_of_levels] Moves the current scope up by number_of_levels. If number_of_levels is not specified, current scope is moved up '1' level. number_of_levels must be an integer and greater than 0.

Commands 3-20

scope [-active] Sets the current scope to active scope. The active scope is the scope in which simulator is currently stopped. For more information, see the topic Current versus Active Point in the UCLI User Guide. Example
ucli% scope

Returns the current scope. This command displays current scope in the design.
T.t ucli% scope T.t1.t2.t3.dig

Sets the current scope to T.t1.t2.t3.dig. This command displays scope to which tool is set to. In this case the output will be:
T.t1.t2.t3.dig ucli% scope -up 2

Moves the current scope up by 2 levels. This command displays the new scope.
T.t1 ucli% scope -active

Sets the current scope to active scope. This command displays the new scope.
T.t1

thread
This command is used to do the following tasks:

Commands 3-21

Display current thread information Move thread in current scope to active scope Attach a new thread to current thread.

The thread information displayed contains Thread id State of the thread Scope of the thread and File name and line number in which this particular thread is present.

Note: This command is for NTB-OV or System Verilog test benches only. Syntax
thread thread [-attach [tid]] thread [-active] thread [<tid>] [-all] [-blocked | -running | -current | -waiting]

thread Displays detailed information of the threads and their state. thread [tid] Displays all the details of a particular thread specified by tid. This command is same as thread <tid> -all. thread [-attach [tid]] Changes current scope of the thread (with thread id tid) to active scope.
Commands 3-22

thread [-active] Resets tool's current thread to active point. thread -all Displays all threads with detailed information. thread [-current | -blocked | -running | -waiting] Displays thread by their state. Examples
ucli% thread

Displays information about all the threads. The output of this command contains thread id, state of the thread, scope of the thread and file name and line number in the file in which this particular thread is present.
thread #1 : (parent: #<root>) RUNNING 1 : -line 6 -file t2.vr -scope {test_2.test_2.unnamed$$_1} thread #2 : (parent: #1) CURRENT 0 : -line 7 -file t2.vr -scope {test_2.test_2.unnamed$$_1.unnamed$$_2} ucli% thread 1

Displays information about thread 1. This command displays the following output.
thread #1 : (parent: #<root>) CURRENT 0 : -line 6 -file t2.vr -scope test_2.test_2 ucli% thread -attach 2

Changed current scope of thread 2 to active scope. This command displays a positive integer for successful execution.
2

Commands 3-23

ucli% thread -all

Displays all threads with full thread information. This command displays the following output.
thread #1 : (parent: #<root>) RUNNING 0 : -line 6 -file t2.vr -scope test_2.test_2 1 : -line 6 -file t2.vr -scope {test_2.test_2.unnamed$$_1} thread #2 : (parent: #1) CURRENT 0 : -line 7 -file t2.vr -scope {test_2.test_2.unnamed$$_1.unnamed$$_2} ucli% thread -current

Displays all threads that are currently being executed. This command displays the following output.
thread #2 : (parent: #1) CURRENT 0 : -line 7 -file t2.vr -scope {test_2.test_2.unnamed$$_1.unnamed$$_2}

Related Commands stack

stack
This command is used to display current call stack information; it lists the threads that are in CURRENT state. The stack information displayed is scope of the thread, file name, and line number in the file in which this particular thread is present. Note: This command is for NTB-OV or System Verilog test benches only.

Commands 3-24

Syntax
stack stack [-up | -down [number]] stack [-active]

stack Displays all NTB-OV or System Verilog threads that are in CURRENT state. stack [-active] Moves current point to active point within the tool. stack [-up | -down [intnbr]] This command is useful only if stack contains more than one thread. This command moves the stack pointer up or down by intnbr of locations. If number is not specified, then stack pointer is moved up or down by '1'. The number has to be a positive integer. Examples
ucli% stack

Lists all threads that are in CURRENT state. The output of this command contains thread id, scope of the thread and file name and line number in the file in which this particular thread is present.
0 : -line 13 -file t2.vr -scope {test_2.test_2.unnamed$$_1.unnamed$$_4} 1 : -line 6 -file t2.vr -scope {test_2.test_2.unnamed$$_1} ucli% stack -active

This command sets the stack pointer to active thread in the stack. The output of this command is id of thread present at the location pointed by stack pointer.

Commands 3-25

0 ucli% stack -up 1

This command moves the stack pointer up by 1. The output of this command is ID of the thread present at the location pointed by stack pointer.
1

Related Commands thread

Signal/Variable/Expression Commands
get
This command is used to return the current value of a signal, variable, net or reg. The default radix used to display the value is decimal. Use the config command to change the default radix. Syntax
get <nid> get <nid> [-radix string]

<nid> Nested hierarchical identifier of the signal, variable, net or reg. get <nid> Displays current value of nid. get <nid> [-radix string]

Commands 3-26

Displays current value of nid in the radix specified by -radix. The supported radices are binary, decimal, octal and hexadecimal. Examples
ucli% get T.t.tsdat

Displays current value of T.t.tsdat in decimal radix. This command displays the following output.
16 ucli% get tsdat -radix hex

Displays current value of tsdat in hexadecimal radix. This command displays the following output.
'h10

Related Commands config show

force
This command is used to force a value onto an HDL object (signal or variable). This command takes precedence over all other drivers of the HDL object being forced. You can control the force on an HDL object by applying at a particular time, multiple times or repeat a sequence as desired by you. By default, no other activity in the tool (some other driver applying a new value to the forced HDL object) can override this value. The effect of this command on an HDL object can be canceled by the following commands:

Commands 3-27

a release command another force command or specifying -cancel option with the force command.

Note: This command is not supported for NTB-OV and System Verilog testbench objects. Syntax
force <nid> <value> [<time> {, <value> <time>}* [-repeat <time>]] [-cancel <time>] [-freeze|-deposit] [-drive]

Note: The order in which value-time pairs and options are specified is arbitrary; there is no strict ordering rule to be followed. nid Nested identifier (Hierarchical path name) of HDL objects that must be forced. value Specifies the value to be forced on the HDL object. The value could be of any radix, such as binary, decimal, hexadecimal, or octal decimal. The default radix is decimal. Only literal values of appropriate type can be specified for a given HDL object. The supported data types are as follows: - integer - real number

Commands 3-28

- enumeration - character - character string - bit - bit vector - 4-value logic - 9-value logic - 9-value and 4-value logic vector - array - VHDL and Verilog syntax for literals is accepted. VHDL 9-value logic is converted into Verilog 4-value logic when it is forced on a Verilog object. The conversion is as follows.
U W L H -> -> -> -> -> X X 0 1 X

Similarly 9-value or 4-value logic is converted to 2-value logic when it is forced on a VHDL object of the predefined type BIT. The table below together with the table above defines the conversion.
X Z -> -> 1 0

Character string literals must be specified within double quotes (" ") and enclosed in curly braces. Example: {"Hello"}. time Expressed as
Commands 3-29

- [@]number - number - number[unit] or - [@]number[unit] - '@' is optional and implies absolute time. unit is one of [s | ms | us | ns | ps | fs]. number is any integer number. If no unit is specified, then time precision of the tool (config timebase command gives time precision of the tool) is used. -freeze If this option is specified, no other activity in the tool (some other driver applying value to a forced signal or variable) can override applied value. This is the default option. This option is useful after -deposit option is used. -deposit If this option is specified, some other activity in the tool (some other driver applying a new value to the forced HDL object) can override previously forced value. -drive This option is for VHDL only. This option attaches a new driver with specified value to the signal. Limitation:

Commands 3-30

Works only with VHDL_STD_LOGIC and STD_LOGIC_VECTOR signals. Forcing part of a vector is not supported. -cancel <time> This option is used to cancel the effect of force command after specified time. -repeat (-r) <time> This option is used to repeat a sequence after specified interval. Example
ucli% force probe 4'h8

This command forces the value of HDL object probe to hold value 4'h8. The above command is same as force -freeze probe 4'h8. This command displays no output.
ucli% force probe 4'h9 @10ns

This command forces the value of HDL object probe to hold value 4'h9 at 10ns absolute simulation time. This command displays no output.
ucli% force probe 4'h9 10ns

This command forces the value of HDL object probe to hold value 4'h9 at 10ns relative to the current simulation time. This command displays no output.
ucli% force probe 4'h9 10

This command forces the value of HDL object probe to hold value 4'h9 at 10 time units relative to the current simulation time. This command displays no output.

Commands 3-31

ucli% force probe 4'h9 -deposit

This command forces the value of HDL object probe to 4'h9. This command displays no output.
ucli% force top.clk 1 10, 0, 20

Assuming that current simulation time is at '0', this command forces the HDL object top.clk to '1' at 10ps and '0' at 20ps. This command displays no output.
ucli% force top.clk 1 10, 0, 20 -repeat 30

This command generates 20ps period clock, that is, top.clk will be clock with 20ps period and 50% duty cycle. After 30ps, the sequence (of applying 1 and holding it for 10ps more and applying 0 and holding it for 10ps more) repeats and this will continue forever. This command displays no output.
ucli% force top.clk 1 10, 0, 20 -repeat 30 -cancel 1sec

See the explanation of above command. This command cancels effect of force after 1 sec of simulation time. This command displays no output. Different ways in which force can be used
ucli% ucli% ucli% ucli% ucli% ucli% ucli% ucli% ucli% ucli% ucli% ucli% ucli% ucli% force force force force force force force force force force force force force force var var var var var var var var var var var var var str 10 'h 20 10 ns, 'o7460 20ns 4'b1001 10ns, 5 'D 3 7ns, 3'b01x 10 12'hx 100, 16'hz 200 27_195_000 '16'b00_111_0011_1_11111_0 32'h 1_23_456_7_8 1.23 1.2E12 236.123_763_e-12 2#1101_1001 10, 16#FA 20, 16#E#E1 30 B"1110_1100_1000" 1, X"F77" 3 '0' 50ps, 1 60ps, 1'b1 70 ps, 1'b0 1ns {"Hello"} @ 1us, ('H', L, L) @ {2us}

Commands 3-32

Related Commands release get

release
This command is used to release the value forced to a signal, variable, net or reg previously by force command. After this command is executed, the drivers of signal, variable, net or reg will be original drivers. Note: If the net type is reg or wire, then it retains the value until the original driver forces a new value. This command is not supported in NTB-OV and System Verilog testbench variables. Syntax
release <nid>

<nid> Nested hierarchical identifier of the signal, variable, net or reg. Examples
ucli% release T.t.tsdat

Displays current value of T.t.tsdat in decimal radix. This command displays the following output. Related Commands

Commands 3-33

force get

sexpr
This command is used to display the result of an expression. The expression must adhere to VHDL syntax expression. If there is only one operand and no operation to be performed on the operand, then this command returns the current value of operand. Note: This command is not supported in NTB-OV and System Verilog Test benches. The supported data types are bit and boolean. VHDL data types std_logic, std_logic_vector, std_ulogic and std_ulogic_vector. Verilog data types wire, wire vectors, reg, reg vectors, integer, real and time.

The following operators are supported by this command. Unary operator + and -. Binary operators +, -, * and // (Note: Division requires two forward slashes, //) Concatenation operator & Logical operators and, or, nand, xor, nor and or.

Commands 3-34

Relation operators =, <, <=, > and >=.

Limitations Unsupported data types will cause an error message. Only VHDL array syntax '(' and ')' is supported, Verilog array syntax '[' and ']' is not supported for array variables. Function calls within expression are not supported. Unsupported operators are - Unary Negation (for example, -3) - Remainder (REM) and Modulo (MOD) operator. - "** (Exponentiation) Expression operands should be type consistent; no type casting is done by this command. For example, an integer type can't be added to a non-integer type. Hierarchical path delimiters are respective to HDL language. For Verilog path delimiters, use '.' (dot) and for VHDL path delimiter, use '/' (forward slash). Example Consider vhdl_top is VHDL, vlog_inst is Verilog module instance inside vhdl_top and vlog_var is a Verilog variable inside vlog_inst. The way to reference vlog_var is
/vhdl_top/vlog_inst.vlog_var

Instead of '.', you can always use '/' i.e. in the previous example, vlog_var can also be referenced like /vhdl_top/vlog_inst/vlog_var.

Commands 3-35

Absolute and relative paths are supported.

Syntax
sexpr [-radix] expression

-radix The default radix is decimal. The supported radix are [binary | decimal | octal | hexadecimal]. Examples
ucli% sexpr T.t.tsdat

Displays current value of T.t.tsdat in decimal radix. For example,


6 ucli% sexpr {period1 = 10 and period2 =10}

This command checks if both variables period1 and period2 have values 10. If yes returns 1 (Boolean TRUE) and 0 (Boolean FALSE). In this case returns 1, that is, both have values 10. For example, 1.
ucli% sexpr {period1 + period2}

This command adds variables period1, period2 and returns result. In this case the result is 20 so 20 is displayed as output. For example,
20

call
This command is used to call Verilog and VHDL tasks, functions and procedures from UCLI. This command automatically executes the called task, function or procedure. Hierarchical referencing is not allowed for task, function or procedure.

Commands 3-36

Note: This command does not advance simulation time. Executable statements after delay elements in the routine will not be executed and call returns to UCLI. Since UCLI is Tcl based, curly braces '{' and '}' are needed as special characters like '$' are interpreted as variables in Tcl. Instead of curly braces, '\' (back slash) can also be used. Curly braces are not needed if there are no special characters. Syntax
call {cmd()}

cmd cmd is a Verilog task or function, a user PLI task, a system task (example $display) or a VHDL procedure or function. A foreign procedure implemented in C language can also be called. Examples
ucli% call {$display("Hello World")}

Executes Verilog predefined function $display(). This command displays the following output.
Hello World ucli% call verilog_task(a, b)

Executes the verilog_task defined in the current scope. This output of this command depends on task verilog_task.
ucli% call verilog_function(a, b) ucli% call vhdl_proc(a, b)

Commands 3-37

virtual bus (vbus)


This command is used to create, delete or query a virtual bus. You can do the following tasks: Create a new bus that is a concatenation of buses and sub elements. Delete the created virtual bus. Query the expression of the created virtual bus.

The elements used to create virtual buses could be different data types, elements of different scope or different language. Virtual buses can also be used as elements to create new virtual buses. Hierarchical referencing is allowed. Note: The actual command is 'virtual bus'. This has been aliased to 'vbus'. Both 'virtual bus' and 'vbus' can be used. Alternately 'virtual' can also be used. Forward slash '/' is used as path delimiter. The Verilog path delimiter '.' (dot) is not supported. Syntax
vbus vbus[-install <scope>] [-env <scope>] <expression> <vb_name> vbus[-delete] <vb_name> vbus[-expand] <vb_name>

vbus Lists all the created virtual buses in all scopes. This command can be executed from any scope.

Commands 3-38

-env <scope> Defines the scope from which vbus elements will be used to create virtual bus. This is useful if you want virtual bus to be created in the current scope by using elements from a different scope. -install <scope> Specifies the scope in which the vbus must be created. vbus -delete <vb_name> Deletes virtual bus vb_name. This command must be executed only from the same scope where vb_name was created. vbus -expand <vb_name> Expands virtual bus vb_name. This command can be executed only from the same scope where vb_name was created. This command recursively expands the elements i.e. if there are virtual buses in vb_name, and then they will also be expanded. Limitations The following commands/operations are not supported on vbus. change. Instead of change, you can use force -deposit. loads drivers dump

Examples
ucli% vbus

Commands 3-39

Lists all virtual buses from all scopes. This command displays the following output.
tbTop.vb_1 tbTop.IST1.vb_2 tbTop.IST1.vb_3 ucli% vbus {/tbTop/clk & /tbTop/IST1/rst} vb_1

Creates virtual bus vb_1 in current scope. This command displays no output.
ucli% vbus -env /tbTop/IST1/IST2 {a & b & c} vb_2

Creates virtual bus vb_2 in current scope. Elements a, b and c are defined in scope tbTop.IST1.IST2. This command displays no output.
ucli% vbus -install /tbTop {/tbTop/vb_1 & /tbTop/IST1/vb_2} vb_3

Creates virtual bus vb_3 in scope /tbTop. Element vb_1 is in scope tbTop and element vb_2 is in scope tbTop.IST1. This command displays no output.
ucli% vbus -install /tbTop -env /tbTop/IST1/IST2 {/tbTop/ vb_1 & /tbTop/IST1/vb_2 & vb_3} vb_4

Creates virtual bus vb_4 in scope tbTop. Element vb_1 is defined in tbTop, element vb_2 is defined in tbTop.IST1 and element vb_3 is defined in tbTop.IST1.IST2. This command displays no output.
ucli% vbus -expand vb_4

Expands virtual bus vb_4. This command displays following output.


tbTop.clk tbTop.reset tbTop.IST1.TMP tbTop.IST1.TMP1

Commands 3-40

ucli% vbus -delete vb_4

Deletes virtual bus vb_4. This command displays no output.

Tool Environment Array Commands


senv
This command is used to display the simulator environment array. You can also query individual element of the simulator environment array. Simulation environment array contains following elements. activeDomain: Language Domain. Example: Verilog. activeFile: Source file tool is executing. activeFrame: activeLine: Line number in the activeFile being executed. activescope: The scope in which tool has stopped. activeThread: The thread id whose state is CURRENT. file: File name you are currently navigating. frame: fsdbFilename: Debussy fsdb file name. hasTB: If design loaded has test bench constructs this value will be '1' else '0'. inputFilename: UCLI input commands file name.

Commands 3-41

keyFilename: UCLI commands entered are stored in this file. Default is ucli.key. line: Line number in the file you are currently navigating. logFilename: Simulation log file name. (Specified with -l option) scope: Current Scope. state: State of the tool. thread: The current thread id. time: Absolute simulation time. timePrecision: Time precision of the tool. vcdFilename: VCD file name. vpdFilename: VPD file name.

Note: This is a read-only array i.e. no element in the environment array is writable by user. Syntax
senv [element]

senv Lists all elements in the environment array. senv [element] Displays current value of element in the environment array. The argument element is case sensitive.

Commands 3-42

Examples
ucli% senv

Displays all elements and their values in environment array currently. This command displays the following output.
activeDomain: Verilog activeFile: tbTop.v activeFrame: activeLine: 1 activeScope: tbTop activeThread: file: tbTop.v frame: fsdbFilename: hasTB: 0 inputFilename: keyFilename: ucli.key line: 19 logFilename: scope: tbTop.IST1 state: stopped thread: time: 0 timePrecision: 1 PS vcdFilename: vpdFilename: ucli% senv activeDomain

Displays current value of activeDomain in environment array. This command displays the following output.
activeDomain: Verilog

Related Commands show config

Commands 3-43

Breakpoint Commands
stop
This command is used to set break points in the tool (Example: simv) i.e. tool can be stopped based on certain condition(s) or certain event(s) and display previously set break points in the tool. This command can be used to specify an action to be taken after the tool has stopped. UCLI provides many ways to stop the tool, such as On an event i.e. change in value of a signal. At a particular time during simulation. At a particular executable line in the source code. In task or function. On assertion trigger by using assertion command. For more information, see the assertion command.

There are many actions you can perform after the tool has stopped, such as: Deleting a break point. Setting another break point. Execute a Tcl script. Executing any UCLI command.

Note: Break points can be set only at executable lines.


Commands 3-44

If the source code is encrypted, then only source file name is displayed. Syntax
stop [arguments]

Different ways in which tool can be stopped are as follows:


stop -line <linenum> [-file <filename>]

Sets a break point at the line number specified by linenum in the file specified by filename. If no filename is specified, then break point is set at lineno in the current file. However it is strongly recommended that you use -file option.
stop -line <linenum> -file <filename> -instance <nid>

Sets a break point at the line number specified by linenum in the file specified by filename. The source code at this lineno is an instantiation of another module. The nid is one level above nested identifier of actual instance on which break point is being set i.e. if break point is being set on Top.I1.I2.I3 then nid should be Top.I1.I2.
stop -absolute | -relative <time>

Sets a break point at absolute time (from simulation time '0') or relative time (from the current simulation time). Absolute time should be more than the current simulation time.
stop [-thread <tid> | -allthreads]

This is for NTB-OV and System Verilog Test benches only. Sets break point at the thread specified by tid or, if -allthreads is specified, sets break points at all threads. The tid must exist at current simulation time to set break point.
stop -in <task/function> [thread <tid>]

Commands 3-45

This is for NTB-OV and System Verilog Test benches only. Sets break point at the thread specified by tid of the task or function. If no tid is specified, then sets break points in all threads of task or function.
stop -posedge | -rising <nid> [-condition expression]

This is not supported in NTB-OV and System Verilog Test benches. Sets a break point on posedge or rising (low -> high transition) of signal specified by nid.
-condition expression

Optionally in VHDL only, an expression can be specified. If this expression is evaluated as TRUE (Boolean TRUE), the simulator stops when a posedge or rising transition occurs on signal nid.
stop -negedge | -falling <nid> [-condition expression]

This is not supported in NTB-OV and System Verilog Test benches. Sets a break point on negedge or falling (high->low transition) of signal specified by nid.
stop -change | -event <nid> [-condition expression]

This is not supported in NTB-OV and System Verilog Test benches. Sets a break point on change in state or an event happened in the signal specified by nid.
stop -mailbox <mid> [-thread <tid> | -allthreads]

This is for NTB-OV and System Verilog Test benches only.


stop -semaphore <sid> [-thread <tid> | -allthreads]

This is for NTB-OV and System Verilog Test benches only. Actions that can be performed when tool stops are as follows:
stop -show <stop-id>

This command can be used to display stop point with id stop-id.

Commands 3-46

stop -delete <stop-id>

This command can be used to delete stop point with id stop-id.


stop -enable | -disable <stop-id>

This command can be used to Enable or Disable stop points. By default all the stop points are enabled.
stop -once | -repeat <stop-id>|<stop-specification>

This command can be used to control how often stop points are triggered. By default all the stop points are triggered repeatedly. If -once option is specified, then tool stops only once for the break point with stop id stop-id.
stop -halt | -continue <stop-id>|<stop-specification>

This option can be used to continue simulation even after a stop point is triggered. By default, all the stop points are in halt state i.e. simulation stops after break point is triggered.
stop -quiet | -verbose <stop-id>|<stop-specification>

This option can be used to turn on or off the verbose information associated with stop point (specified by stop-id). By default, the verbose information is ON.
stop -command {tcl_script} <stop-id>|<stop-specification>

This option can be used to execute a Tcl script (which has UCLI commands) when stop point with id stop-id is triggered.
stop -condition { tool_condition } <stop-specification>

This option can be used to add additional condition to an existing stop point. If this stop point already has a condition attached to it, then another condition cannot be attached.
stop -name <string> <stop-id>|<stop-specification>

This option can be used to give a name to stop point.

Commands 3-47

stop -skip <num> <stop-id>|<stop-specification>

This option can be used to skip num times the stop point with stop id specified by stop-id i.e. tool ignores this stop point num times before actually stopping because stop point with stop-id got triggered. Examples
ucli% stop

This command displays active break points. This command displays the following output.
1: -change tbTop.IST1.CLK -condition {TMP1 = 0 } 2: -change tbTop.IST1.CLK -once -condition {TMP = 0 } ucli% stop -line 10 -file tbTop.v

This command sets break points at line number 10 in the file tbTop.v. The output of this command is stop-id of this particular break point.
4 ucli% stop -line 11 -file level9.v -instance tbTop.INST1.INST2

This command sets break points at line number 11 in the file level9.v. The source code at line 11 in file level9.v is an instance of some other module. If the instance name if this module is INST3, then hierarchical reference of this instance from top is tbTop.INST1.INST2.INST3. So after -instance option, you should use tbTop.INST1.INST2. The output of this command is stop-id of this particular break point.
5 ucli% stop -absolute 1000ns

This command sets break points absolute time 1000ns. The output of this command is stop-id of this particular break point.

Commands 3-48

6 ucli% stop -thread 1

This command sets break points on thread 1. The output of this command is stop-id of this particular break point.
7 ucli% stop -in hw_task -thread 1

This command sets break points on thread 1 of task hw_task. The output of this command is stop-id of this particular break point.
2 ucli% stop -change CLK -condition {TMP = 0}

This command sets break points on change in value of CLK and value of TMP equals to '0'. The output of this command is stop-id of this particular break point.
1

Related Commands run

Timing Check Control Command


tcheck
This command is used to disable or enable timing checks on a specified instance or port. By default all timing checks are enabled. The command can also be used to query the timing check control status.

Commands 3-49

Note: This command is used only for Verilog designs. The source code should contain timing related checks inside specify block for this command to work. If timing related checks are not found on a specified instance or port, then a warning is displayed. Syntax
tcheck <instance|port> <tcheck_type> <-msg|-xgen> [-disable|-enable] [-r] tcheck <instance|port> -query

instance|port This is hierarchical full name of an instance or port. tcheck_type This is type of timing check to be enabled or disabled. The valid timing check types are as follows:
[all|HOLD|SETUP|SETUPHOLD|WIDTH|RECOVERY|REMOVAL|RECREM |PERIOD|SKEW]

HOLD Enables or Disables HOLD timing check. SETUP Enables or Disables SETUP timing check. SETUPHOLD Enables or Disables SETUPHOLD timing check. WIDTH
Commands 3-50

Enables or Disables WIDTH time timing check. RECOVERY Enables or Disables RECOVERY timing check. REMOVAL Enables or Disables REMOVAL timing check. RECREM Enables or Disables RECREM timing check. PERIOD Enables or disables PERIOD timing check. SKEW Enables or Disables SKEW timing check. -disable|-enable Enables or Disables particular timing check specified by tcheck_type. -msg|-xgen Controls simulation behavior when a particular timing related violation is detected, such as. - disable/enable timing violation warning on the specified instance or port. - disable/enable notifier toggling on the specified instance or port. -r

Commands 3-51

Enables or Disables timing checks for specified instance and all sub-instances below it recursively. Examples
ucli% tcheck {TEST_top.C$0010001} WIDTH -msg -disable

This command disables pulse width timing check on instance TEST_top.C$0010001. This command displays no output.
ucli% tcheck {TEST_top.C$0010001} -query

This command displays status timing checks on instance TEST_top.C$0010001. This output of this command contains file name and line number along with status of timing check(s).
Timing Check for : TEST_top.TEST_shell.TEST.C$0010001 File : noTcTest5.v Line | Timing Check | msg | xgen L223 : SETUP ON ON L226 : HOLD ON ON L233 : WIDTH ON OFF L235 : PERIOD ON ON

report_timing
The report_timing command is added in this release of UCLI. Report Timing feature allows you to get the information of the SDF (Standard Delay Format) values annotated for a specific Instance. The feature is useful when debugging timing based simulations. Typically, SDF files are very big and when there is a violation, it is hard to get the delay values for the specific instance as you need to browse through the huge SDF files. With the report_timing command, you can specify the instance path, which is showing the violation and the tool prints out all the IOPATH and Timing Check delay values for that instance.

Commands 3-52

The feature is also helpful for debugging NTC issues (Negative Timing Check Convergence). When negative timing-checks do not converge, VCS rounds the negative delay values to 0. The report_timing command always show you the delay values applied by the tool after SDF annotation instead of original values that makes it easier to debug timing failures. The syntax of the report_timing command is as follows:
report_timing [-recursive] [-file <filename>] [<instance_name1><instance_name2>...<instance_nameN>]

-recursive (Optional). Generates timing information for the specified instance and all instances underneath it in the design hierarchy.

Commands 3-53

-file <filename> (Optional). Specifies the name of the output file where the data is written. If the -file argument is omitted, timing information is reported to the console. <instance_name> Identifies the name(s) of the instance(s) for which timing information is written. If -recursive option is given, only one instance name is allowed. If multiple names are given, the timing information of the first instance is reported; others are ignored. The timing information of duplicated instances is reported only once. The format of the timing information is Standard Delay Format (SDF). For example,
(CELL (CELLTYPE "and2x1" ) (INSTANCE T.t.dig.a_top.apb.mpeg_top.mpeg_clk_rst_1.u_mpeg_clk) (DELAY (ABSOLUTE ( IOPATH A Y (10)(10) ) ( IOPATH B Y (10)(10) ) ) ) )

Examples
ucli% report_timing -r T.t.dig

This command generates timing report to instance T.t.dig and all the sub-instances underneath it and redirects the output to standard output. This command displays the following output.
(CELL (CELLTYPE "and2x1")
Commands 3-54

(INSTANCE T.t.dig.a_top.apb.mpeg_top.mpeg_clk_rst_1.u_mclk_en) (DELAY (ABSOLUTE ( IOPATH A Y (10)(10) ) ( IOPATH B Y (10)(10) ) ) ) ) more

Signal Value and Memory Dump Specification Commands


dump
This command is used to dump the specified scope or signal value change information to a file during the simulation. Currently supported for VPD format only. The following objects can be dumped using this command. Verilog and VHDL scopes, variables. Complex data structures like VHDL aggregates, VHDL records, Verilog multi dimensional arrays.

Syntax
dump [-file <filename>] [-type VPD] [-locking] dump -add <list_of_nids> [-fid <fid>] [-depth <levels>] [-aggregates] [-ports|-in|-out|-inout] dump -close [<fid>] dump -flush [<fid>] dump -autoflush <on | off> [-fid <fid>] dump -interval <seconds> [-fid <fid>] dump -deltaCycle <on | off> [-fid <fid>]

Commands 3-55

-file <filename> (Optional) Specifies VPD file name and returns a File Handle, fid. If this argument is not specified, VPD information will be dumped to file inter.vpd. In the current implementation only 1 VPD file can be opened for dumping during simulation. VPD0 is the default ID. -type VPD (Optional) This argument specifies the dump file format. In the current implementation only VPD format is supported which is default. -add <list_of_nids> Specifies signals, scopes or instances to be dumped. -depth <levels> (Optional) Specifies the number of levels to be dumped. If argument -add is specified, depth is calculated from the scope specified by the -add argument. If -add is not specified, depth is calculated from the current scope. The default value is 0, which means the entire design is down to the specified scope. Value 1 enables dumping only to the specified scope. -fid <fid> This argument specifies the File ID of VPD file to which the VPD information must be dumped. The file ID, <fid>, is returned by the dump -file command. If this argument is not specified, dump information is written to the VPD file that is currently open. -aggregates

Commands 3-56

This switch enables dumping complex data structures, such as VHDL records and arrays of records, and Verilog multi dimensional arrays. This switch must be used with -add option. -ports|-in|-out|-inout This switch enables dumping only (in/out/-inout) ports. This switch can only be used along with -add option. -close <fid> Closes the dump file specified by File ID 'fid'. The argument <fid> is optional. If this argument is not specified, VCS closes the VPD file currently open. -autoflush <on/off> This switch enables automatic dumping when the tool is stopped by Ctrl-C, $stop, or $finish. By default, autoflush is off. -flush <fid> Forces VCS to flush dump data to the VPD file irrespective of any value change. If -interval is specified, the dump interval is determined by the value specified with the -interval argument. If interval is not specified, data is flushed immediately. The argument <fid> is optional. -interval <seconds> Tells simulator how often to flush VPD information in wall clock time. This command doesn't automatically enable flushing. To enable flushing, use -flush. -deltaCycle <on | off>

Commands 3-57

Turns on dumping delta cycle information. By default, delta cycle dumping is disabled. -locking This option when used insures that VPD file is not being read while it is written or not being written while it is being read. Examples
ucli% dump -file dump.vpd -type vpd

Opens a file by name dump.vpd with FileID VPD0. However this command doesn't record any signals. This command displays the following output.
VCD+ Writer Y-2006.06-6_Full64 Copyright 2005 Synopsys Inc. VPD0 ucli% dump -add [senv scope] -fid VPD0 -depth 2

Adds current scope and 2 levels of hierarchies underneath it to the file with FileID VPD0. This command displays the following output.
1 ucli% dump -autoflush on -fid VPD0

Turns autoflush on using -fid.


ucli% dump -deltacycle on

Turns dumping delta cycle information without using -fid. This command displays the following output.
on

Commands 3-58

ucli% dump -add / -aggregates

Dumps everything from root including complex data types. This command displays the following output.
2 ucli% dump -interval 1 -flush VPD0

Flushes VPD information every second to the file with FileID VPD0.
ucli% dump -close VPD0

Closes the dump file with -fid VPD0

memory
This command is used to load memory type variables in the HDL from a file or writes contents of memory type variables to a file. This command can be used for both VHDL and Verilog memories. Note: The memory command does not support octal radix for Verilog objects. Syntax
memory -read|-write <nid> -file <fname> [-radix <radix>] [-start start_address][-end end_address]

-read Reads values from the file specified by the -file argument and writes into memory type variable. -write

Commands 3-59

Reads values from the memory type variable and writes into the file specified by the -file argument. <nid> Nested identifier (hierarchical path) of the memory type variable. Hierarchy need not be specified if the variable is in the current scope. Relative or absolute hierarchy can be specified. -file <fname> Specifies the file from which values must be read for memory read or written for memory -write command. File name can be specified with relative or absolute path. -radix <hexadecimal|binary|decimal> This argument specifies the radix of the values. Default radix is hexadecimal. Shorthand notation h (hexadecimal), b (binary) and d (decimal) can also be used. -start <start_address> Starting address of the memory type variable to write or read. Default is beginning of the memory type variable defined in the HDL. -end <end_address> End address of the memory type variable to write or read. Default is end of the memory type variable defined in the HDL. Note: Applicable only for Verilog memories.

Commands 3-60

Starting Address (SA) can be greater than End Address (EA). Memory access (read or write) progresses from SA to EA regardless of whether SA is greater or less than EA. The file <fname> should not have more than (absolute value of (SA -(minus) EA) + 1) elements. Example
SA = 1, EA = 10. File <fname> should not have more than abs(SA - EA) + 1 i.e. abs(1 -10) + 1 = 9 + 1 = 10 elements.

Note: For VHDL memories Start & End addresses and radix are only applicable for -write option. Data Format for Input file For VHDL The data format for the input file is as shown below. There are three variables, which you can set a default values that applies for the entire file. ADDRESSFMT This variable sets the default radix for the address value. DATAFMT This variable sets the default radix for the data value. DEFAULTVALUE

Commands 3-61

This sets the default value for unspecified address locations of the memory. For example, if you do not specify any value to address 1, then this default value will be loaded into that address. Also, you can specify the addresses in three different formats as follows: - You can directly specify value to a single address.
address / data

- You can specify the start address with multiple values. The address will be incremented for each data values.
address / addr1_data; addr2_data; ...

- You can specify the address range and the unique data. All the addresses will be loaded with the specified single data.
address range / data

Note: The address must be in increasing order. Do not mix the above specifications. Syntax for Memory File Format
#comments $ADDRESSFMT radix (H | O | B) $DATAFMT radix (H | O | B) $DEFAULTVALUE value address / data address / addr1_data; addr2_data; ... addr_start:addr_end / data

Example: (mem.dat)
#RAM8x8 $ADDRESSFMT H

Commands 3-62

$DATAFMT H $DEFAULTVALUE 0 0000 / E2; C6; 00; 30; 15; 23; 7F; 7F;8E 0009 / 90 000A:000E / 28 000F / 33

For Verilog The following two formats are supported: Format 1: (mem.dat). In this format, Start and End Addresses give by -start and -end options to load the data into memory.
0 1 2 4 5

Format 2: (mem.dat). This format is same as Verilog $reamem format.


@0 0 1 2 4 5 @10 10 11 12

Example
ucli% memory -read signal_mem -file input.mem

Reads data in hexadecimal format from file input.mem and writes into memory variable signal_mem in the current scope.
Commands 3-63

ucli% memory -write signal_mem -file output.mem

Reads data from memory variable signal_mem in the current scope and writes into file output.mem in hexadecimal format.
ucli% memory -write signal_mem -file ../out.mem -radix b

Reads data from memory variable signal_mem in the current scope and writes into file out.mem (relative path) in binary format.
ucli% memory -read top.d1.d2.signal_mem -file /root/xyz/ in.mem -radix decimal

Reads data (in decimal format) from file /root/xyz/in.mem and writes into memory variable top.d1.d2.signal_mem from the current scope.
ucli% memory -write signal_mem -file output.mem -start 5 end 10

Writes data (in hexadecimal format) from file output.mem and writes into memory variable signal_mem in the current scope.

Design Query Commands


search
Searches for design object whose name matches with the pattern specified. Syntax
search [-<filter>] [-scope <scope>] [-depth <level>] [module <module_pattern>] [-limit <limit>] [<name_pattern>]

filter Identifies any of "in inout out ports instances signals variables".

Commands 3-64

scope Identifies the starting scope to search. The default value is the current scope. level Identifies the number of scope levels to search. The default value is 0 (searches all hierarchies). module_pattern Identifies the module name to search, which can have '*' or '?' for pattern matching. limit Specifies the limits for maximum matched items. name_pattern Identifies the name to search, which can have '*' or '?' for pattern matching. Example
dve search as* test.asim1 test.asim2 dve search a* -depth 2 test.asim1 test.asim2 test.risc1.accum test.risc1.address test.risc1.alu1 test.risc1.alu_out test.risc1.alureg test.risc2.accum test.risc2.address

Commands 3-65

test.risc2.alu1 test.risc2.alu_out test.risc2.alureg

show
This command is used to show (display) HDL objects, such as Instances Scopes Ports Signals Variables Virtual buses in a design

This command can be used to display object attributes, such as domain (Verilog or VHDL) fullname (full hierarchy name) parent type where value

If no 'objects' are given, 'show' assumes all the objects in the current scope. If the hierarchical path of an instance is not given, then 'show' assumes current scope. This command supports wildcard (*).
Commands 3-66

Syntax
show [nid] [object(s)] [attribute(s)] [-radix <radix>] NTB Only: show -mailbox [<mid>] show -semaphore [<sid>]

<nid> Nested identifier (Hierarchical path) of scopes, instances, or signals in the HDL. If this argument is not specified, the current scope is used as reference. object(s) (Optional) This argument specifies the object type. Objects can be instances, scopes, ports, signals, variables and virtual types. If this argument is not specified all object types are displayed. The object(s) can be any one of the following options. -instances Shows all the instance(s) in the current scope or in the hierarchy specified by nid. -ports Shows all the port(s) of the current scope or in the hierarchy specified by nid. -signals Shows all the objects defined as regs, wires in the current scope or in the hierarchy specified by nid. -scopes

Commands 3-67

Show all tasks and functions defined in the current scope or in the hierarchy specified by nid. -variables Shows all the objects defined as integer, real in the current scope or in the hierarchy specified by nid. -virtual [<instance(s)>] Displays virtual signals which are created by using virtual (or vbus) command. -attribute(s) (Optional) The attributes can be domain, fullname, parent, type, where and value. If no object(s) is given after attribute(s), then the selected attribute(s) will be displayed for all object(s). By default no attributes are displayed. -domain Displays the domain of the objects. Domain can be Verilog or VHDL. -fullname Displays the full hierarchical name of the object(s). -parent Displays the scope where the object is defined. -type Displays the object type. Type can be one of reg, wire, integer, real, IN, OUT, INOUT, instance. For arrays and multidimensional arrays, the array bounds are also displayed.

Commands 3-68

-where Displays name of the design file and line number in which the object is defined. -value Displays the current simulation value of the object. The value can be displayed in radix (hex|dec|bin|oct) by using -radix option. -radix <hexadecimal|binary|decimal|octal> Specifies the radix in which the values of the objects must be displayed. Default radix is decimal (or set by 'config radix'). Shorthand notation h (hex), b (binary) and d (decimal) can be used. -mailbox [<mid>] Shows a mailbox or all mailboxes and shows the data or blocked threads. Mailbox ID, <mid> is optional. If this argument is not specified, all mailboxes are displayed. It is only applicable for NTB-OV or SVTB. -semaphore [<sid>] Shows a semaphore or all semaphores and shows number of keys (#keys) and/or blocked threads. Semaphore ID, <sid>, is optional. If this argument is not specified, all semaphores are displayed. It is only applicable for NTB-OV or SVTB. Example
ucli% show
Commands 3-69

Displays all the objects in the current scope. Same as 'show *' (using wildcard). This command displays the following output.
probe clk reset IST1 ucli% show IST_1

Display all objects in scope IST_1. This command displays the following output.
TMP TMP1 RESET CLK OUTTOP IST1 _P0 _P1 ucli% show IST_1 -domain -fullname -parent -type -value -where

Displays attributes of instance IST_1. This command displays the following output.
IST1 tbTop.IST1 tbTop {BASE {} {COMPONENT INSTANTIATION STATEMENT}} {} {tbTop.v 18} ucli% show -mailbox

Display all mail boxes in the current scope, data in those mail boxes and blocked threads. This command displays the following output.
mailbox 1: data (2): -->5 -->15. mailbox 2: blocked threads: 3, 4. ucli% show -semaphore

Commands 3-70

Display all semaphores in the current scope, number of keys and blocked threads. This command displays the following output.
semaphore 1: keys (2): blocked threads: 3, 4.

Related Commands search get

drivers
This command is used to display driver(s) of a port, signal, or variable. Note: This command is not supported for NTB-OV and System Verilog test benches. Syntax
drivers <nid> [-full]

<nid> Nested identifier (Hierarchical path) of a single signal, port, or variable. Multiple objects cannot be specified. For vectors, drivers for all bits are displayed. -full Crosses hierarchies to display the drivers of the specified signal. By default only drivers from the local scope are displayed.

Commands 3-71

Example
ucli% drivers clk

Displays driver(s) of the object clk in current scope. This command displays the following output.
1 - port T.host.clk NA - port T.host pci_host tokens.v 1584: pci_host host(clk, rst ucli% drivers clk -full

Displays full driver(s) information of the object clk by crossing the module boundary. This command displays the following output.
1 - port T.host.clk 1 - primterm T.clk_pci.clk nand tokens.v 1598: nand # (15.000) clk_pci (clk, ucli% drivers cbe_

Displays full driver(s) information of the vector object cbe_. This command displays the following output.
1001 - net T.cbe_ 1 T.t.zpl44.PAD tokens.v 11280 1001 T.host.cbe_ tokens.v 4934

Related Commands loads

loads
This command is used to display load(s) information of a port, signal, or variable. Note:

Commands 3-72

This command is not supported in NTB-OV and System Verilog testbenches. Syntax
loads <nid> [-full]

<nid> Nested identifier (Hierarchical path) of a single signal or port or variable. Multiple objects cannot be specified. -full Displays loads for the specified objects in all hierarchies. By default only loads in the local scope are displayed. Examples
ucli% loads irdy_ x - port T.host.irdy_ sx - assignstmt T.host pci_host tokens.v 6887: NA - IfElse T.host pci_host tokens.v 6895: NA - port T.host pci_host tokens.v 1584:

iq_irdy_ = irdy_; if ((((~gnt_) & pci_host host (clk,

ucli% loads irdy_ -full x - port T.host.irdy_ x - assignstmt T.host pci_host tokens.v 6887: iq_irdy_ = irdy_; NA - If T.host pci_host tokens.v 6902: else if ((gnt_ & NA - IfElse T.host pci_host tokens.v 6895: if ((((~gnt_) & x - contassign T.mem pci_mem tokens.v 3111: assign # (0.20001) x - primterm T.t.zpb11.b1.PAD bsuf tokens.v 11276: buf # (1.20) b1(OUT, ucli% loads cbe_
Commands 3-73

Displays load information of the vector variable cbe_, 1001 - net T.cbe_ 1 T.t.zpl44.PAD tokens.v 11279 0 T.host.rd_par tokens.v 6369 1001 T.mem.i_cbe_ tokens.v 3108

Related Commands show

Macro Control Routines


do
This command reads a macro file into simulator. Macro files are similar to source command files except that additional commands are enabled that provide more control over the following: Simulation Break Points (onbreak) Error Conditions (onerror) User Input (pause)

The do command can be called recursively i.e. one macro file can load another macro file. Each macro file can have its own local onbreak and onerror scripts. You can switch to interactive mode using pause and then resume execution of the macro file by using resume or abort the execution of the remaining commands in the macro file by using abort. There are two ways in which you can read a macro file into simulator. 1. From the command line using -do option.
Commands 3-74

simv -ucli -do onbreak.tcl

2. From UCLI shell using do command.


ucli% do onbreak.tcl

Syntax
do [-trace [on|off]] [-echo [on|off]] <filename> [<macro parameters>]

filename The UCLI macro file name. If the do command is run from the command line, then the filename should be specified to the current working directory. If the do command is called from another macro file, then this new macro file is sought relative to the directory of the calling macro file. macro parameters The optional parameter values that can be passed to macro file. These parameters can be accessed using variables $1, $2 etc. The $argc variable contains the total number of actual variables. -trace [on|off] Tracing is used to display the commands being executed from the macro file. By default, trace is off i.e. no commands in the macro file is displayed during execution. To display each commands, use the -trace on option. -echo [on|off] Displays output of the evaluated command. By default, echo is off i.e. no output of the evaluated command is not displayed. To display the output, use the -echo on option.

Commands 3-75

Example Assume that, // onbreak.tcl file contains following code.


onbreak {puts "SNPS: Break point on reset hit"; run} stop -once -change RESET run

// onerror.tcl file contains following code.


onerror {puts "SNPS: Error occurred"; resume} show -type error_sig1 puts "SNPS: After Error, other commands executed"

// onerror_main.tcl file contains following code. This file calls onerror_sub.tcl.


onerror {puts "SNPS: Error occurred"; do onerror_sub.tcl} show -type error_sig1 puts "SNPS: In Main Scr: After Error, other commands executed" run

// onerror_sub.tcl file contains following code.


onerror {puts "SNPS: Error occurred in sub do script"; resume} force error_sig2 puts "SNPS: In Sub Scr: After Error, other commands executed" ucli% do onbreak.tcl

This command reads macro file onbreak.tcl. This command displays the following output while the breakpoint is hit during simulation

Commands 3-76

SNPS: Break point on reset hit ucli% do onerror.tcl

This command reads macro file onerror.tcl. This command displays the following output when the specified object is incorrect with the show command.
file onerror.tcl, line 2: Error: Unknown object: error_sig1 SNPS: Error occurred SNPS: After Error, other commands executed ucli% do -trace on -echo on onerror.tcl

This command reads macro file onerror.tcl. This command displays the following output.
1 onerror {puts "SNPS: Error occurred"; resume} puts "SNPS: Error occurred"; resume 2 show -type error_sig1 Error: Unknown object: error_sig1 file onerror.tcl, line 2: Error: Unknown object: error_sig1 SNPS: Error occurred 3 puts "SNPS: After Error, other commands executed" SNPS: After Error, other commands executed

ucli% do onerror_main.tcl

This command reads macro file onerror_main.tcl. The file onerror_main.tcl in turn calls onerror_sub.tcl. This command displays the following output.
file onerror_main.tcl, line 2: Error: Unknown object: error_sig1 SNPS: Error occurred file ./onerror_sub.tcl, line 2: Error: Illegal usage, at least two arguments expected usage: force <name> <value> SNPS: Error occurred in sub do script

Commands 3-77

SNPS: In Sub Scr: After Error, other commands executed SNPS: In Main Scr: After Error, other commands executed

Related Commands onbreak onerror pause resume abort status

onbreak
This command is used to specify an action to execute when a stoppoint, $stop task or CTRL-C is encountered while executing a macro file. Each macro file can define its own local onbreak script. The script can contain any commands. The script is not re-entrant i.e. a command (Example: run) which causes another break point will not rerun onbreak script. If an onbreak script is not defined in a macro file, then a break point will cause macro to enter pause mode. Syntax
onbreak [{commands}]

Commands 3-78

commands Any UCLI command can be specified. Multiple commands should be specified with a semicolon. Example Assume that, //onbreak.tcl file contains following code.
onbreak {puts "SNPS: Break point on reset hit"; run} stop -once -change RESET run ucli% do onbreak.tcl

This command reads macro file onbreak.tcl into simulator. This command displays the following output.
SNPS: Break point on reset hit ucli% do onbreak_nocmmand.tcl

This command reads macro file onbreak_nocommand.tcl into simulator. This script defines no commands to be executed when simulator stops. So simulator pauses. This command displays the following output.
Pause in file onbreak.tcl, line 4 pause%

Related Commands do onerror pause


Commands 3-79

resume abort status

onerror
This command is used to specify an action to execute when an error is encountered while executing a macro file. Each macro file can define its own local onerror script. The script can contain any commands. The script is not re-entrant i.e. a command (Example: run) which causes another error will not rerun onerror script, rather this will cause the macro to abort. If an onerror script is not defined in the macro file, then the default error script will be used (see config). If no default script exists, then an error will cause the macro to abort. Syntax
onerror [{commands}]

commands Any UCLI commands can be specified. Multiple commands should be specified with a semicolon. Examples Assume that, // onerror.tcl file contains following code.
onerror {puts "SNPS: Error occurred"; resume}

Commands 3-80

show -type error_sig1 puts "SNPS: After Error, other commands executed" ucli% do onerror.tcl

This command reads macro file onerror.tcl into simulator. This command displays the following output.
file onerror.tcl, line 2: Error: Unknown object: error_sig1 SNPS: Error occurred SNPS: Error is resumed and other commands executed

Related Commands do onbreak pause resume abort status

resume
This command is used resume execution of a macro file after simulator encounters a breakpoint, error or pause. Syntax
resume

Commands 3-81

Examples Assume that, // onbreak.tcl file contains following code.


onbreak {puts "SNPS: Break point on reset hit"; resume} stop -once -change RESET run ucli% do onbreak.tcl

This command reads macro file onbreak.tcl into simulator. After the breakpoint is hit, the tool waits for user input. This command displays the following output.
SNPS: Break point on reset hit

Related Commands do onbreak onerror pause abort status

Commands 3-82

pause
This command interrupts execution of the macro file. In pause mode, the prompt is displayed as pause% and simulator will accept input from command line. In this mode, you can execute any UCLI command. In this mode, status can be used to display stack of macro files, resume can be used to resume execution of macro files or abort can be used to abort the execution of macro file. Syntax
pause

Examples Assume that, // onbreak.tcl file contains following code.


onbreak {puts "SNPS: Break point on reset hit"; pause} stop -once -change RESET run ucli% do onbreak.tcl

This command reads macro file onbreak.tcl into simulator. After the breakpoint is hit, the tool pauses. This command displays the following output.
SNPS: Break point on reset hit Pause in file onbreak.tcl, line 4 pause%

Related Commands do onbreak


Commands 3-83

onerror resume abort status

abort
This command is used to stop execution of a macro file and remaining commands in the macro file are discarded. After execution of this command, the user will be taken to UCLI prompt. This command can be used in the onbreak or onerror scripts, at the pause prompt (pause%) or in a macro file. Syntax
abort [n | all]

n Stops executing n levels of macro files. Default is 1. This argument should be an integer. This argument is useful for nested macro files. all Stops executing all macro files. Examples Assume that, // onbreak.tcl file contains following code.
onbreak {puts "SNPS: Break point on reset hit"; abort}

Commands 3-84

stop -once -change RESET run ucli% do onbreak.tcl

This command reads macro file onbreak.tcl into simulator. When the breakpoint is hit, the tool stops executing remaining commands in the macro file and returns to UCLI prompt. This command displays the following output.
SNPS: Break point on reset hit ucli%

Related Commands do onbreak onerror resume pause status

status
This command displays the stack of nested macro files being executed. By default, the following information is displayed: Macro file name Line number being executed in the macro file The command which caused the macro file to pause

Commands 3-85

The onerror script (if present)

Syntax
status [file | line]

file Returns the name of the macro file currently being executed. line Returns line number being executed in the current macro file. Examples Assume that, // onerror_main.tcl file contains following code. This file calls onerror_sub.tcl.
onerror {puts "SNPS: Error occurred"; do onerror_sub.tcl} show -type error_sig1 puts "SNPS: After Error, other commands executed" run

// onerror_sub.tcl file contains following code.


onerror {puts "SNPS: Error occurred in sub do script"; pause} force error_sig2 puts "SNPS: After Error, other commands executed" ucli% do onerror_main.tcl

This command reads macro file onbreak_main.tcl into simulator. After the breakpoint is hit, the tool pauses. At the pause prompt (pause%), issue status command. This command displays the following output.
Commands 3-86

file onerror_main.tcl, line 2: Error: Unknown object: error_sig1 SNPS: Error occurred file ./onerror_sub.tcl, line 2: Error: Illegal usage, at least two arguments expected usage: force <name> <value> SNPS: Error occurred in sub do script Pause in file ./onerror_sub.tcl, line 2 pause% status Macro 2: file ./onerror_sub.tcl, line 2 executing command: "force error_sig2" onerror script: {puts "SNPS: Error occurred in sub do script"; pause} Macro 1: file onerror_main.tcl, line 2 executing command: "show -type error_sig1" onerror script: {puts "SNPS: Error occurred"; do onerror_sub.tcl} pause% status file ./onerror_sub.tcl pause% status line 2

Related Commands do onbreak onerror resume pause abort

Commands 3-87

Coverage Command
Coverage
This command is used to enable/disable toggle or line coverage on any coverage watch point(s) during simulation. Coverage watch points are those portions of source code on which coverage is enabled. For more information about coverage and coverage metrics, see the VCS Coverage Metrics User Guide. Note: - Coverage must be enabled (using -cm tgl | line | tgl+line) during compile time. - Default status of toggle or line coverage is on at the beginning of simulation. - This command is supported only in the pure VHDL and MixedHDL (with VHDL top) flows. Syntax
coverage -tgl on|off coverage -line on|off coverage -tgl on|off -line on|off

coverage -tgl on|off Turns on/off toggle coverage. coverage -line on|off Turns on/off line coverage. coverage -tgl on|off -line on|off

Commands 3-88

Turns on/off toggle and line coverages. Examples


ucli% coverage -tgl on -line off

Enables toggle coverage and disables line coverage. This command displays no output.

assertion
This command is used to display statistical information like pass, fail, or failattempts of System Verilog Assertions (SVA) or PSL assertions. This command can also be used to perform the following tasks: Set a break point on an assertion failure Display existing assertions in the source code

Note: - This command currently supports System Verilog Assertions (SVA) and PSL assertions only. - Terms fail, failattempts, and pass have been derived from SVA. Refer to $VCS_HOME/doc/UserGuide/pdf/sva_quickref.pdf for further information. - The source code must be compiled with -sverilog switch. - Wildcard support inside hierarchical path specification (<path>/ <assertion>) is not supported yet.

Commands 3-89

- The option [-r /|<path>/<assertion>] in the syntax below should always be at the end of the command. Always -r option must be followed by a scope name. -r means recursively visit every sub-scope under a given scope. / means root. - When assertion name or scope name is specified in the command, the path name delimiters are based on language domains. For example, For Verilog only and Verilog top designs, the assertion name or scope name should be specified as test1.test2.a1. For VHDL only and VHDL top designs, the assertion name or scope name should be specified as test1/test2/a1.

Syntax You can use the assertion command in the following ways: 1. assertion count <-fails|-failattempts> <-r / | <path>/<assertion>> This command is used to find fails or failattempts of - a single assertion (by specifying hierarchical path of the assertion) or - all assertions in a particular scope and all sub-scopes below it (by specifying option -r / or -r /<scope>). The number returned tells you whether a particular assertion (or all assertions) has failed or not. It doesn't tell you how many times a particular assertion (or all assertions) has failed. 2. assertion report [-v] [-file <filename>] [-xml]

Commands 3-90

<-r /| <path>/<assertion>> This command is used to generate statistical report. Using -file option this report can be redirected to a file, name given by filename. By default, the information reported contains number of successes and failures. Using -v option number of attempts and incompletes can also be reported. Note: Currently -xml option is not supported. 3. assertion <pass|fail> [-enable|-disable|-limit [<count>]] -log <on|off> <-r /|<path>/<assertion>> This command is used to turn on or off information to be reported (to stdout or to a file). By default log is on so assertion report command reports information. Note: Currently [pass|fail][-enable|-disable|-limit] options are not supported. 4. assertion fail -action <continue|break|exit> [-r /|<path>/<assertion>] This command is used to set a break point on an assertion failure. The break option is used to set a break point whereas continue option is used to delete a break point. Note: Currently exit option is not supported. 5. assertion name [-r] <ScopeName>
Commands 3-91

This command returns the hierarchical name of all the assertions present in a particular scope. If -r is used, then this command displays hierarchical references of all the assertions present in a particular scope and all sub-scopes below it. Examples
ucli% assertion name /m

This command displays hierarchical references of assertions present in the scope /m. This command displays the following output.
m.A1 m.A2 ucli% assertion count -fails m.A1

This command returns 1 if assertion m.A1 fails, else returns 0. This command displays the following output.
0 ucli% assertion count -fails -r /m

This command returns number of times all assertions from scope m and below have failed. This command displays the following output.
0 ucli% assertion fail -action break m.A1

This command sets break point on failure of assertion m.A1. This command displays the break point id.
2 ucli% assertion report m.A1

This command displays statistical report of assertion m.A1. This command displays the following output.

Commands 3-92

"m.A1", 7 successes,

2 failures

ucli% assertion report -v -r /

This command generates statistical report and redirects to stdout. The report contains number of attempts, successes, failures and incompletes.
"m.A1", 0 attempts, 0 successes, 1 failures, 2 incompletes "m.A2", 0 attempts, 2 successes, 0 failures, 2 incompletes

Helper Routine Commands


help
This command is used to display usage information of a specific command or to display all UCLI commands. Syntax
help [[-text|-info|-full] <cmd>]

-text <cmd> This option is used to display one line description of any UCLI command given by cmd. -info <cmd> This option is same as -text option and additionally also displays command line options of UCLI command cmd. This command is same as help cmd. -full <cmd>

Commands 3-93

This option is used to display complete usage information of UCLI command cmd. The following commands are supported in UCLI
abort ace alias assertion call cbug change config coverage do drivers dump expr finish fanin force fsdb get listing loads memory next onbreak onerror pause power Halts evaluation of a macro file. Evaluates analog simulator command. Creates an alias for a command. Statistic functions like fails/failattemps counting of assertions. Executes a system task or function within the tool. Debugging support for C, C++ and SystemC source files. Changes the value of a variable; the tool may override value. Displays current settings for configuration variables. Evaluates coverage command(s). Evaluates a macro script. Obtains driver information for a signal/variable Creates/manipulates/closes dump value change file information. Evaluates an expression in the tool. Allows the tool to finish, then return control back to UCLI. Extracts the fanin cone of the specified signal(s). Forces value onto signal/variable; the tool may NOT override. Debussy FSDB Command Set for VCS(-MX). Obtains the value of a signal/variable. Displays source text on either side of 'current' point. Obtains load information for a signal/variable. lLoads or write memory type values fromor to a file. Advances the tool stepping over tasks and functions. Specifies script to run when a macro hits a stop-point. Specifies script to run when a macro encounters an error. Interrupts the execution of a macro file. Measures power.

Commands 3-94

release report_timing restart restore resume run save scope search senv sexpr show stack start status step stop tcheck Tcl thread unalias vbus virtual

Releases a variable from the value assigned using 'force'. Reports timing information of given instance(s) to specified. Restarts tool execution, and keep the your setting in the last. Restores simulation state saved in a file. Restarts execution of a paused macro file from the point where it stopped Advances the tool and stop Saves simulation state into a file Gets or changes the current scope Locates design objects whose names match the name. Displays one or all env array elements Evaluates an expression in the tool. Displays design information for a scope or nested identifier. Displays thread information or move the call stack Starts tool execution Displays the macro file stack Advances the tool one statement Adds or displays stop breakpoints Disable/enable timing check upon an specified instance/ port at runtime. Help for Tcl built-in commands Displays thread information or move the current thread Removes one or more aliases. Creates, deletes, or displays a virtual object. Creates, deletes, or displays a virtual object.

Examples
ucli% help

This command displays one line usage information of all the UCLI commands.

Commands 3-95

ucli% help -text start

This command displays one line usage information of the command start. This command displays the following output.
start ucli% help -info start Start tool execution

This command displays one line usage information and command line options of the command start. This command displays the following output.
start Start tool execution usage: start <toolname> [cmd line options] ;# start tool execution ucli% help -full start

This command displays complete usage information of the command start. This command displays the following output.
start Start tool execution usage: start <toolname> [cmd line options] ;# start tool execution

Normally, the start command will reset config values to their default state. Use "config reset off" to prevent start from resetting your configuration. Examples
start start start start simv simv -l sim.log ;#create log file 'sim.log' simv -a sim.log ;#append to log file 'sim.log' simv -k sim.key ;#create command file'sim.key'

Commands 3-96

alias
This command is used to create an alias for UCLI command. Note: There are many default aliases in UCLI. Examples
get is aliased as synopsys::get. scope is aliased as synopsys::scope.

Syntax
alias [<name> <command>]

name This argument specifies the alias name. command This argument specifies the UCLI command the name should be an alias for. Examples
ucli% alias

This command displays all the commands that are currently aliased.
ucli% alias my_start start

This command creates an alias my_start for the UCLI command start. This command displays new alias as output
my_start

Commands 3-97

listing
This command is used to display source code on either side of the executable line from the tool current or active scope. For more information, see the section Current versus Active Point. Syntax
listing [-nodisplay] [-active|-current] [-up|-down] [<nLines>] listing [-nodisplay] [-file <fname>] -line <lineno> [<nLines>]

-active|-current This option is used to display code from either the active point or current point. By default the source code is displayed from the active point. This is referred to as listing point. nLines This option is used to display nLines above and below the listing point. This number is sticky i.e. subsequent calls to command listing will use this value. The default value of nLines is 5. -up|-down This option is used to move the listing point up or down by a page and display code. A page is defined as 2 * nLines. However this doesn't move current or active point. -line <linenumber> This option is used to move the listing point line number specified by linenumber and display text. However this doesn't move current or active point.
Commands 3-98

-file <filename> -line <linenumber> This option is used to move the listing point to line number specified by linenumber in the file specified by filename and display text. However this doesn't move current or active point. -nodisplay This option is used to turn the display of text off. This option can be used together with any of the options mentioned above to move the listing point. Examples
ucli% listing

This command displays 5 lines above and 5 lines below from the listing point in the current scope. The output of this command depends on source code.
ucli% listing -nodisplay 10

This command sets number of lines of source code displayed (on subsequent call to command listing) to 10. This command displays no output, Related Commands scope

config
This command can be used to display or change the current configuration settings. Syntax
config [var] [value]

Commands 3-99

var This argument is any configuration variable. The configuration variables supported are endofsim, followactivescope, onerror, prompt, radix, reset, resultlimit, resultlimitmsg, sourcedirs and timebase value This argument depends on configuration variable selected. The following options are possible with config command. onerror <script> If a do macro doesn't define a local onerror script, this script will be used. (Local onerror scripts are only enabled when processing macros) The config onerror script will also be run if an error occurs in a i file. If the onerror script reports a Tcl error, execution of the do or -i file will abort. endofsim (noexit | toolexit | exit) Controls behavior after tool event queue is empty. The options are as follows: - noexit - tool remains active and connected to the debugger, - toolexit - tool exits and debugger remains active, - exit - tool and debugger exit which is also the default option. followactivescope (on | off) Controls whether current scope should follow active scope. Default is off.

Commands 3-100

prompt (scope | default | <user-defined-proc>) Changes the command prompt. If scope is specified, the prompt displays the current scope (or active scope if config followactivescope is on). If default is specified, the prompt is reset to the default string, which is ucli%. If a value other than scope or default is specified, the value is expected to be the name of a proc defined by the user. That proc should return a string to use as the prompt. radix (binary | decimal | octal | hexadecimal) Sets the radix used for values returned by UCLI commands. Default radix is decimal. reset (on | off) Specify on to have the start command reset config variables to their default state. Specify off to keep the current config state after a start. The default is on. sourcedirs <dir1> <dir2> ... Specifies a space-separated list of directories to be searched when looking for source files. The list given on the command line replaces the existing search list. Use an empty string to delete the entire list. timebase [number]<unit> Sets the timebase used for setting the time unit for UCLI commands. The optional number is one of 1, 10 or 100 and unit is one of fs, ps, ns, us, ms or s. Default is the timePrecision value, see senv timePrecision. resultlimit <number>

Commands 3-101

Sets the maximum number of items returned by a command. Where the <number> is an integer. Default is 1024. Even if show command has more than 1024 items to be displayed, it displays only 1024 items. After displaying resultlimit items, the simulator gives the following warning message. Warning: The number of results has reached the maximum (1024). More results are omitted. resultlimitmsg (on | off) Controls whether message is displayed when resultlimit is exceeded. Default is on. Examples
ucli% config

This command displays current configuration settings and their values. This command displays the following output.
endofsim: exit followactivescope: auto onerror: {} prompt: default radix: decimal reset: on resultlimit: 1024 resultlimitmsg: on sourcedirs: {} timebase: 1PS ucli% config radix binary

This command changes the default radix in the tool to binary. This command displays value of changed variable.
binary

Commands 3-102

Related Commands senv

Multi-Level Mixed-Signal Simulation


ace
ACE (Analog Circuit Engine) Commands Interface. This command is used to send arguments 'as an interactive command string' to the transistor-level simulators like Nanosim, TimeMill or PowerMill. Note: This command can be used only with Analog Co-Simulation. Syntax
ace <analog_cmd> [options]

analog_cmd Any transistor-level simulator command. options Any options to the above analog_cmd command. Examples
ucli% ace help

This command displays all transistor-level simulator commands. This command displays the following output.
Analysis and Trace ==================

Commands 3-103

get_inst_param get_sim_time list_elem_name

Specman Interface Command


sn
This command can be used to do the following tasks: Execute Specman e code while still in the UCLI shell. Go to Specman prompt, execute e-code and come back to UCLI. You can return to UCLI prompt from Specman prompt by issuing restore command at Specman prompt. Note: All Specman related environmental settings needs to be set before executing this command. For more information on how to set your environment and run Specman, see the appendix "Using VCS MX ESI Adapter" in the VCS MX User Guide. Syntax
sn [Specman_Commands]

Specman_Commands Specman related commands. Examples


ucli% sn

Commands 3-104

This command displays all Specman prompt. All Specman related e-code commands can be executed here. This command displays the following output.
Specman> ucli% sn load test.e

This command executes Specman e-code in the file test.e without leaving UCLI prompt. The output of this command depends on ecode in test.e.

Commands 3-105

Commands 3-106

4
Using the C, C++, and SystemC Debugger4
Note: The C, C++, and SystenC Debugger is a limited-customeravailability (LCA) release. You can use LCA features without requiring a special license from this release onwards. To enable the LCA features, you must use the following compile-time option at the VCS command prompt:
vcs -lca Y-2006.06-SP1

This appendix describes debugging VCS and VCS MX designs that include C, C++, and SystemC modules with UCLI. It contains the following sections. Getting Started Commands Supported by the C Debugger Common Design Hierarchy

Using the C, C++, and SystemC Debugger 4-1

Interaction with the Simulator

Getting Started
This section describes how to get started using CBug with UCLI.

Using a Specific gdb Version


Debugging of C, C++ and SystemC source files relies upon a gdb installation with specific patches. This gdb is shipped as part of the VCS image and is used per default when CBug is attached. No manual setup nor installation of gdb is needed.

Starting UCLI with the C-Source Debugger


The following steps outline the general flow for using UCLI to debug VCS or VCS MX (Verilog, VHDL, and mixed) simulations containing C, C++, and SystemC source code. Note that the -debug_all flag enables line breakpoints for the HDL (Verilog, VHDL) parts only but not for C files as well. C files must be compiled with the "-g" C compiler option. Do this as follows: When invoking the C/C++ compiler directly:
gcc ... -g ... g++ ... -g ...

When invoking one of the VCS tools:


vcs ... -cflags -g ... syscan ... -cflags -g ... syscsim ... -cflags -g ...

Using the C, C++, and SystemC Debugger 4-2

The following steps describe attaching the C-source debugger to run DVE to debug VCS or VCS MX (Verilog, VHDL, and mixed) simulations containing C, C++, and SystemC source code. 1. Compile your VCS or VCS MX with C, C++, or SystemC modules as you normally would, making sure to compile all C files you want to debug. For example, with a design with Verilog on top of a C or C++ module:
gcc -g [options] -c my_pli_code.c vcs +vc -debug_all -P my_pli_code.tab my_pli_code.o

Or with a design with Verilog on top of a SystemC model


syscan syscan -cflags -g syscan -cpp g++ -cflags "-g" my_module.cpp:my_module vcs -cpp g++ -sysc -debug_all top.v

Note that you must use -debug or -debug_all to enable debugging. 2. Start UCLI as follows:
simv -ucli

3. Start the C debugger as follows:


ucli% cbug

The command synopsys::cbug will explicitly start the C debugger. The C debugger will also start automatically when a breakpoint is set in a C source code file.

Using the C, C++, and SystemC Debugger 4-3

Detaching the C-source Debugger


You can detach and reattach the C-source debugger at any time during your session. To detach the C-source debugger, enter cbug -detach on the console command line.

Commands Supported by the C Debugger


These commands are supported by the C debugger: continue run next next -end step finish get -values stack dump (of SystemC objects)

cbug These commands are not supported: save restore

Using the C, C++, and SystemC Debugger 4-4

release (applied to C or SystemC signals) drivers (applied to C or SystemC signals) loads (applied to C or SystemC signals)

Note that save/restore is supported for Verilog and VHDL but not in C code models. The internal state of any user-written C, C++, and SystemC model is not saved/restored, meaning that the save/ restore feature does not work when C code is involved in the simulation. Note: This section uses the full UCLI command names. If you are using a command alias file such as the Synopsys-supplied alias file, enter the alias on the UCLI command line. See the UCLI User Guide for more information. cbug Enables debugging of C, C++, and SystemC source code cbug -detach Disables debugging of C, C++, and SystemC source code scope The scope command is supported for SystemC instances. show show [-instances|-signals|-ports] is supported for SystemC instances, for example "show -ports top.inst1". Any other type such as -scopes, -variables, -virtual is not supported for SystemC instances. A radix is ignored.

Using the C, C++, and SystemC Debugger 4-5

change The change command is supported within these two strict limitations: - Only variables that are visible in the current scope of the C function (e.g. local variables, global variables, class members.) can be changed. Hierarchical path names like top.inst1.myport are not supported. - The type must be a simple ANSI type like int, char, bool. Changing SystemC bit-vector types like sc_int<> or userdefined types is not supported. Any attempt to set an unsupported datatype will trigger the error message "Unsupported type for setting variable". command Command force -deposit var expr is supported. It has the same functionality and restrictions as command change described above. Other options of the force command like multiple values, timing information or -repeat, -cancel, -drive options are not supported. stack When you are stopped in C code, then you can see the stack list. Each entry of the list tells the source file, line number, function name. The function where your are stopped right now appears at the top of the list. If the source code for a given function has been compiled without compiler flag -g, then the file/line number information is not available. CBug selects without-g.txt in this case.

Using the C, C++, and SystemC Debugger 4-6

Command stack -up|-down move the active scope up or down. The source file corresponding to the active scope is shown and get command applies to this scope. Accessing C/C++/SystemC Elements with the get Command When stopped at a C source location, certain elements are visible and can be queried with the ucli::get command: Function arguments Global variables Local variables Class members (if the current scope if a method) Ports, sc_signal and plain members of SystemC modules anywhere within the combined HDL+SystemC instance hierarchy. Arbitrary expression including function calls, pointers, array indices etc. Please note that some characters such as [ ] need to be enclosed by { } or escaped with \ otherwise Tcl will interpret them.

Examples ucli::get myint ucli::get this->m_counters ucli::get {this->m_counters[2]} ucli::get strlen(this->name) The name given with a synopsys::get <name> argument refers to the scope in the C source where the simulation stopped (the active scope). This is important to keep in mind because C source may

Using the C, C++, and SystemC Debugger 4-7

have multiple objects with the same name but in different scopes.Which one is visible depends on the active scope. This means hat <name> may not be accessible anymore once you step out of a C/C++ function. Accessing SystemC Elements with the get Command through an hierarchical Path Name The argument of synopsys::get may refer to an instance within the combined HDL/SystemC instance hierarchy. All ports, sc_signals and also all plain member variables of an SystemC instance can be accessed with synopsys::get at any time. Access is possible independant of where the simulation is currently stopped, even if it is stopped in a different C/C++ soure file or not in C/C++ at all. Example Assume this instance hierarchy
top (Verilog) middle (Verilog) bottom0 (SystemC)

whereby "bottom0" is an instance of this SC module:


SC_MODULE(Bottom) { sc_in<int> I; // SC port sc_signal<sc_logic> S; // SC signal int PM1; // "plain" member variable, ANSI type str PM2; // "plain" member variable, user-def type }; struct str { int a; char* b; };

Using the C, C++, and SystemC Debugger 4-8

These accesses are possible:


synopsys::get synopsys::get synopsys::get synopsys::get synopsys::get top.middle.bottom0.I top.middle.bottom0.S top.middle.bottom0.PM1 top.middle.bottom0.PM2 top.middle.bottom0.PM2.a

Access is possible at any point in time, independant of where the simulation stopped. Note that this is a difference to accessing local variable of C/C++ functions. They can only be accessed is the simulation is stopped within that function. Please also note that accessing plain member variables of SystemC instances is only possible with synopsys::get but not with synopsys::dump. Format / Radix: The C debugger will ignore any implicitly or explicitly specified radix. The format of the value returned is exactly as it is given by gdb (only SystemC data types are specially dealt with). Besides integers, you can also query the value of pointers, strings, structures, or any other object that gdb can query.

SystemC Datatypes
The C debugger offers specific support for SystemC datatypes, for example, an sc_signal<sc_bv<8>>. When you do a print of such a value, gdb usually returns the value of the underlying SystemC data structure that is used to implement the data type. This is normally by no means what you want to see and is generally useless. The C debugger recognizes certain native SystemC data

Using the C, C++, and SystemC Debugger 4-9

types and prints the value in an intuitive format. For example, it will print the value of the vector in binary format for an sc_signal<sc_bv<8>>. The following native SystemC types are recognized. Templatized channel types C<T1>:
C := { sc_in_clk, sc_in, sc_inout, sc_out, sc_signal, ccss_param } T1 := { bool, [[un]signed] char, [unsigned][long|short] int, [[long] double] float, sc_logic, sc_lv, sc_bit, sc_bv, sc_[u]int, sc_int_base, sc_big[u]int, sc_[un]signed, sc_fxval[_fast], sc_[u]fix[ed][_fast], sc_string, char*, void*, struct X* }

When the value of an object O of such a type C is to be printed, then the C debugger prints the value of O.read() rather than O itself. Native SystemC data types:
T2 := { sc_logic, sc_lv, sc_bit, sc_bv, sc_[u]int, sc_int_base, sc_big[u]int, sc_[un]signed, sc_fxval[_fast], sc_[u]fix[ed][_fast], sc_string }

The C debugger prints values of these data types in an intuitive format. Decimal format is taken for sc_[u]int, sc_int_base, sc_big[u]int,sc_[un]signed, binary format for sc_logic, sc_lv, sc_bit, sc_bv. Example SystemC source code:
sc_in int A sc_out<sc_bv<8>>B;
Using the C, C++, and SystemC Debugger 4-10

sc_signal <void*>; int D; synopsys::get A 17 synopsys::getB 01100001 synopsys::getC 0x123abc synopsys::getD 12

source filename.

Using Line Breakpoints


You can set line breakpoints on C / C++ / SystemC source files using the Breakpoints dialog box or the command line.

Set a Breakpoint
To create a line breakpoint from the command line, enter the stop command using the following syntax:
stop -file filename -line linenumber

For example:
stop -file B.c -line 10 stop -file module.cpp -line 101

Instance Specific Breakpoints Instance specific breakpoints are supported with respect to SystemC instances only. Specifying no instance or instance name "-all" means to always stop, no matter what the current scope is,

Using the C, C++, and SystemC Debugger 4-11

If the debugger reaches a line in C, C++, SystemC source code for which a instance-specific breakpoint has been set, then it will stop only if the following two conditions are met: The corresponding function was called directly or indirectly from a SystemC SC_METHOD, SC_THREAD or SC_CTHREAD process. The name of the SystemC instance to which the SystemC process belongs matches the instance name of the breakpoint.

Please note that C functions called through the DPI, PLI, DirectC or VhPI interface will never stop in an instance-specific breakpoint because there is no corresponding SystemC process. Please also note that you must use the name of the Systemc module instance and not the name of the SystemC process itself. Breakpoints in Functions You can also define a breakpoint by its C/C++ function name with the
stop -in function

command. Examples
stop -in my_c_function stop -in stimuli::clock_action()

Restriction multiple active breakpoints are set in the same line of a C, C++ or SystemC source code file, then the simulation will stop only once.

Using the C, C++, and SystemC Debugger 4-12

Deleting a Line Breakpoint


To delete a line breakpoint, enter stop -delete <index> and press Enter.

Stepping Through C-source Code


Stepping within, into, and out of C sources during simulation is accomplished using the step and next commands. Extra arguments to either step or next such as -lang or -thread are not supported for C code. ONLY next -end IS ALLOWED.

Stepping within C Sources:


You can step over a function call with next or step into a function with step. Note: Stepping into a function that was not compiled with -g is generally supported by gdb and also CBug. However, in some cases gdb becomes confused on where to stop next and may proceed further than anticipated. In such cases, we recommend to set a breakpoint on a C source that should be reached soon after the called function finishes and then issue command continue. Use the stack -up command to open the source code location where you want to stop, set a breakpoint and then continue.

Cross-stepping between HDL and C code


Cross-stepping is supported in many but not all cases where C code is invoked from Verilog or VHDL code. These case are supported:

Using the C, C++, and SystemC Debugger 4-13

From Verilog caller into a PLI C function: note tha this is only supported for the "call" function but not that "misc" or "check" function and also only if the PLI function was statically registered. From the PLI C function back into the Verilog caller. From Verilog caller into DirectC function and also back to Verilog From VHDL caller into an VhPI "foreign" C function that mimics a VHDL function and also back to VHDL: please note that the crossstep is not supported on the very first occasion when the C function is executed. Cross-stepping is possible for 2nd, 3rd and any later call of that function. From Verilog caller into an export "DPI" C function and also back to Verilog At the end of a Verilog export "DPI" task or function back into the calling C function. Note that this cross step HDL->C is only possible if the Verilog code was reached via a cross-step from C->HDL in the first place.

All cross-stepping is only possible if the C code has been compiled with debug information (gcc -g).

Cross-stepping in and out of Verilog PLI Functions


When you steps through HDL code and come to a call of a userprovided C function such as a PLI function like $myprintf, then the next command will step over this function. But the step command will step into the C source code of this function. Consequent step/ next commands walk through the C function and finally you returns to the HDL source. Seamless stepping HDL->C->HDL is thus possible. This feature is called cross-stepping. Cross-stepping is supported only for function that meet this criteria:

Using the C, C++, and SystemC Debugger 4-14

PLI function Statically registered through a tab file The call call only (but not misc or check)

Cross-stepping into other Verilog PLI functions is not supported. However, an explicit breakpoint can be set into these function which will achieve the same effect.

Cross-Stepping in and out of VhPI Functions


Cross-stepping from VHDL code into a C function that is mapped through the VhPI interface to a VHDL function is supported with certain restrictions: cross-step in is not possible on the very first occasion when the C function is executed. Only later calls are supported. A cross-step out of C back into VHDL code is always supported. Cross-stepping is not supported for C code mapped through the VhPI interface onto a VHDL entity. Cross-Stepping in and out of DirectC Functions Cross-stepping from Verilog into a DirectC function is supported, also cross-step back out. There are no restrictions. Cross-Stepping in and out of DPI Code Cross-stepping between [System]Verilog and import/export DPI functions is supported with a few restrictions: Cross-step from Verilog into an import DPI function is always supported.

Using the C, C++, and SystemC Debugger 4-15

Cross-step from an import DPI function back into the calling Verilog source code is supported only if this DPI function was entered with a cross-step in the first place. That means doing continuously step commands will lead from the Verilog caller, into and through the import DPI function and back to the Verilog caller.statement into the import DPI function, through that function and finally back into the calling Verilog statement. However, if the DPI function was entered through a run command and the simulation stopped in the import C function due to a breakpoint, then the cross-step out of the import DPI function into the calling Verilog statement is not supported. The simulation will advance until the next breakpoint is reached.

Cross-step from C code into an export Verilog task or function is always supported. Cross-step from an export DPI task/function back into the calling C source code is supported only if this DPI task/function was entered with a cross-step in the first place. That means doing continuously step commands will lead from the C caller, into and through the import DPI task/function and back to the C caller. However, if the export DPI task/function was entered through a run command and the simulation stopped in the export task/ function due to a breakpoint, then the cross-step out of the export DPI function into the calling C statement is not supported. The simulation will advance until the next breakpoint is reached.

Cross-stepping from C into HDL:


Stepping from C code (that is called as a PLI/... function) into HDL code is generally supported. There are two ways to do this.

Using the C, C++, and SystemC Debugger 4-16

If the C function was reached by previously cross-stepping from HDL into C, then CBug is able to automatically transfer control back to the HDL side once you step out of the C function. In this case, just type step or next in C code. In all other cases, CBug is not able to detect that the C domain is exited and needs an explicit command to transfer control back to the HDL side. When you do a step or next command that leaves the last statement of a C function called from HDL, then the simulation will stop in a location that belongs to the simulator kernel. There will be usually no source line information available since the simulator kernel is generally not compiled with -g, so you will not see a specific line/file information.Instead, file withoutg.txt will be displayed. If this happens, you can proceed as follows:
synopsys::continue or run

or
next -end

The continue will bring you to the next breakpoint which could be in either HDL or C source code. The next -end command will stop as soon as possible in the next HDL statement or the next breakpoint in C code, whichever comes first. Again, use commands synopsys::continue or synopsys::next -end to proceed.

Cross-Stepping in and out of SystemC Processes


The C debugger does offer specific support for the SystemC kernel.

Using the C, C++, and SystemC Debugger 4-17

If you step out of a SC_METHOD process, then a step or next statement will stop in the next SystemC or HDL process that is executed. If you step into a wait(...) statement of an SC_[C]THREAD process, then a step or next statement will stop in the next SystemC or HDL process that is executed. Doing step or next statements continuously will eventually come back to the next line located after the wait(...) statement. If stopped in SystemC source code, a step/next command will stop at the next statement exactly like it does with gdb.

Direct gdb Commands


You can send certain commands directly to the underlying gdb through UCLI command cbug::gdb. The command will be executed right away and the UCLI command will return the response from gdb. The command is
cbug::gdb gdb-cmd

gdb-cmd is an arbitrary command accepted by gdb including an arbitrary number of arguments, for example info sources. Doing cbug::gdb will automatically attach CBug, send <gdb-cmd> to gdb and return the response from gdb as the return result of the Tcl routine. The result may have one or multiple lines. The routine returns successfully in most cases, even if gdb itself gives an error response. The routine gives an Tcl error response only when gdb-cmd has the wrong format, for example when it is empty.

Using the C, C++, and SystemC Debugger 4-18

Only a small subset of gdb commands are always allowed. These are commands that for sure do not change the state of gdb or simv, e.g. commands show, info, disassemble, x, etc. Other command make cbug::gdb return with error cannot execute this gdb command because it would break CBug Example:
ucli% cbug::gdb info sources

Source files for which symbols have been read in:


../pythag.c, rmapats.c, ctype-info.c, C-ctype.c, C_name.c, ../../gcc/libgcc2.c

Source files for which symbols will be read in on demand:


ucli% cbug::gdb whatis pythag type = int (int, int, int) ucli%

Add Directories to Search for Source Files


This is directly done with the gdb dir dir-name command. For example:
ucli% gdb dir /u/joe/proj/abc/src

Use this command to check which directories are searched:


ucli% gdb show dir Source directories searched: /u/joe/proj/abc/src:$cdir:$cwd

Adding directories may be needed to locate the absolute location of some source files.

Using the C, C++, and SystemC Debugger 4-19

Example:
ucli% cbug::expand_path_of_source_file foo.cpp Could not locate full pathname, try "gdb list sc_fxval.h:1" followed by "gdb info source" for more details. Add directories to search path with "gdb dir <src-dir>". ucli% gdb dir /u/joe/proj/abc/src ucli% cbug::expand_path_of_source_file foo.cpp /u/joe/proj/abc/src/foo.cpp

Note that adding a directory partially invalidates the cache used to store absolute pathnames. Files for which the absolute path name has already been successfully found and cached are not affected. But files for which the pathname could not be located so far will be tried again the next time if a new directory was added after the last try.

Common Design Hierarchy


An important part of debugging simulations containing SystemC and HDL is the ability to view the common design hierarchy and common VPD trace file. The common design hierarchy shows the logical hierarchy of SystemC and HDL instances in the way it is specified by the user. See also the VCS / DKI documentation for more information how to add SystemC modules to a simulation. The common hierarchy shows these elements for SystemC objects: Modules (instances)

Using the C, C++, and SystemC Debugger 4-20

Processes: - SC_METHOD, SC_THREAD, SC_CTHREAD

Ports: sc_in, sc_out, sc_inout, - sc_in<T> - sc_out<T> - sc_inout<T> - sc_in_clk (= sc_in<bool>) - sc_in_resolved - sc_in_rv<N> - sc_out_resolved - sc_out_rv<N> - sc_inout_resolved - sc_inout_rv<N>

Channels: - sc_signal<T> - sc_signal_resolved - sc_signal_rv<N> - sc_buffer<T> - sc_clock - rvm_sc_sig<T> - rvm_sc_var<T>

Using the C, C++, and SystemC Debugger 4-21

- rvm_sc_event With datatype T being one of - bool - signed char - [unsigned] char - signed short - unsigned short - signed int - unsigned int - signed long - unsigned long - sc_logic - sc_int<N> - sc_uint<N> - sc_bigint<N> - sc_biguint<N> - sc_bv<N> - sc_lv<N> - sc_string All these objects can also be traced in the common VPD trace file. Port or channels that have a different type, for example a userdefined struct, will be shown in the hierarchy but cannot be traced.

Using the C, C++, and SystemC Debugger 4-22

The common design hierarchy is generally supported for all combinations of SystemC, Verilog and VHDL. The pure-SystemC flow (the simulation contains only SystemC but neither VHDL nor Verilog modules) is also supported.

Post-processing Debug Flow


There are different ways to create a VPD file. Not all are supported for common VPD with SystemC: Supported Run the simulation in -ucli mode and apply the synopsys::dump command Interactive using DVE and the Add to Waves... command

Not Supported With $vcdpluson() statement(s) in Verilog code With VCS option +vpdfile

If you create a VPD file in one of the unsupported ways, then you will not see SystemC objects at all. Instead you will find dummy Verilog or VHDL instances at the place were the SystemC instances are expected. The simulation will print warning that SystemC objects are not traced. Use these commands to create a VPD file when SystemC is part of the simulation:
Create file dumpall.ucli : cbug::config add_sc_source_info always synopsys::cbugsynopsys::cbug <-- this line is optional, *1 <-- this line

Using the C, C++, and SystemC Debugger 4-23

is optional, *1 synopsys::scope . set fid [synopsys::dump -file dump.vpd -type VPD] puts "Creating VPD file dump.vpd" synopsys::dump -add "." -depth 0 -fid $fid synopsys::continue

Then run simulation like this:


simv -ucli < dumpall.ucli

The line synopsys:cbug is optional. If specified, then CBug will attach and store in the VPD file the source file/line information for SystemC instances that are dumped. This is convenient for postprocessing: a double-click on a SystemC instance or process will open the source-code file. Note that all source code must be compiled with compiler flag -g which will slow down the simulation speed to some extend (how much varies greatly with each design). Furthermore, attaching CBug will take some CPU time during which the underlying gdb reads all debug information. This seconds runtime overhead is constant. Last, attaching CBug creates a gdb process that may need a large amount of memory if the design contains many C/C++ files compiled with -g flag. In summary, adding the synopsys:cbug s a tradeoff between better debugging support and runtime overhead.

Interaction with the Simulator


Usually CBug and the simulator (the tool, e.g. simv) work together unnoticed by the user. However, there are a few occasion when CBug and the tool cannot fully cooperate and when this is visible to

Using the C, C++, and SystemC Debugger 4-24

the user. These cases depend on whether the active point (the point where the simulation stopped, for example due to a BP) is in the C domain or HDL domain.

Prompt Indicates Current Domain


The prompt reflects if the simulation is stopped in the HDL or C domain. ucli% -> HDL domain CBug% -> C domain

Commands Affecting the C Domain:


Commands that apply to the C domain, for example setting a BP in C source code, can always be issued, no matter in which domain the current point lies. Most commands that apply to the C domain, for example setting a breakpoint in C source code, can always be issued, no matter in which domain the current point lies. Some commands, however, can only be applied when the simulation is stopped in the C domain: The stack command to show which C/C++ functions are currently active.

Using the C, C++, and SystemC Debugger 4-25

Reading a value from C domain (e.g. a class member) with "synopsys::get" command is sensitive to the C function where the simulation is currently stopped. Only variables visible in this C scope can be accessed. That means is not possible to access, for example, local variables of a C/C++ function or C++ class members when stopped in HDL domain. Only global C variables can always be read.

Combined Error Message:


When CBug is attached and the user enters a command such get xyz, then UCLI issues the command to both the simulator and the C debugger (starting with the one where the active point lies, e.g. starting with the tool in case the simulation is stopped in the HDL domain). If the first one responds without error, then the command is not issued again to the second one. However, if both tool and CBug produce an error message, the UCLI combines both error messages into a new one which is then printed. Example:
Error: { {tool: Error: Unknown object} (cbug: Error: No symbol "xyz" in current context.;} }

Update of Time, Scope and Traces


Any time, when the simulation is stopped in C code, the following information is updated: Correct simulation time Scope variable (accessible with synopsys::env scope) is either set to a valid HDL scope or to string "<calling-C-domain>"

Using the C, C++, and SystemC Debugger 4-26

- If you stop in C/C++ code while executing a SystemC process, then the scope of this process is reported. - String "<calling-C-domain>" is reported when the HDL scope that calls the C funcion is not known. This happens, for example, in case of DPI, PLI, VhPI or DirectC functions. All traces (VPD file) are flushed

Configuring CBug
Use the cbug::config UCLI command to configure the CBug behavior. The following modes are supported:

Startup Mode
When CBug attaches to a simulation, then there are two different modes to choose from. Enter the UCLI command:
cbug::config startup fast_and_sloppy|slow_and_thorough

to select the mode before attaching CBug . Mode 'slow_and_thorough' is the default and may consume much CPU time and virtual memory for the underlying gdb in case of large C/C++/SystemC source code bases with many 1000 lines of C/ C++ source code.

Using the C, C++, and SystemC Debugger 4-27

Mode 'fast_and_sloppy' will reduce the CPU and memory needed, however, it comes on the expense that not all debug information is available to CBug right away. Most debugging features will still work fine, but there may be occasional problems, for example, setting breakpoints in header files may not work.

Attach Mode
cbug::config attach auto|always|explicit

Mode 'attach' defines when CBug attaches. Value 'auto' is the default and attaches CBug is some situations, for example when you set a breakpoint in a C/C++ source files and when double-clicking a SystemC instance. Value 'always' will attach CBug whenever the simulation starts. If value 'explicit' is selected, then CBug is never attached automatically.

cbug::config add_sc_source_info auto|always|explicit


The cbug::add_sc_source_info command stores source file/ line information for all SystemC instances and processes in the VPD file. Doing that may take a long time but is useful for post-processing a VPD file after the simulation ended. Value 'auto' invokes cbug::add_sc_source_info automatically when CBug attaches and the simulation runs without the DVE GUI; 'always' invokes cbug::add_sc_source_info automatically whenever CBug attaches; 'explicit' never invokes it automatically. Default is 'auto.'

Using the C, C++, and SystemC Debugger 4-28

Using a Different gdb Version


Debugging of C, C++ and SystemC source files relies upon gdb version 6.1.1 with specific patches. This gdb is shipped as part of the VCS image and is used per default when CBug is attached. No manual setup nor installation of gdb is needed. However, it is possible to select a different gdb installation by setting environment variable CBUG_DEBUGGER before starting the simulation or DVE.

Supported platforms
Interactive debugging with CBug is supported on the following platforms: Linux RH3/RH4/Suse, 32-bit Linux RH3/RH4/Suse, 64-bit (VCS flag -full64 or -mode64) Solaris 5.9/5.10, 32-bit

Interactive debugging with CBug is not supported on these platforms: Solaris, 64-bit -comp64 flow of VCS, all platforms any other platform

An explicit error message is printed when you try to attach CBug on a platform that is not supported.

Using the C, C++, and SystemC Debugger 4-29

For solaris 64-bit, debugging of SystemC modules is only possible in the post-processing flow. Port/signals of SystemC modules can be dumped in a VPD file and later displayed by DVE. Note that this specific platform does not allow tp store source file/line information for SystemC instances; doing a double-click an SystemC instance or process will not open the corresponding source file.

Using SYSTEMC_OVERRIDE
VCS ships with multiple SystemC versions (2.0.1, 2.1, 2.2) which are used per default. In rare cases, it might be necessary to use a different SystemC installation that you compiled on your own. This can be done by setting the SYSTEMC_OVERRIDE environment variable (see the VCS / VCSi User Guide). If you use SYSTEMC_OVERRIDE, then some or all of the SystemC specific CBug features are not available. These features are not available: tracing of SystemC objects (ports, sc_signals) printing of SystemC native datypes like sc_int in an intuitive format. Instead you will see the usual form how gdb prints the data which is generally useless for SystemC objects stopping in the next SystemC user process with next or step.

These feature may or may no work depending on how much different the SystemC installation is compared to an OSCI installation: showing SystemC objects (instances, processes, ports) in the common hierarchy (hierarchy pane in DVE)

Using the C, C++, and SystemC Debugger 4-30

double-clicking an SystemC instance or processes to open the source file cross-stepping in or out of SystemC user processes and HDL code

Any other SystemC specific CBug feature The following non-SystemC specific CBug feature will always work: setting breakpoints in SystemC source code (you may have to open the source file with File/Open File in DVE, though) stepping through SystemC source code. Note that stepping out of one SC user processes and stopping in the next one without a breakpoint is not supported). access a variable/class member with synopsys::get. The variable needs to be visible in scope of the C function where the simulation is currently stopped. Note that enhanced printing of native SystemC types is not available.

Using the C, C++, and SystemC Debugger 4-31

Using the C, C++, and SystemC Debugger 4-32

A
Examples A
This appendix presents examples of debugging designs with UCLI using various tools. The source code for examples used here are in the ucli_installation_examples directory of your UCLI installation. UCLI with VCS on page 1 UCLI with VHDL (VCS MX) on page 7 SystemVerilog Example on page 12 Native TestBench (OV and SV) Examples on page 15

UCLI with VCS


The design getdrivers.v was used in this example. You can find the source code in your VCS installation directory.

A-1

Compiling the VCS Design and Starting Simulation


In this example -debug is used in the vcs command line to specify UCLI as the default command line interface.
%> vcs -debug_all driversget.v Chronologic VCS (TM) Version 7.2_Beta1R15 -- Wed Nov 3 08:07:50 2004 Copyright (c) 1991-2003 by Synopsys Inc. ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure. Parsing design file 'driversget.v' Top Level Modules: top TimeScale is 1 ns / 10 ps Starting vcs inline pass... 1 module and 0 UDP read. recompiling module top if [ -x ../simv ]; then chmod -x ../simv; fi gcc -o ../simv 5NrI_d.o 5NrIB_d.o N654_1_d.o SIM_l.o /fs/Release/linux_VCS7.2_32/virsimdir/linux/vcdplus/ vcs7_2/libvirsim.a /fs/Release/linux_VCS7.2_32/lib/libvcsnew.so -ldl -lm -lc -ldl ../simv up to date CPU time: .100 seconds to compile + .090 seconds to link % > simv -ucli Chronologic VCS simulator copyright 1991-2004 Contains Synopsys proprietary information. Compiler version 7.2_Beta1R15; Runtime version 7.2_Beta1R15; Nov 3 08:08 2004 ucli%

A-2

Running Simulation on the VCS Design


ucli% scope top ucli% senv activeFile: driversget.v activeFrame: activeLine: 3 activeScope: top activeThread: file: driversget.v frame: fsdbFilename: inputFilename: keyFilename: ucli.key line: 3 logFilename: scope: top state: stopped thread: time: 0 timePrecision: 10 ps vcdFilename: vpdFilename: ucli% config defaulterrorscript: {} endofsim: exit followactivescope: off radix: decimal timebase: 10ps ucli% config -followactivescope on on ucli% config -timebase 1ns 1ns ucli% dump -add top.t1 -depth 2 VCD+ Writer 4.4R12A Copyright 1993-2004 Synopsys Inc. 1 ucli% stop -change top.t1.cnt 1 ucli% stop -absolute 3

A-3

2 ucli% step driversget.v, 16 : ucli% step driversget.v, 17 :

ra = 0;

rb = 0;

ucli% listing file ./driversget.v, line 17 12: wire wa, wb, wc, wd, we; 13: 14: initial 15: begin 16: ra = 0; 17:=> rb = 0; 18: rc = 0; 19: rd = 0; 20: re = 0; 21: rf = 0; 22: clk = 0; ucli% run Stop point #1 @ 00 ps; top.t1.cnt = 0 ucli% stop -disable 1 1 ucli% run Stop point #2 @ 3000 ps; ucli% senv time 3000 ps ucli% get top.t1.rc 0 ucli% get top.t1.cnt -radix binary 'b0000 ucli% drivers top.t1.rc 0 - reg top.t1.rc NA - Assignment top.t1 test1 driversget.v 18 : NA - Assignment top.t1 test1 driversget.v 52 : NA - Assignment top.t1

rc = 0; rc = cnt[2];

A-4

test1 driversget.v 54 : rc = cnt[3]; NA - Assignment top.t1 test1 driversget.v 69 : 0: rc = cnt[0]; NA - Assignment top.t1 test1 driversget.v 70 : 1: rc = cnt[2]; NA - Assignment top.t1 test1 driversget.v 73 : rc = cnt[1]; ucli% change top.t1.rc 1'b1 1 ucli% scope top.t1 top.t1 ucli% loads cnt 0 - reg top.t1.cnt[3] NA - Assignment top.t1 test1 driversget.v 42 : cnt = cnt + 1; NA - Assignment top.t1 test1 driversget.v 54 : rc = cnt[3]; NA - EventControl top.t1 test1 driversget.v 66 : always @( cnt ) NA - TaskCall top.t1 test1 driversget.v 103 : task3(re, cnt, fcnt); NA - Wait top.t1 test1 driversget.v 101 : always wait( cnt[2] ) 0 - reg top.t1.cnt[2] NA - Wait top.t1.task3 task3 driversget.v 96 : wait( ~cnt[2] ) NA - Assignment top.t1 test1 driversget.v 42 : cnt = cnt + 1; NA - Assignment top.t1 test1 driversget.v 52 : rc = cnt[2]; NA - Assignment top.t1 test1 driversget.v 58 : rb = cnt[1] | cnt[2]; NA - IfElse top.t1 test1 driversget.v 60 : if( cnt[2] ) NA - Assignment top.t1 test1 driversget.v 70 : 1: rc = cnt[2]; NA - EventControl top.t1 test1 driversget.v 66 : always @( cnt ) NA - TaskCall top.t1 test1 driversget.v 103 : task3(re, cnt, fcnt); NA - Wait top.t1 test1 driversget.v 101 : always wait( cnt[2] )

A-5

0 - reg top.t1.cnt[1] NA - Assignment top.t1 test1 driversget.v 42 : cnt = cnt + 1; NA - Assignment top.t1 test1 driversget.v 47 : ra = cnt[0] ^ cnt[1]; NA - Assignment top.t1 test1 driversget.v 58 : rb = cnt[1] | cnt[2]; NA - Assignment top.t1 test1 driversget.v 73 : rc = cnt[1]; NA - EventControl top.t1 test1 driversget.v 66 : always @( cnt ) NA - TaskCall top.t1 test1 driversget.v 103 : task3(re, cnt, fcnt); NA - Wait top.t1 test1 driversget.v 101 : always wait( cnt[2] ) 0 - reg top.t1.cnt[0] NA - Assignment top.t1 test1 driversget.v 42 : cnt = cnt + 1; NA - Assignment top.t1 test1 driversget.v 47 : ra = cnt[0] ^ cnt[1]; NA - Assignment top.t1 test1 driversget.v 50 : rb = cnt[0]; NA - Assignment top.t1 test1 driversget.v 69 : 0: rc = cnt[0]; NA - EventControl top.t1 test1 driversget.v 66 : always @( cnt ) NA - TaskCall top.t1 test1 driversget.v 103 : task3(re, cnt, fcnt); NA - Wait top.t1 test1 driversget.v 101 : always wait( cnt[2] ) NA - Wait top.t1 test1 driversget.v 114 : wait( cnt[0] ) ucli% show -variables -where -type ucli% stop -disable 1 Warning: watch point '1' already set to 'disable' 1 ucli% stop -disable 2 2 ucli% force rc 1'b1 @0, 1'b0 @5 -repeat 10 ucli% stop -change rc

A-6

3 ucli% run Stop point #3 @ 5000 ps; top.t1.rc = 0 ucli% run Stop point #3 @ 10000 ps; top.t1.rc = 1 ucli% quit V C S S i m u l a t i o n R e p o r t Time: 10000 ps CPU Time: 0.010 seconds; Data structure size: 0.0Mb Wed Nov 3 08:13:36 2004 %>

UCLI with VHDL (VCS MX)


The VHDL files mux.vhd and testbench mux_tb.vhd was used for the example. You can find the source code in your UCLI installation directory.

Compiling the VHDL Design and Starting Simulation


This example shows the command lines for compiling the VHDL
design. %> vhdlan mux.vhd mux_tb.vhd Synopsys 1076 VHDL Analyzer Version 7.2_Beta1R15 -- Nov 02, 2004 Copyright (c) 1990-2004 by Synopsys, Inc. ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys, Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure.

A-7

Parsing design file 'mux.vhd' Parsing design file 'mux_tb.vhd' %> vcs CFG_TB -debug_all vcs -- VCS MX Compiled Simulator Version VCS MX-7.2_Beta1R15 -- Nov 02, 2004 Copyright 1995-2004 by Synopsys Inc., ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure.

%> simv -ucli -i test.key simv -- VCS MX Compiled Simulator Version VCS MX-7.2_Beta1R15 -- Nov 02, 2004 Copyright 1995-2004 by Synopsys Inc., ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure. ucli%

Simulating the VHDL the Design


The step command moves the simulation forward by stepping one line of code.
ucli% senv activeFile: mux_tb.vhd activeFrame: activeLine: 37 activeScope: /MUX_TB activeThread:

A-8

file: mux_tb.vhd frame: fsdbFilename: inputFilename: test.key keyFilename: ucli.key line: 37 logFilename: scope: /MUX_TB state: stopped thread: time: 0 timePrecision: 1 PS vcdFilename: vpdFilename: ucli% config defaulterrorscript: {} endofsim: exit followactivescope: off radix: decimal timebase: 1PS ucli% show U_MUX _P0 T_I3 T_I2 T_I1 T_I0 T_O T_S ucli% scope U_MUX /MUX_TB/U_MUX ucli% dump -file dump.vpd Warning: file type not specified, assuming VPD VPD0 ucli% dump -depth 0 1 ucli% show -type -where -value _P0 {BASE {} {PROCESS STATEMENT}} {mux.vhd 36} {} I3 {VECTOR {} {{2 0}} STD_LOGIC_VECTOR IN PORT} {mux.vhd 7} 0 I2 {VECTOR {} {{2 0}} STD_LOGIC_VECTOR IN PORT} {mux.vhd 8} 0 I1 {VECTOR {} {{2 0}} STD_LOGIC_VECTOR IN PORT} {mux.vhd 9} 0 I0 {VECTOR {} {{2 0}} STD_LOGIC_VECTOR IN PORT} {mux.vhd

A-9

10} 0 S {VECTOR {} {{1 0}} STD_LOGIC_VECTOR IN PORT} {mux.vhd 11} ? O {VECTOR {} {{2 0}} STD_LOGIC_VECTOR OUT PORT} {mux.vhd 12} ? ucli% stop -change O 1 ucli% run Stop point #1 @ 0 PS; /MUX_TB/U_MUX/O = ? ucli% run Stop point #1 @ 10000 PS; /MUX_TB/U_MUX/O = 7 ucli% drivers O 1 - port /MUX_TB/U_MUX/O(2) 1 - process /MUX_TB/U_MUX MUX mux.vhd 36 : 1 - port /MUX_TB/U_MUX/O(1) 1 - process /MUX_TB/U_MUX MUX mux.vhd 36 : 1 - port /MUX_TB/U_MUX/O(0) 1 - process /MUX_TB/U_MUX MUX mux.vhd 36 : ucli% stop 1: -change /MUX_TB/U_MUX/O ucli% stop -disable 1 1 ucli% stop -relative 3 2 ucli% run Stop point #2 @ 10003 PS;

O <=

I0 when S="00" else

O <=

I0 when S="00" else

O <=

I0 when S="00" else

ucli% stop -disable 2 2 ucli% scope -up /MUX_TB ucli% force T_S "01" @0, "10" @5 -repeat 10 ucli% stop -change T_O 3 ucli% run Stop point #3 @ 10010 PS; /MUX_TB/T_O = 5

A-10

ucli% config -radix binary binary ucli% show -value U_MUX {} _P0 {} T_I3 'b001 T_I2 'b010 T_I1 'b101 T_I0 'b111 T_O 'b101 T_S 'b01 ucli% run Stop point #3 @ 10015 PS; /MUX_TB/T_O = 'b010 ucli% show -value U_MUX {} _P0 {} T_I3 'b001 T_I2 'b010 T_I1 'b101 T_I0 'b111 T_O 'b010 T_S 'b10 ucli% step mux.vhd, 36 : O <=

I0 when S="00" else

ucli% config -followactivescope on on ucli% listing 2 file ./mux.vhd, line 36 34: begin 35: 36:=> O <= I0 when S="00" else 37: I1 when S="01" else 38: I2 when S="10" else ucli% step mux.vhd, 37 :

I1 when S="01" else

ucli% step Stop point #3 @ 10020 PS; /MUX_TB/T_O = 'b101

A-11

ucli% step mux.vhd, 36 : ucli% step mux.vhd, 37 : ucli% step mux.vhd, 38 :

O <=

I0 when S="00" else

I1 when S="01" else

I2 when S="10" else

ucli% step Stop point #3 @ 10025 PS; /MUX_TB/T_O = 'b010 ucli% stop -line 87 -file mux_tb.vhd 4 ucli% stop 1: -change /MUX_TB/U_MUX/O -disable 2: -absolute 10003 -disable 3: -change /MUX_TB/T_O 4: -line 87 -file mux_tb.vhd -instance /MUX_TB/U_MUX ucli% stop -disable 3 3 ucli% run 11000 PS Assertion ERROR at 11000 PS in design unit MUX_TB(TB) from process /MUX_TB/_P0: "Error Case 0" mux_tb.vhd, 50 : assert (T_O="111") report "Error Case 0" severity error; ucli% quit

SystemVerilog Example
The design packet.sv was used for the example. You can find the source code in your UCLI installation directory. Note that the vcs compile-time option +sysvcs has been renamed to -sverilog.

A-12

Compiling the SystemVerilog Design and Starting Simulation %> vcs -debug_all -sverilog packet.sv Chronologic VCS (TM) Version 7.2_Beta1R15 -- Wed Nov 3 13:49:02 2004 Copyright (c) 1991-2003 by Synopsys Inc. ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure. Parsing design file 'packet.sv' Top Level Modules: $root test No TimeScale specified Starting vcs inline pass... 2 modules and 0 UDP read. compiling module $root recompiling module test Both modules done. if [ -x ../simv ]; then chmod -x ../simv; fi gcc -o ../simv 5NrI_d.o 5NrIB_d.o E1gK_1_d.o gzYz_1_d.o SIM_l.o /fs/Release/linux_VCS7.2_32/virsimdir/linux/ vcdplus/vcs7_2/libvirsim.a /fs/Release/linux_VCS7.2_32/ lib/libvcsnew.so -ldl -lm -lc -ldl ../simv up to date CPU time: .080 seconds to compile + .090 seconds to link %> simv -ucli Chronologic VCS simulator copyright 1991-2004 Contains Synopsys proprietary information. Compiler version 7.2_Beta1R15; Runtime version 7.2_Beta1R15; Nov 3 13:49 2004 ucli%

A-13

Simulating the SystemVerilog Design Stepping Through HDL Code


ucli% step packet.v, 19 : ucli% step packet.v, 20 : through HDL code to assign default ucli% step packet.v, 21 : bl1 = b1; p1 = {8'h44, 32'h12345678}; // stepping values to p1 #100 $finish;

Setting Breakpoints on Change of Complex Data Types


ucli% stop -change p1.addr 1 ucli% run 0 s; test.p1.addr = 'h44

Printing SystemVerilog Data Types


ucli% show -type -value p1 {STRUCT packet { {addr VECTOR {} {{7 0}} logic} {payload PACKED_UNION { {dword VECTOR {} {{31 0}} logic} {databyte ARRAY {} {{3 0}} BASE {} logic}}}}} {} bl1 {ENUM byte_lane { {b1 1} {b2 2} {b3 3} {b4 4} {b5 5} {b6 6} {b7 7} {b8 8}}} 1 Printing the same data in 32 bit granularity and 8bit granularity ucli% show p1.payload.dword -value p1.payload.dword 'h12345678 ucli% show p1.payload.databyte -value -type p1.payload.databyte ('h78,'h56,'h34,'h12) {ARRAY {} {{3 0}} BASE {} logic}

A-14

Forcing SystemVerilog Data Types


ucli% force p1.addr 8'h03 @0, 8'h09 @5 -repeat 10 ucli% run 5 s; test.p1.addr = 'h09 ucli% run 10 s; test.p1.addr = 'h03

Native TestBench (OV and SV) Examples


The testbench testcase.vr was used for the example. You can find the source code in your UCLI installation directory.

Compiling the NTB OpenVera Testbench and Starting Simulation


%> vcs -debug -ntb testcase.vr Chronologic VCS (TM) Version 7.2_Beta1R15 -- Wed Nov 3 14:04:32 2004 Copyright (c) 1991-2003 by Synopsys Inc. ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure. Parsing vera file 'testcase.vr' Parsing vera file '/fs/Release/linux_VCS7.2_32/include/ vera_defines.vrh' Parsing vera file '/fs/Release/linux_VCS7.2_32/include/ assertions_defines.vrh' Parsing vera file '/fs/Release/linux_VCS7.2_32/include/ vera_defines.vrh' Parsing vera file 'testcase.vr' Top Level Modules: Ptest

A-15

No TimeScale specified Starting vcs inline pass... 1 module and 0 UDP read. recompiling module Ptest if [ -x ../simv ]; then chmod -x ../simv; fi gcc -o ../simv 5NrI_d.o 5NrIB_d.o suzg_1_d.o SIM_l.o / fs/Release/linux_VCS7.2_32/virsimdir/linux/vcdplus/vcs7_2/ libvirsim.a /fs/Release/linux_VCS7.2_32/lib/libvcsnew.so -ldl -lm -lc -ldl ../simv up to date CPU time: .150 seconds to compile + .110 seconds to link 40 eurika101 > simv -ucli Chronologic VCS simulator copyright 1991-2004 Contains Synopsys proprietary information. Compiler version 7.2_Beta1R15; Runtime version 7.2_Beta1R15; Nov 3 14:05 2004 ucli%

Simulating the NTB OpenVera Testbench Setting a Breakpoint in a Task


ucli% stop -in t1 1 ucli% run 0 s; ucli% scope -active Ptest.t1 ucli% listing file ./testcase.vr, line 18 13: stop(); 14: } 15: 16: task t1( 17: { 18:=> delay(10); 19: printf("mailbox data (integer) put\n"); 20: mailbox_put(mb, 5); 21: printf("mailbox data (string) put\n");

A-16

22: 23:

mailbox_put(mb, "mbox_data"); delay(10);

Setting Breakpoints on Mailbox and Semaphore


ucli% show -mailbox mailbox 1 : data available: 0 data: NONE blocked threads: NONE ucli% show -semaphore semaphore: 1 keys available: 5 blocked threads: NONE ucli% stop -mailbox 1 1 ucli% run 0 s; ucli% listing file ./testcase.vr, line 29 24: } 25: 26: task t2() 27: { 28: integer data; 29:=> mailbox_get(WAIT, mb, data); 30: printf("mailbox data got\n"); 31: } 32: 33:34: task t3() ucli% stop -semaphore 1 2 ucli% run 0 s; ucli% listing file ./testcase.vr, line 46 41: printf("semaphore keys put\n"); 42: }

A-17

43: 44: task t4() 45: { 46:=> semaphore_get(WAIT, sem1, 15); 47: printf("semaphore keys got\n"); 48: } 49:

Thread Commands
ucli% 1 : 0 2 : 1 1 3 : 1 2 4 : 1 1 5 : 1 2 thread testcase.vr 7 Ptest.Ptest READY : testcase.vr 18 Ptest.t1 READY : testcase.vr 29 Ptest.t2.unnamed$$_11 BLOCKED : testcase.vr 36 Ptest.t3 READY : testcase.vr 46 Ptest.t4.unnamed$$_13 BLOCKED :

ucli% stop -thread 2 1 ucli% run 10 s; ucli% listing file ./testcase.vr, line 19 14: } 15: 16: task t1() 17: { 18: delay(10); 19:=> printf("mailbox data (integer) put\n"); 20: mailbox_put(mb, 5); 21: printf("mailbox data (string) put\n"); 22: mailbox_put(mb, "mbox_data"); 23: delay(10); 24: }

A-18

Stack Command
ucli% stack 0 : -line 8 -file testcase.vr -scope Ptest.Ptest.unnamed$$_5.unnamed$$_6 1 : -line 19 -file testcase.vr -scope Ptest.t1 ucli% listing file ./testcase.vr, line 19 14: } 15: 16: task t1() 17: { 18: delay(10); 19:=> printf("mailbox data (integer) put\n"); 20: mailbox_put(mb, 5); 21: printf("mailbox data (string) put\n"); 22: mailbox_put(mb, "mbox_data"); 23: delay(10); 24: } ucli% stack -up 0 ucli% listing file ./testcase.vr, line 8 3: program Ptest 4: { 5: integer mb = alloc(MAILBOX, 0, 1); 6: integer sem1 = alloc(SEMAPHORE, 5); 7: fork 8:=> t1(); 9: t2(); 10: t3(); 11: t4(); 12: join all 13: stop();

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A-20

B
CLI / SCL and UCLI Equivalent CommandsB
This appendix lists equivalent CLI and SCL UCLI commands. It is intended for users migrating to UCLI from the VCS Command Language Interface and the Scirocco Command Language. The following sections are included: CLI and UCLI Equivalent Commands SCL and UCLI Equivalent Commands

B-1

CLI and UCLI Equivalent Commands


The following table lists CLI commands with their UCLI equivalents. Note that, not all UCLI commands are listed. Only those UCLI commands that are equivalent to CLI command funcitonality are listed.
CLI Command Tool Advancing Commands
. (period) continue next finish stop -continue stop -continue next finish

Equivalent UCLI Command

Navigation Commands
scope [module_instance_hierarchical_name] upscope scope [-up [level] | -active] [path] scope -up

Signal/Variable/Expression Commands
print %[b|c|t|f|e|g|d|h|x|m|o|s|v] net_or_reg force net_or_reg = value info set reg_or_memory_address [=]value [,reg_or_memory_address[=]value] release net_or_reg get -path [-radix [ binary | decimal | octal | hexadecimal] force -deposit value [ time { value time }* get -path show -scope change -variable value release path

Breakpoint Commands
always [#relative_time|@posedge|@negedge] stop-repeat net_or_reg [relative time(unit) | posedge negedge] -conditon expression] break [#relative_time|@posedge|@negedge] net_or_reg delete breakpoint_number stop [relative time(unit) | posedge negedge] -conditon expression] stop -delete index

B-2

CLI Command
once [#relative_time|##absolute_time| @posedge|@negedge] net_or_reg

Equivalent UCLI Command


stop -once [-absolute | -relative] time[unit][posedge | -negedge ] [-conditon expression ] path stop -once [-absolute | -relative] time[unit] [-posedge | -negedge | change] [-conditon expression ] path

tbreak [#relative_time| ##absolute_time| @posedge| @negedge] net_or_reg

Design Query Commands


show break drivers net_or_reg ports scopes variables drivers [-d | -e] signal_name_list Macro Control Routines define [name [definition]] source filename trace undefine name do | onbreak | onerror -i input filename do -trace|-traceall [on|off] pause | abort show -[ signals | variables | ports | instances | scopes ] path_name drivers signal_name

drivers path_name [-full]

Helper Routine Commands


? help alias [alias_name list [-n | n] unalias alias_name help help alias alias_name UCLI_command_name listing [ n | -n] alias UCLI_command_name alias_name

B-3

SCL and UCLI Equivalent Commands


The following table lists SCL commands with their UCLI equivalents. Note that, not all UCLI commands are listed. Only those UCLI commands that are equivalent to SCL command funcitonality are listed.
SCL Command Tool Invocation Commands
exe_name restart Session Management Commands checkpoint file_name restore file_name Tool Advancing Commands run [relative time] run [-relative | -absolute time] [-posedge | -negedge | -change] path_name save file_name restore file_name start exe_name [options]

Equivalent UCLI Command

Navigation Commands
ls path_name, cd path_name scope [-up [level] | active] path_name

Signal/Variable/Expression Commands
ls -v path_name assign [value] signal/variable_name force value [options] path_name get path_name [-radix radix] change [path_name value] force path_name value [time { , value time }* [ -repeat delay ] ] [ -cancel time ][-deposit] [-freeze] release path_name call [$cmd(...)]

release path_name call procedure_name

Tool Environment Array Commands


env | environment senv <element>

Breakpoint Commands

B-4

SCL Command
monitor -s|-c [options]

Equivalent UCLI Command


stop [-file file_name] [-line num] [instance path_name] [-thread thread_id] [-conditon expression]

Signal Value and Memory Dump Specification Commands


dump -o file_name -vcd|-vpd|-evcd all|deep [depth depth] region/object/ file_name dump [-file file_name] [-type VPD] -add [list_of_path_names -fid fid -depth levels | object -aggregates -close] [-file file_name] [-autoflush on] [-file file_name][-interval <seconds>] [-fid fid] memory [-read|-write nid] [-file file_name] [-radix radix] [-start start_address] [-end end_address]

dump_memory [-ascii_h | -ascii_o | ascii_b] [-start start_address] [-end end_address] memoryName [dataFileName]

Design Query Commands


ls -v path_name drivers [-d | -e] signal_name_list show <-options> path_name drivers path_name [-full]

Helper Routine Commands


help or [command_name] -help alias alias_name scl_command help -full command alias alias UCLI_command

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B-6