library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- uncomment the following lines to use the declarations that are

-- provided for instantiating xilinx primitive components.
--library unisim;
--use unisim.vcomponents.all;

entity jkff2 is
port (j, k, clk, res : in std_logic;
q, qb : out std_logic);
end jkff2;

architecture behavioral of jkff2 is

begin
process (clk, res)
variable q1 : std_logic;
begin
if res = '1' then
q1 := '0';
else
if clk'event and clk = '1' then
if j = '1' and k = '0' then
q1 := '1';
elsif j = '0' and k = '1' then
q1 := '0';
elsif j = '1' and k = '1' then
q1 := not q1;
end if;
end if;
end if;
q <= q1;
qb <= not q1;
end process;

end behavioral;