module bus_enum(

inout
input
input
input
input
input
input
output
output

[31:0]AD_BUS,
[3:0] C_BE,
clk,
reset,
IDSEL,
FRAME,
IRDY,
TRDY,
DEVSEL);

//Global variables
reg [ 5:0] reg_num;
reg [ 2:0] func_num;
reg [ 4:0] dev_num;
reg [ 7:0] bus_num;
reg [20:0] IDSEL_31_11;
reg [31:0] addr_in, data;
reg [ 3:0] cmd, byte_en;
wire [31:0] addr_out = {IDSEL_31_11,addr_in[10:0]};
wire [ 1:0]config_type = addr_in[1:0];
assign DEVSEL = (data == 32'h0000_FFFF) ? 1'b1 : 1'b0;
always @(posedge clk or negedge reset) begin
if(~reset) begin
data <= 'h0;
end
else if(~FRAME && IRDY) begin
addr_in <= AD_BUS;
cmd <= C_BE;
$display("ADDRESS IS %d, COMMAND is %d, DEVSEL is ", addr_in, cmd, DEVSEL
);
end
else begin
data
<= AD_BUS;
byte_en <= C_BE;
$display("DATA IS %d, BE is %d", data, byte_en);
end
end
always @(*) begin
for(bus_num = 0; bus_num <= 8'hFF; bus_num = bus_num+1) begin
for(dev_num = 0; dev_num <= 5'h1F; dev_num = dev_num+1 ) begin
for(func_num = 0; func_num <= 3'd7; func_num = func_num+1) begin
if(~cmd[0]) begin
$display("ADDRESS OUT IS %d, ", addr_out);
pci_read(addr_out, data);
end
else begin
$display("ADDRESS OUT IS %d, ", addr_out);
pci_write(addr_out, data, byte_en);
end
end
end
end
end

// Decoder Logic to generate IDSEL Using Device No.

always @(AD_BUS or config_type) begin
if (config_type) begin
//type 1 cycle - address goes through unchanged
IDSEL_31_11 = addr_in[31:11] ;
$display("ADDR_IN is %0b ", addr_in);
end
else begin
$display("ADDR_IN[15:11] is %0b ", addr_in[15:11]);
$display("ADDR_IN[31:0] is %0b ", addr_in);
case(addr_in[15:11])
5'h00:IDSEL_31_11 = 21'h00_0001 ;
5'h01:IDSEL_31_11 = 21'h00_0002 ;
5'h02:IDSEL_31_11 = 21'h00_0004 ;
5'h03:IDSEL_31_11 = 21'h00_0008 ;
5'h04:IDSEL_31_11 = 21'h00_0010 ;
5'h05:IDSEL_31_11 = 21'h00_0020 ;
5'h06:IDSEL_31_11 = 21'h00_0040 ;
5'h07:IDSEL_31_11 = 21'h00_0080 ;
5'h08:IDSEL_31_11 = 21'h00_0100 ;
5'h09:IDSEL_31_11 = 21'h00_0200 ;
5'h0A:IDSEL_31_11 = 21'h00_0400 ;
5'h0B:IDSEL_31_11 = 21'h00_0800 ;
5'h0C:IDSEL_31_11 = 21'h00_1000 ;
5'h0D:IDSEL_31_11 = 21'h00_2000 ;
5'h0E:IDSEL_31_11 = 21'h00_4000 ;
5'h0F:IDSEL_31_11 = 21'h00_8000 ;
5'h10:IDSEL_31_11 = 21'h01_0000 ;
5'h11:IDSEL_31_11 = 21'h02_0000 ;
5'h12:IDSEL_31_11 = 21'h04_0000 ;
5'h13:IDSEL_31_11 = 21'h08_0000 ;
5'h14:IDSEL_31_11 = 21'h10_0000 ;
default: IDSEL_31_11 = 21'h00_0000 ;
endcase
$display("IDSEL GENERATED is %0b ",IDSEL_31_11);
end
end
task pci_read(input [31:0] addr, output [31:0] data);
begin
data = 32'hFFFF_FFFF;
$display("This is the PCI READ task, Data is %b", data);
end
endtask
task pci_write(input [31:0] addr,data, input [3:0] C_BE);
$display("This is the PCI WRITE task");
endtask
endmodule