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探索嵌入式 ARM 平台與 SoC Part I – ARM 架構瀏覽 . SoC 平台 . 關鍵概念 Jim

探索嵌入式 ARM 平台與 SoC

Part I – ARM 架構瀏覽 .SoC 平台 . 關鍵概念

Jim Huang (jserv) from 0xlab

July 18, 2009

0xlab – connect your device to application – http://0xlab.org/

Jim Huang ( jserv ) from 0xlab July 18, 2009 0xlab – connect your device to

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Rights to copy © Copyright 2009 0xlab .org contact@0xlab.org Corrections, suggestions, contributions and translations
Rights to copy © Copyright 2009 0xlab .org contact@0xlab.org Corrections, suggestions, contributions and translations

Rights to copy

© Copyright 2009 0xlab.org

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Corrections, suggestions, contributions and translations are welcome!

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切入點 從軟體開發者的角度檢視 ARM 架構 善用開放原始碼軟體 GNU Toolchain – CodeSourcery 2009q1

切入點

從軟體開發者的角度檢視 ARM 架構

善用開放原始碼軟體

GNU Toolchain – CodeSourcery 2009q1ARM 架構 善用開放原始碼軟體 QEMU 0.10.5 CuRT v1 ( 土製 ARM 即時作業系統 )

QEMU 0.10.5GNU Toolchain – CodeSourcery 2009q1 CuRT v1 ( 土製 ARM 即時作業系統 ) 參考 ARM

CuRT v1 ( 土製 ARM 即時作業系統 ) ( 土製 ARM 即時作業系統 )

QEMU 0.10.5 CuRT v1 ( 土製 ARM 即時作業系統 ) 參考 ARM SoC 平台: Marvell/Intel PXA255

參考 ARM SoC 平台: Marvell/Intel PXA255

作中學:觀察、系統模擬、驗證,動手

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Agenda ARM 架構快速瀏覽 ARM SoC 平台 關鍵概念: 工作模式、暫存器組、系統狀態、指令集、

Agenda

ARM 架構快速瀏覽 架構快速瀏覽

ARM SoC 平台 平台

關鍵概念:Agenda ARM 架構快速瀏覽 ARM SoC 平台 工作模式、暫存器組、系統狀態、指令集、 例外處理

工作模式、暫存器組、系統狀態、指令集、

例外處理

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ARM 架構快速瀏覽 ARM 歷史背景 ARM 的「家族」 ARM SoC 平台 關鍵概念:

ARM 架構快速瀏覽 架構快速瀏覽

ARM 歷史背景 歷史背景

ARM 的「家族」 的「家族」

ARM SoC 平台 平台

關鍵概念:ARM 歷史背景 ARM 的「家族」 ARM SoC 平台

工作模式、暫存器組、系統狀態、指令集、例外處理

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Part I 涵蓋範圍 0xlab – connect your device to application – http://0xlab.org/ 6
Part I 涵蓋範圍 0xlab – connect your device to application – http://0xlab.org/ 6

Part I 涵蓋範圍

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無所不在的 ARM Most of the above devides are powered by ARM. 0xlab – connect your

無所不在的 ARM

無所不在的 ARM Most of the above devides are powered by ARM. 0xlab – connect your device

Most of the above devides are powered by ARM.

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Darwin's Concept 適者生存 0xlab – connect your device to application – http://0xlab.org/ 8

Darwin's Concept

適者生存
適者生存

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在 ARM 之前 BBC Micro (BBC Microcomputer System) 在 BBC (Britsh Broadcasting Corporation) 主導的 BBC

ARM 之前

BBC Micro (BBC Microcomputer System) 在 BBC (Britsh Broadcasting Corporation) 主導的 BBC Computer Literacy Project BBC (Britsh Broadcasting Corporation) 主導的 BBC Computer Literacy Project 中,設計一系列的電腦與週邊裝置。於 1980 年代已有 顯著的技術突破

The Computer Programme 》 , 1982 The Computer Programme , 1982

programming, graphics, sound and music, Teletext, controlling external hardware and artificial intelligence《 The Computer Programme 》 , 1982 ( 對 BBC Micro 的 ) 電腦供應商 Acorn Computers

controlling external hardware and artificial intelligence ( 對 BBC Micro 的 ) 電腦供應商 Acorn Computers

( 對 BBC Micro 的 ) 電腦供應商 Acorn Computers 升級其 Atom microcomputer 設計,是為 Proton , BBC Micro 的 ) 電腦供應商 Acorn Computers 升級其 Atom microcomputer 設計,是為 Proton 提供更佳的圖形處 理與更快的 2 MHz MOS Technology 6502 CPU

1982 年,競爭對手 Sinclair 推出 ZX Spectrum ,嚴重威脅 Acrom 獲利 年,競爭對手 Sinclair 推出 ZX Spectrum ,嚴重威脅 Acrom 獲利

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ARM 就此展開 1983­1985 年間, Acorn Computers 推出第一款 ARM chip ,即 Acorn RISC Machine

ARM 就此展開

ARM 就此展開 1983­1985 年間, Acorn Computers 推出第一款 ARM chip ,即 Acorn RISC Machine

1983­1985 年間, Acorn Computers 推出第一款 ARM chip ,即 Acorn RISC Machine 。爾後該設計團隊於 1990 年間, Acorn Computers 推出第一款 ARM chip ,即 Acorn RISC Machine 。爾後該設計團隊於 1990 年代分後,公司 命名為 Advanced RISC Machine” (ARM)

成功取代 6502 processor 市場 6502 processor 市場

ARM1 –RISC Machine” (ARM) 成功取代 6502 processor 市場 ARM2 – 量產 (1986) 32­bit data bus, 26­bit address

ARM2 – 量產 (1986) 32­bit data bus, 26­bit address space (top 6 bits used as status flag) 量產 (1986) 32­bit data bus, 26­bit address space (top 6 bits used as status flag) 16 32­bit registers (1 PC), 30,000 transistors No microcode, cache, Low power

國家半導體 NS 32016 的出現,威脅 Acorn 的獲利模式,隨後引發 財務危機, 1985 年,義大利設備商 Olivetti NS 32016 的出現,威脅 Acorn 的獲利模式,隨後引發 財務危機, 1985 年,義大利設備商 Olivetti Ing et Cie 入主

ARM3 – 引入 4KB Cache, 25MHz (1989­1990) 引入 4KB Cache, 25MHz (1989­1990)

VLSI Technology, Inc. 製造晶圓生產 (1985)

由 VLSI Technology, Inc. 製造晶圓生產 (1985) 0xlab – connect your device to application –
由 VLSI Technology, Inc. 製造晶圓生產 (1985) 0xlab – connect your device to application –
由 VLSI Technology, Inc. 製造晶圓生產 (1985) 0xlab – connect your device to application –

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ARM Ltd. 出現 1990 年代, Acorn 的財務狀況趨於穩定,亟欲轉型。 1991 年,於英國劍橋,由

ARM Ltd. 出現

1990 年代, Acorn 的財務狀況趨於穩定,亟欲轉型。 1991

年,於英國劍橋,由 Apple, Acorn, VLSI 三家公司共同成立 ARM Ltd.

ARM Ltd. 成立後,將 ARM3 的下一代命名為 ARM6 ,實體裝 置為 ARM600

的下一代命名為 ARM6 ,實體裝 置為 ARM600 稍候的 ARM610 用於 Apple Newton PDA (­1998) 1992

稍候的 ARM610 用於 Apple Newton PDA(­1998)

ARM600 稍候的 ARM610 用於 Apple Newton PDA (­1998) 1992 年底, 3DO 公司 ( 主要產品:遊戲機 ) 自

1992

年底, 3DO 公司 ( 主要產品:遊戲機 ) 自 ARM Ltd. 取得

ARM 授權並成功量產電子設備,自此, ARM 在出售晶片設計 技術授權,獲得成功

目前採用 ARM 技術知識產權 (IP) 核心的微處理器,即我們常 所說的 ARM 微處理器

ARM 遍及工業控制、消費性電子產品、通信網路系統等領域

ARM7TDMI 是早期成功的 ARM core ,出貨量達數億單位

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ARM 的時代 DEC 自 ARM Ltd. 取得 ARM6 的授權,依據此基礎研發出 時 脈可 達 233MHz 的

ARM 的時代

DEC 自 ARM Ltd. 取得 ARM6 的授權,依據此基礎研發出 時 脈可 達 233MHz 的 StrongARM (SA­1x 系列 ) ARM Ltd. 取得 ARM6 的授權,依據此基礎研發出 時脈可233MHz StrongARM (SA­1x 系列 )

使用於 PDA 裝置, 如 HP iPAQ 用於 PDA 裝置,HP iPAQ

500 mWatt of power @160MHz @.35 m m

DEC 後 來 為 了 與 Inte l 控 訴和解 ,將技術 移 轉 到 Intel (1997) Intel 訴和解,將技術Intel (1997)

Intel 依據 StrongARM 的基礎,發展出 Xscale 依據 StrongARM 的基礎,發展出 Xscale

StrongARM 關鍵的成 員 出 走 Intel 後,成立 P.A. Semi (Palo Alto Semiconducto) (2003) ,爾後 被 Apple 關鍵的成Intel 後,成立 P.A. Semi (Palo Alto Semiconducto)(2003) ,爾後Apple 併購 (2008)

Intel 出售 XScale 產品 線予 Marvell (2006) 出售 XScale 產品線予 Marvell (2006)

(2008) Intel 出售 XScale 產品 線予 Marvell (2006) 0xlab – connect your device to application –

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ARM 的「家族」 Architecture Versions ARM V3, V4, V5, V6, V7 使 用 “ architecture” 一

ARM 的「家族」

Architecture VersionsARM 的「家族」 ARM V3, V4, V5, V6, V7 使 用 “ architecture” 一 詞標注硬 體設計架構 更

ARM V3, V4, V5, V6, V7ARM 的「家族」 Architecture Versions 使 用 “ architecture” 一 詞標注硬 體設計架構 更 具 體 來

使用 “ architecture” 一 詞標注硬 體設計架構 architecture” 詞標注硬體設計架構

用 “ architecture” 一 詞標注硬 體設計架構 更 具 體 來 說,指的是 ISA (Instruction Set

說,指的是 ISA (Instruction Set Architecture)

Implementations ( 涉 及不同的製 程 ) ( 及不同的製)

ARM6 (1991) , ARM7 (1995) , ARM9 (1997) (1991), ARM7 (1995), ARM9 (1997)

ARM10 (1999) , ARM11 (2003) (1999), ARM11 (2003)

使用 “ cores” 一 詞標注 其 世 代 演進 cores” 詞標注演進

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Application Note – Core Type & Revision Identification, ARM 0x41 A ( ARM Ltd )

Application Note – Core Type & Revision Identification, ARM

0x41 A (ARM Ltd)

0x44 D (DEC) 0x69 I (Intel Corporation)

0x41 A ( ARM Ltd ) 0x44 D (DEC) 0x69 I (Intel Corporation) / / #

/ / # # cat cat /proc/cpuinfo /proc/cpuinfo

Architecture

version

Processor Processor

BogoMIPS BogoMIPS

Features Features

CPU CPU implementer implementer : : 0x41 0x41 CPU CPU architecture: architecture: 7 7

CPU CPU variant variant

CPU CPU part part

CPU CPU revision revision

: : ARMv7 ARMv7 Processor Processor rev rev 3 3 (v7l) (v7l) : : 471.61 471.61

: : swp swp half half thumb thumb fastmult fastmult vfp vfp edsp edsp thumbee thumbee neon neon

: : 0x1 0x1 : : 0xc08 0xc08 3 3

: :

ARM ISA feature

Hardware Hardware Revision Revision Serial Serial

: : OMAP3 OMAP3 Beagle Beagle Board Board : : 0020 0020 : : 0000000000000000 0000000000000000

Serial : : OMAP3 OMAP3 Beagle Beagle Board Board : : 0020 0020 : : 0000000000000000
: : 0020 0020 : : 0000000000000000 0000000000000000 採用 ARM 技術知識產權 (IP)
採用 ARM 技術知識產權 (IP) 核心的微處理器,即我們 常所說的 ARM
採用 ARM 技術知識產權 (IP) 核心的微處理器,即我們
常所說的 ARM 微處理器,實際的組態變化相當多元

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ARMv1 Implementation: 僅 在原型機 ARM1 出現 指令集: 基 本 的 資料 處理指令 (ALU) ,不

ARMv1

Implementation: 僅 在原型機 ARM1 出現 在原型機 ARM1 出現

指令集:ARMv1 Implementation: 僅 在原型機 ARM1 出現 基 本 的 資料 處理指令 (ALU) ,不 包含乘法 指令

本 的 資料 處理指令 (ALU) ,不 包含乘法 指令 資料處理指令 (ALU) ,不包含乘法指令

Byte, half­word, word 的 Load/Store 指令 Load/Store 指令

跳躍 (jump/branch) 指令, 包括 procedure call (jump/branch) 指令,包括 procedure call

軟體中斷 (SWI) 指令 (SWI) 指令

址空 間: 64MB 址空間: 64MB

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ARMv2 Implementation: ARM2 與 ARM3 (ARMv2a) 等 硬 體 指令集: 增加乘法和乘加 指令 支援輔助運算

ARMv2

Implementation: ARM2 與 ARM3 (ARMv2a) 等 硬 體 ARM3 (ARMv2a)

指令集:ARMv2 Implementation: ARM2 與 ARM3 (ARMv2a) 等 硬 體 增加乘法和乘加 指令 支援輔助運算 器 操

增加乘法和乘加指令 支援輔助運算作指令

快速中斷 模式 (FIQ) 模式 (FIQ)

SWP/SWPB 的 最 基 本記憶 體與暫存器 交換 指令 本記憶體與暫存器交換指令

址空 間: 64MB (32­bit data bus, 26­bit address space (top 6 bits used as status 址空間: 64MB (32­bit data bus, 26­bit address space (top 6 bits used as status flag)

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ARMv2 :: SWP 在 ARM 暫存器組 交換 一 個 word Two cycles 並 確保 single

ARMv2 :: SWP

ARM 暫存器組 交換 一 個 word ARM 暫存器組交換word

Two cyclesARMv2 :: SWP 在 ARM 暫存器組 交換 一 個 word 並 確保 single atomic action Support

確保

single atomic actionARM 暫存器組 交換 一 個 word Two cycles 並 確保 Support for RT semaphores 0xlab –

Support for RT semaphores一 個 word Two cycles 並 確保 single atomic action 0xlab – connect your device to

0xlab – connect your device to application – http://0xlab.org/

for RT semaphores 0xlab – connect your device to application – http://0xlab.org/ R0 R1 R2 R7

R0

R1

R2

R7

R8

R15

for RT semaphores 0xlab – connect your device to application – http://0xlab.org/ R0 R1 R2 R7

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ARMv3 較 大的 改 動,將定 址空 間 增至 32­bit (4GB) 。 追加 CPSR 和 SPSR

ARMv3

大的動,將定址空增至 32­bit (4GB) 追加 CPSR SPSR 常處理。增加 止和未定義等兩種處理器模式

Implementation: ARM6增加 中 止和未 定義等 兩種 處理器模式 裝置範例: Apple Newton PDA 指令集: 增加

裝置範例: Apple Newton PDA Apple Newton PDA

指令集:Implementation: ARM6 裝置範例: Apple Newton PDA 增加 MRS/MSR 指令,存取 新增 的 R0 R1 R2

ARM6 裝置範例: Apple Newton PDA 指令集: 增加 MRS/MSR 指令,存取 新增 的 R0 R1 R2

增加 MRS/MSR 指令,存取新增

R0

R1

R2

R14

R15

LDM

R0 R1 R2 R14 R15 LDM STM M i M M i+1 i+2 M i+14 M
R0 R1 R2 R14 R15 LDM STM M i M M i+1 i+2 M i+14 M

STM

M i

M i

M

M

i+1

i+2

M

i+14

M

i+15

CPSR/SPSR 暫存器

增加常處理返回的指令功

暫存器 增加 從 異 常處理 返回 的指令功 能 CPSR SPSR MRS MSR 0xlab – connect your

CPSR

SPSR

MRS

從 異 常處理 返回 的指令功 能 CPSR SPSR MRS MSR 0xlab – connect your device to

MSR

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R0

R1

R7

R8

R14

R15

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ARMv3 :: Memory Addressing Byte : 8 bits Halfword : 16 bits must be aligned

ARMv3 :: Memory Addressing

Byte : 8 bitsARMv3 :: Memory Addressing Halfword : 16 bits must be aligned to 2­byte boundaries Word :

Halfword : 16 bitsARMv3 :: Memory Addressing Byte : 8 bits must be aligned to 2­byte boundaries Word :

ARMv3 :: Memory Addressing Byte : 8 bits Halfword : 16 bits must be aligned to

must be aligned to 2­byte boundaries

Word : 32 bitsHalfword : 16 bits must be aligned to 2­byte boundaries bit 31 bit 0 23  

16 bits must be aligned to 2­byte boundaries Word : 32 bits bit 31 bit 0

bit 31

bit 0

be aligned to 2­byte boundaries Word : 32 bits bit 31 bit 0 23   22

23

 

22

21

20

19

 

18

17

16

 

word16

  word16
 

15

 

14

13

12

half-word14 half-word12

11

 

10

9

8

 

word8

  word8
 

7

 

6

5

4

byte6

half-word4

3

 

2

1

0

byte3 byte2 byte1

byte0

must be aligned to 4­byte boundaries3   2 1 0 byte3 byte2 byte1 byte0 ARM address can be 32 bits long.

ARM address can be 32 bits long.byte2 byte1 byte0 must be aligned to 4­byte boundaries Address refers to byte. Address 4 starts

Address refers to byte.to 4­byte boundaries ARM address can be 32 bits long. Address 4 starts at byte 4.

ARM address can be 32 bits long. Address refers to byte. Address 4 starts at byte

Address 4 starts at byte 4.

在系統 啟 動時, 調整 為 little­ or big­endian mode 在系統動時,調整little­ or big­endian mode

bit 31

byte 3

little­endian

little­endian

byte 2

byte 1

bit 0

byte 0

little­endian byte 2 byte 1 bit 0 byte 0 bit 0 big­endian bit 31 byte address

bit 0

big­endian

bit 31

byte

address

byte 0

byte 1

byte 2

byte 3

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ARMv4 廣泛 應用的 ARM 架構,對 ARMv3 作 進 一 步擴充 ,引入引 進了 16­bit Thumb 指令集

ARMv4

廣泛應用的 ARM 架構,對 ARMv3 作 進 一 步擴充 ,引入引 進了 16­bit Thumb 指令集 ( 可選擇 應用的 ARM 架構,對 ARMv3 步擴充,引入引 進了 16­bit Thumb 指令集 ( 可選擇 )

Implementation: ARM7, ARM9, StrongARM進了 16­bit Thumb 指令集 ( 可選擇 ) 裝置範例: GameBoy Advance, Nintendo DS, iPod, LEGO

裝置範例: GameBoy Advance, Nintendo DS, iPod, LEGO NXT, Openmoko GTA01/GTA02 GameBoy Advance, Nintendo DS, iPod, LEGO NXT, Openmoko GTA01/GTA02

指令集:Advance, Nintendo DS, iPod, LEGO NXT, Openmoko GTA01/GTA02 增加 16­bit Thumb 指令集 加強 軟體中 斷 (SWI)

增加 16­bit Thumb 指令集 16­bit Thumb 指令集

加強軟體中 斷 (SWI) 指令的功 能 軟體中(SWI) 指令的功

處理器系統模式引進特(SVC) 時,user 暫存 器作 將未使用的指令間,捕捉定義指令

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ARMv4 :: ARM/Thumb 32­bit ARM Instruction Sets 16­bit Thumb Instruction Set 更 高 的指令集 密

ARMv4 :: ARM/Thumb

32­bit ARM Instruction SetsARMv4 :: ARM/Thumb 16­bit Thumb Instruction Set 更 高 的指令集 密 度 對 cache 處理更有 效率

16­bit Thumb Instruction SetARMv4 :: ARM/Thumb 32­bit ARM Instruction Sets 更 高 的指令集 密 度 對 cache 處理更有 效率

高 的指令集 密 度 的指令集

cache 處理更有 效率 cache 處理更有效率

All instructions are executed as ARM更 高 的指令集 密 度 對 cache 處理更有 效率 Decompressor converts Thumb to equivalent ARM instruction

Decompressor converts Thumb to equivalent ARM instruction處理更有 效率 All instructions are executed as ARM Decompressor present in the decode stage of the

Decompressor present in the decode stage of the pipeline. .

Decompressor present in the decode stage of the pipeline . 22 0xlab – connect your device

22

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ARMv5 Implementation: ARM10, Xscale 裝置範例: HTC Dream (Google G1 Phone) 指令集: BLX 指令 (Improved ARM

ARMv5

Implementation: ARM10, XscaleARMv5 裝置範例: HTC Dream (Google G1 Phone) 指令集: BLX 指令 (Improved ARM and Thumb interworking) CLZ

裝置範例: HTC Dream (Google G1 Phone) HTC Dream (Google G1 Phone)

指令集:ARM10, Xscale 裝置範例: HTC Dream (Google G1 Phone) BLX 指令 (Improved ARM and Thumb interworking) CLZ

BLX 指令 (Improved ARM and Thumb interworking) 指令 (Improved ARM and Thumb interworking)

CLZ 指令 (count leading­zeroes) 指令 (count leading­zeroes)

BRK 中 斷 指令 指令

增加 DSP 強化 指令 (v5TE) DSP 強化指令 (v5TE)

E – enhanced DSP instructions including saturated arithmetic operations and 16­bit multiply operations – enhanced DSP instructions including saturated arithmetic operations and 16­bit multiply operations

增加 Jazelle 指令集 Jazelle 指令集

J – support for new Java state, offering hardware and optimized software acceleration of bytecode execution. – support for new Java state, offering hardware and optimized software acceleration of bytecode execution.

co­processor 增加 更 多可選擇 的指令 co­processor 增加多可選擇的指令

0xlab – connect your device to application – http://0xlab.org/

23

ARMv5 :: DSP Extension (E) 0xlab – connect your device to application – http://0xlab.org/ 24

ARMv5 :: DSP Extension (E)

ARMv5 :: DSP Extension (E) 0xlab – connect your device to application – http://0xlab.org/ 24

0xlab – connect your device to application – http://0xlab.org/

24

ARMv5 :: co­processor Marvell/Intel Xscale Wireless MMX co­processor 概念:將 x86 行 之有年的 MMX/SSE

ARMv5 :: co­processor

Marvell/Intel Xscale Wireless MMX co­processorARMv5 :: co­processor 概念:將 x86 行 之有年的 MMX/SSE 指令集設計概念,應用於 Xscale 處理

概念:將 x86 行 之有年的 MMX/SSE 指令集設計概念,應用於 Xscale 處理 器, 以 co­processor 的形式存在 x86 之有年的 MMX/SSE 指令集設計概念,應用於 Xscale 處理 器,co­processor 的形式存在

ARM 的架構 最多可支援 16 個 co­processor , 以 Xscale 為例: 的架構最多可支援 16 co­processor Xscale 為例:

co­processor 016 個 co­processor , 以 Xscale 為例: co­processor 1 Xscale co­processor instructions

co­processor 1co­processor , 以 Xscale 為例: co­processor 0 Xscale co­processor instructions Coprocessor data transfers

Xscale co­processor instructions, 以 Xscale 為例: co­processor 0 co­processor 1 Coprocessor data transfers Coprocessor data operations

Coprocessor data transfers0 co­processor 1 Xscale co­processor instructions Coprocessor data operations Coprocessor register load and

Coprocessor data operationsXscale co­processor instructions Coprocessor data transfers Coprocessor register load and store 0xlab – connect your

Coprocessor register load and storeCoprocessor data transfers Coprocessor data operations 0xlab – connect your device to application –

0xlab – connect your device to application – http://0xlab.org/

ARM

Core

register load and store 0xlab – connect your device to application – http://0xlab.org/ ARM Core Co-processor
register load and store 0xlab – connect your device to application – http://0xlab.org/ ARM Core Co-processor
register load and store 0xlab – connect your device to application – http://0xlab.org/ ARM Core Co-processor

Co-processor

25

ARMv6 Implementation: ARM11 裝置範例: Apple iPhone (1st/2nd) 指令集 / 特 性: 引入 60 個以上新 的

ARMv6

Implementation: ARM11ARMv6 裝置範例: Apple iPhone (1st/2nd) 指令集 / 特 性: 引入 60 個以上新 的 SIMD(Single

裝置範例: Apple iPhone (1st/2nd) Apple iPhone (1st/2nd)

指令集 / 特 性: / 特性:

引入 60 個以上新 的 SIMD(Single Instruction Multiple Data) , 使多媒 體處理速度快 1.75 倍 60 個以上新SIMD(Single Instruction Multiple Data) 使多媒體處理速度快 1.75

提出新 的 atomic operations(LDREX/STREX) atomic operations(LDREX/STREX)

改進記憶理,使系統性30%

強化 Mixed­Endian 支援 (Little­Endian OS + Bit­Endian Data for TCP/IP) Mixed­Endian 支援 (Little­Endian OS + Bit­Endian Data for TCP/IP)

改進 Unaligned Data 支援 ( 使 DSP 應用 受益 ) Unaligned Data 支援 ( 使 DSP 應用受益 )

0xlab – connect your device to application – http://0xlab.org/

26

ARMv6 :: SIMD Extensions 0xlab – connect your device to application – http://0xlab.org/ 27

ARMv6 :: SIMD Extensions

ARMv6 :: SIMD Extensions 0xlab – connect your device to application – http://0xlab.org/ 27

0xlab – connect your device to application – http://0xlab.org/

27

ARMv6 :: Endianness Support (E bit) 0xlab – connect your device to application – http://0xlab.org/

ARMv6 :: Endianness Support (E bit)

ARMv6 :: Endianness Support (E bit) 0xlab – connect your device to application – http://0xlab.org/ 28

0xlab – connect your device to application – http://0xlab.org/

28

ARMv6 :: Byte Reverse instruction 0xlab – connect your device to application – http://0xlab.org/ 29

ARMv6 :: Byte Reverse instruction

ARMv6 :: Byte Reverse instruction 0xlab – connect your device to application – http://0xlab.org/ 29

0xlab – connect your device to application – http://0xlab.org/

29

ARMv7 Implementation: Cortex­A8 第一 個 ARMv7 ISA 的 完整 implementation , 包含 Advanced SIMD Media

ARMv7

ARMv7 Implementation: Cortex­A8 第一 個 ARMv7 ISA 的 完整 implementation , 包含 Advanced SIMD Media

Implementation: Cortex­A8ARMv7 第一 個 ARMv7 ISA 的 完整 implementation , 包含 Advanced SIMD Media Extension (NEON) 自

ARMv7 Implementation: Cortex­A8 第一 個 ARMv7 ISA 的 完整 implementation , 包含 Advanced SIMD Media

第一ARMv7 ISA 完整 implementation 包含 Advanced SIMD Media Extension (NEON)

, 包含 Advanced SIMD Media Extension (NEON) 自 ARMv7 起 , core 命名 改以 Cortex 開

ARMv7 起 , core 命名 改以 Cortex 開 頭 ARMv7 core 命名改以 Cortex

In­order, dual­issue superscalar core自 ARMv7 起 , core 命名 改以 Cortex 開 頭 13­stage integer pipeline 10­stage NEON media

13­stage integer pipelineCortex 開 頭 In­order, dual­issue superscalar core 10­stage NEON media pipeline Dedicated L2 with 9­cycle

10­stage NEON media pipelinedual­issue superscalar core 13­stage integer pipeline Dedicated L2 with 9­cycle latency Branch predictor based on

Dedicated L2 with 9­cycle latency13­stage integer pipeline 10­stage NEON media pipeline Branch predictor based on global history NEON: 64/128­bit

Branch predictor based on global historyNEON media pipeline Dedicated L2 with 9­cycle latency NEON: 64/128­bit SIMD, 2x­4x ≠ over prior ARMv6

NEON: 64/128­bit SIMD, 2x­4x ≠ over prior ARMv6 SIMD over prior ARMv6 SIMD

ARMv7 關鍵 特 性 關鍵

引入 Thumb­2, Thumb­EE (for dynamic/JIT compiler)

引入 Thumb­2, Thumb­EE (for dynamic/JIT compiler)

時 脈可 達 1 GHz

脈可1 GHz

功 耗小 於 300mW

耗小300mW

< 4mm 2 at 65nm ( 不 含 NEON, L2 cache, ETM)

<

4mm 2 at 65nm ( NEON, L2 cache, ETM)

30

ARMv7 :: NEON 64/128­bit 混合 式 SIMD 架構 D0 Two aliased register files D1 D2

ARMv7 :: NEON

ARMv7 :: NEON 64/128­bit 混合 式 SIMD 架構 D0 Two aliased register files D1 D2 x

64/128­bit 混合 式 SIMD 架構 混合SIMD 架構

D0

Two aliased register filesD1

D1

D2

x 64­bit (D0­D31)32

32

D3

x 128­bit (Q0­Q15)16

16

x 128­bit (Q0­Q15) 16

Shared with VFPfiles D1 D2 x 64­bit (D0­D31) 32 D3 x 128­bit (Q0­Q15) 16   Integer and SP

 

Integer and SP FP processingD30

D30

D31

Q0 Q1 Q15
Q0
Q1
Q15

8, 16, 32, 64­bit integersInteger and SP FP processing D30 D31 Q0 Q1 Q15 Encoded in ARM and Thumb­2 Alias,

Encoded in ARM and Thumb­2D30 D31 Q0 Q1 Q15 8, 16, 32, 64­bit integers Alias, same physical structure D1.U8 64­bit

Q15 8, 16, 32, 64­bit integers Encoded in ARM and Thumb­2 Alias, same physical structure D1.U8

Alias, same physical structure

D1.U8

64­bit D0.U8 Q0.F32 128­bit
64­bit
D0.U8
Q0.F32
128­bit

Source: Grisenthwaite of ARM

0xlab – connect your device to application – http://0xlab.org/

31

vadd.I16 D0, D1, D2 D1 D2 + + + + vmul.I32.S16 Q0, D2, D3 D2
vadd.I16 D0, D1, D2 D1 D2 + + + +
vadd.I16 D0, D1, D2
D1
D2
+
+ +
+

vmul.I32.S16 Q0, D2, D3

D0, D1, D2 D1 D2 + + + + vmul.I32.S16 Q0, D2, D3 D2 D3 *

D2

D3 * * * *
D3
*
*
*
*
D1 D2 + + + + vmul.I32.S16 Q0, D2, D3 D2 D3 * * * *
64b
64b

Source: Grisenthwaite of ARM

D0

D0 128b vshr.I16.I32 D0, Q1, #5 128b Q1
D0 128b vshr.I16.I32 D0, Q1, #5 128b Q1
D0 128b vshr.I16.I32 D0, Q1, #5 128b Q1
D0 128b vshr.I16.I32 D0, Q1, #5 128b Q1
D0 128b vshr.I16.I32 D0, Q1, #5 128b Q1

128b

D0 128b vshr.I16.I32 D0, Q1, #5 128b Q1

vshr.I16.I32 D0, Q1, #5

D0 128b vshr.I16.I32 D0, Q1, #5 128b Q1

128b

D0 128b vshr.I16.I32 D0, Q1, #5 128b Q1
D0 128b vshr.I16.I32 D0, Q1, #5 128b Q1
D0 128b vshr.I16.I32 D0, Q1, #5 128b Q1
D0 128b vshr.I16.I32 D0, Q1, #5 128b Q1
D0 128b vshr.I16.I32 D0, Q1, #5 128b Q1

Q1

>> >>
>> >>
>> >> >> >> D0 #5

>> >>

>> >> >> >> D0 #5
>> >> >> >> D0 #5

D0

>> >> >> >> D0 #5

#5

0xlab – connect your device to application – http://0xlab.org/

Q0

32

NEON Load or store 1­element or 2, 3, 4­elelment structure Handle complex number, coordinates, etc.

NEON Load or store 1­element or 2, 3, 4­elelment structure Handle complex number, coordinates, etc.
Handle complex number, coordinates, etc.NEON Load or store 1­element or 2, 3, 4­elelment structure

Easy AoS to SoAstructure Handle complex number, coordinates, etc. X0 vld3.16 {D0, D1, D2}, [R0]! Y0 Z0 X1 Y1

X0

vld3.16 {D0, D1, D2}, [R0]!

etc. Easy AoS to SoA X0 vld3.16 {D0, D1, D2}, [R0]! Y0 Z0 X1 Y1 Z1

Y0

Z0

X1

Y1

Y0 Z0 X1 Y1 Z1 vst3.16 {D0, D1, D2}, [R0]! • No data swizzling needed! •

Z1

vst3.16 {D0, D1, D2}, [R0]!

Z1 vst3.16 {D0, D1, D2}, [R0]! • No data swizzling needed! • Fewer instruction, higher performance

No data swizzling needed!

Fewer instruction, higher performance

0xlab – connect your device to application – http://0xlab.org/

needed! • Fewer instruction, higher performance 0xlab – connect your device to application – http://0xlab.org/
needed! • Fewer instruction, higher performance 0xlab – connect your device to application – http://0xlab.org/

Y3

Y2

Y1

Y0

Z3

Z2

Z1

Z0

X3

X2

X1

X0

D0

D1

D2

33

ARMv7 :: Thumb­2 大 幅改進 Thumb 指令集的 缺失 引入 混合 16­/32­bit 指令集的並存模式 Most of

ARMv7 :: Thumb­2

幅改進 Thumb 指令集的 缺失 幅改進 Thumb 指令集的缺失

引入混合 16­/32­bit 指令集的並存模式 混合 16­/32­bit 指令集的並存模式

Most of Thumb­2 are unconditional, similar to ARM New conditional execution instruction (If­Then) is introduced (a.k.a. Guarded Execution ) Guarded Execution)

(If­Then) is introduced (a.k.a. Guarded Execution ) Enables 1 to 4 following instructions to be conditional

Enables 1 to 4 following instructions to be conditional(If­Then) is introduced (a.k.a. Guarded Execution ) 不 再需 要 繁瑣 的狀態轉 換 兼顧效能 與 程

再需 要 繁瑣 的狀態轉 換 兼顧效能 與 程 式碼 密 度 再需繁瑣的狀態轉換 兼顧效能式碼

繁瑣 的狀態轉 換 兼顧效能 與 程 式碼 密 度 0xlab – connect your device to application

0xlab – connect your device to application – http://0xlab.org/

換 兼顧效能 與 程 式碼 密 度 0xlab – connect your device to application – http://0xlab.org/

34

34

ARM core performance roadmap Release ARM Cortex “Intelligent Computing” Adv Development 2500 2000 Cortex­A8
ARM core performance roadmap
Release
ARM Cortex
“Intelligent Computing”
Adv Development
2500
2000
Cortex­A8 "Tiger"
1500
1000
x4
750
ARM1176JZF­S ™
ARM11 MPCore
ARM1136EJ­S ™
500
ARM1026EJ­S ™
250
ARM926EJ­S ™
Pre­2005
2005
2006
DMIPS

Source: Williamson of ARM at Fall processor Forum 05

0xlab – connect your device to application – http://0xlab.org/

35

Cortex­A8 NEON Performance • Cortex-A8 NEON performance vs. ARMv5 and ARMv6 implementations MPEG­4 GSM­AMR MP3

Cortex­A8 NEON Performance

Cortex-A8 NEON performance vs. ARMv5 and ARMv6 implementations

MPEG­4

GSM­AMR MP3 Decoder

1x 2x 3x 4x
1x
2x
3x
4x
implementations MPEG­4 GSM­AMR MP3 Decoder 1x 2x 3x 4x ARM926EJ­S ARMv5TE ARM1136J­S ARMv6 Cortex­A8 NEON •
implementations MPEG­4 GSM­AMR MP3 Decoder 1x 2x 3x 4x ARM926EJ­S ARMv5TE ARM1136J­S ARMv6 Cortex­A8 NEON •

ARM926EJ­S

ARMv5TE

GSM­AMR MP3 Decoder 1x 2x 3x 4x ARM926EJ­S ARMv5TE ARM1136J­S ARMv6 Cortex­A8 NEON • CPU bandwidth

ARM1136J­S

ARMv6

Decoder 1x 2x 3x 4x ARM926EJ­S ARMv5TE ARM1136J­S ARMv6 Cortex­A8 NEON • CPU bandwidth required for

Cortex­A8

NEON

3x 4x ARM926EJ­S ARMv5TE ARM1136J­S ARMv6 Cortex­A8 NEON • CPU bandwidth required for various applications: –

CPU bandwidth required for various applications:

MPEG4 VGA decode 1

275 MHz

MP3 decode, 320kbps 48kHz, worst case 2

9.8 MHz

“Quake 2-like” application, CIF resolution 3

300 MHz

H.264 (estimated)

350 MHz

1) MPEG­4 Simple Profile @ 30fps 512kbps , 133MHz SDRAM 10­1­1­1 memory 2) MP3 Decoder @ 320kbps 48kHz (worst case means cold start on context switch), 133MHz SDRAM 10­1­1­1 memory 3) Quake2­like simulator, full software graphics pipeline, FP implementation 133MHz SDRAM 10­1­1­1 memory Source: ARM Developer conference

0xlab – connect your device to application – http://0xlab.org/

36

0xlab – connect your device to application – http://0xlab.org/ 37
0xlab – connect your device to application – http://0xlab.org/ 37

0xlab – connect your device to application – http://0xlab.org/

37

ARM 架構快速瀏覽 ARM SoC 平台 關鍵概念:

ARM 架構快速瀏覽 架構快速瀏覽

ARM SoC 平台 平台

關鍵概念:ARM 架構快速瀏覽 ARM SoC 平台 工作模式、暫存器組、系統狀態、指令集、例外處理 0xlab –

工作模式、暫存器組、系統狀態、指令集、例外處理

0xlab – connect your device to application – http://0xlab.org/

38

SoC (System­on­Chip) 整合多種 不同功 能 的 複雜 IC 組 合 , 針 對 特 定的市場

SoC (System­on­Chip)

SoC (System­on­Chip) 整合多種 不同功 能 的 複雜 IC 組 合 , 針 對 特 定的市場 或

整合多種不同功複雜 IC 定的市場應用需求 典型的組成

Programmable processor針 對 特 定的市場 或 應用 需求 典 型的組成 On­chip memory HW accelerating function units (DSP)

On­chip memory或 應用 需求 典 型的組成 Programmable processor HW accelerating function units (DSP) Peripheral interfaces

HW accelerating function units (DSP)典 型的組成 Programmable processor On­chip memory Peripheral interfaces (GPIO) Embedded software 39 0xlab –

Peripheral interfaces (GPIO)On­chip memory HW accelerating function units (DSP) Embedded software 39 0xlab – connect your device to

Embedded softwarefunction units (DSP) Peripheral interfaces (GPIO) 39 0xlab – connect your device to application –

units (DSP) Peripheral interfaces (GPIO) Embedded software 39 0xlab – connect your device to application –

39

0xlab – connect your device to application – http://0xlab.org/

SoC 實例 0xlab – connect your device to application – http://0xlab.org/ 40

SoC 實例

SoC 實例 0xlab – connect your device to application – http://0xlab.org/ 40

0xlab – connect your device to application – http://0xlab.org/

40

Display Driver IC: TFT, OLED Camera Chipset: CMOS - CCD Connectivity: WLAN, GPS, Bluetooth Processor:

Display Driver IC: TFT, OLED

Camera Chipset: CMOS - CCD

Connectivity: WLAN, GPS, Bluetooth

Processor: ARM

Modem: GSM/GPRS, WCDMA RF/Analog: Rx/Tx, Zero IF

SoCSoC

RAM: Mobile DRAM, SRAM, UtRAM

Smart Card: SIM

SIP / MCP Flash Memory:

Code/Data Storage

41

Card: SIM SIP / MCP Flash Memory: Code/Data Storage 41 0xlab – connect your device to
Card: SIM SIP / MCP Flash Memory: Code/Data Storage 41 0xlab – connect your device to
Card: SIM SIP / MCP Flash Memory: Code/Data Storage 41 0xlab – connect your device to
Card: SIM SIP / MCP Flash Memory: Code/Data Storage 41 0xlab – connect your device to
Card: SIM SIP / MCP Flash Memory: Code/Data Storage 41 0xlab – connect your device to
Card: SIM SIP / MCP Flash Memory: Code/Data Storage 41 0xlab – connect your device to
Card: SIM SIP / MCP Flash Memory: Code/Data Storage 41 0xlab – connect your device to

0xlab – connect your device to application – http://0xlab.org/

Modem Chip Evolution for Cellular Phone 0xlab – connect your device to application – http://0xlab.org/

Modem Chip Evolution for Cellular Phone

Modem Chip Evolution for Cellular Phone 0xlab – connect your device to application – http://0xlab.org/ 42

0xlab – connect your device to application – http://0xlab.org/

42

Moble station :: Baseband 0xlab – connect your device to application – http://0xlab.org/ 43

Moble station :: Baseband

Moble station :: Baseband 0xlab – connect your device to application – http://0xlab.org/ 43

0xlab – connect your device to application – http://0xlab.org/

43

Moble station :: Software WAP Browser Applications (GVM, Wavelet, M-Commerce, LBS ) G-APIs Mobile Platform

Moble station :: Software

WAP

Browser

Moble station :: Software WAP Browser Applications (GVM, Wavelet, M-Commerce, LBS ) G-APIs Mobile Platform T-APIs
Moble station :: Software WAP Browser Applications (GVM, Wavelet, M-Commerce, LBS ) G-APIs Mobile Platform T-APIs

Applications (GVM, Wavelet, M-Commerce, LBS

)

Browser Applications (GVM, Wavelet, M-Commerce, LBS ) G-APIs Mobile Platform T-APIs APP Manager P r o

G-APIs

Applications (GVM, Wavelet, M-Commerce, LBS ) G-APIs Mobile Platform T-APIs APP Manager P r o t

Mobile Platform

(GVM, Wavelet, M-Commerce, LBS ) G-APIs Mobile Platform T-APIs APP Manager P r o t o

T-APIs

Wavelet, M-Commerce, LBS ) G-APIs Mobile Platform T-APIs APP Manager P r o t o c

APP Manager

LBS ) G-APIs Mobile Platform T-APIs APP Manager P r o t o c o l

Protocol

Stack

Platform T-APIs APP Manager P r o t o c o l Stack Radio Comm. Interface

Radio Comm. Interface

I/O Device Driver (HW Abstraction Layer)
I/O Device Driver
(HW Abstraction Layer)
Comm. Interface I/O Device Driver (HW Abstraction Layer) Radio Telephony Device Control (CDMA/GSM/GPRS/WCDMA)

Radio Telephony Device Control (CDMA/GSM/GPRS/WCDMA)

Layer) Radio Telephony Device Control (CDMA/GSM/GPRS/WCDMA) Embedded OS (REX, VxWorks, Symbian) Embedded HW 0xlab –
Embedded OS (REX, VxWorks, Symbian) Embedded HW
Embedded OS (REX, VxWorks, Symbian)
Embedded HW
Embedded OS (REX, VxWorks, Symbian) Embedded HW 0xlab – connect your device to application –

0xlab – connect your device to application – http://0xlab.org/

44

Memory Interface ARM On­Chip Bus ARM Core O n - C h i p RAM

Memory

Interface

ARM On­Chip Bus

ARM Core

On-Chip

RAM

Bridge

AHB/ASB

Bus ARM Core O n - C h i p RAM Bridge AHB/ASB DMA Master UART

DMA

Master

Core O n - C h i p RAM Bridge AHB/ASB DMA Master UART PIO APB

UART

PIO

APB

C h i p RAM Bridge AHB/ASB DMA Master UART PIO APB Timer Keypad A typical

Timer

Keypad

A typical AMBA system

AHB: Advanced High-performance Bus ASB: Advanced System Bus

APB: Advanced Peripheral Bus

** AMBA: Advanced Microcontroller Bus Architecture

0xlab – connect your device to application – http://0xlab.org/

45

Example: GPRS Phone 0xlab – connect your device to application – http://0xlab.org/ 46

Example: GPRS Phone

Example: GPRS Phone 0xlab – connect your device to application – http://0xlab.org/ 46

0xlab – connect your device to application – http://0xlab.org/

46

Example: Videophone 0xlab – connect your device to application – http://0xlab.org/ 47

Example: Videophone

Example: Videophone 0xlab – connect your device to application – http://0xlab.org/ 47

0xlab – connect your device to application – http://0xlab.org/

47

ARM 架構快速瀏覽 ARM 歷史背景 ARM 的「家族」 ARM SoC 平台 關鍵概念:

ARM 架構快速瀏覽 ARM 歷史背景 架構快速瀏覽 ARM 歷史背景

ARM 架構快速瀏覽 ARM 歷史背景 ARM 的「家族」 ARM SoC 平台 關鍵概念:

ARM 的「家族」 的「家族」

ARM SoC 平台 平台

關鍵概念: 工作模式、暫存器組、系統狀態、指令 集、例外處理 探討 PXA255 SoC 為例 PXA255 SoC 為例

集、例外處理 探 討 PXA255 SoC 為例 觀察 CuRT 的 運 作並 驅 動 UART 裝置 0xlab
集、例外處理 探 討 PXA255 SoC 為例 觀察 CuRT 的 運 作並 驅 動 UART 裝置 0xlab

觀察 CuRT 作並UART 裝置

0xlab – connect your device to application – http://0xlab.org/

48

善用大的系統模擬器 QEMU

善用 強 大的系統模擬器 QEMU 不 只 是「 窮人 的 ARM 開發 板 」 ( 中國 北京清華

只 是「 窮人 的 ARM 開發 板 」 ( 中國 北京清華 大學 是「窮人ARM 開發( 中國北京清華大學

Skyeye 開發團隊的故事 )

對於學習 / 分 析 ARM 架構與指令集,提供一 個高 整合 度的 互 動 環境 習 / ARM 架構與指令集,提供一個高 整合度的環境

內建 instruction­level tracer instruction­level tracer

gdb server 的 整合 整合

內建 instruction­level tracer gdb server 的 整合 豐富 的週邊 硬 體模擬 Android SDK/Emulator 的

豐富的週邊體模擬

Android SDK/Emulator 的

goldfish 體平台

的實驗部份皆以 QEMU 模擬環境

0xlab – connect your device to application – http://0xlab.org/

的實驗 部份皆以 QEMU 模擬 硬 體 環境 0xlab – connect your device to application – http://0xlab.org/

49

豐富 的 硬 體模擬 環境 Openmoko GTA01/GTA02 emulated by QEMU ARMv4t / Samsung S3C2410/2442 50

豐富體模擬環境

豐富 的 硬 體模擬 環境 Openmoko GTA01/GTA02 emulated by QEMU ARMv4t / Samsung S3C2410/2442 50 Sharp

Openmoko GTA01/GTA02 emulated by QEMU豐富 的 硬 體模擬 環境 ARMv4t / Samsung S3C2410/2442 50 Sharp PDAs emulated by QEMU ARMv5te

ARMv4t / Samsung S3C2410/2442

GTA01/GTA02 emulated by QEMU ARMv4t / Samsung S3C2410/2442 50 Sharp PDAs emulated by QEMU ARMv5te /

50

Sharp PDAs emulated by QEMU ARMv5te / Marvell PXA2xxemulated by QEMU ARMv4t / Samsung S3C2410/2442 50 ARM Versatile PB board emulated by QEMU ARM926ej

ARM Versatile PB board emulated by QEMU50 Sharp PDAs emulated by QEMU ARMv5te / Marvell PXA2xx ARM926ej Gumstix ARMv5te / Marvell PXA25x

ARM926ej

GumstixPXA2xx ARM Versatile PB board emulated by QEMU ARM926ej ARMv5te / Marvell PXA25x (hardware model: connex)

ARMv5te / Marvell PXA25x

(hardware model: connex)

0xlab – connect your device to application – http://0xlab.org/

Emulated by QEMU Serial / JTAG / TCP-IP 0xlab – connect your device to application
Emulated by QEMU
Emulated by QEMU
Emulated by QEMU Serial / JTAG / TCP-IP 0xlab – connect your device to application –

Serial / JTAG / TCP-IP

0xlab – connect your device to application – http://0xlab.org/

51

QEMU 回顧 (1) 快速的模擬器: Portable dynamic translator 完整 系統模擬 instruction sets + processor +

QEMU 回顧 (1)

快速的模擬器: Portable dynamic translator Portable dynamic translator

(1) 快速的模擬器: Portable dynamic translator 完整 系統模擬 instruction sets + processor +

完整系統模擬 系統模擬

instruction sets + processor + peripherals 硬 體平台: x86 , x86_64 , ppc , arm , sparc , mips, nds ( 體平台: x86, x86_64, ppc, arm, sparc, mips, nds( 台心 )

指定特 定機器: qemu­system­arm ­M ? 定機器: qemu­system­arm ­M ?

兩種模擬模式: User, System 模擬模式: User, System

0xlab – connect your device to application – http://0xlab.org/

52

兩種執行 模式 QEMU 回顧 (2) user mode emulation : 可執行非 原生架構之應用 程 式 支援 :

兩種執行模式

QEMU 回顧 (2)

user mode emulation : 可執行非 原生架構之應用 程 式 支援 : x86 , ppc , arm , sparc , 可執行非原生架構之應用支援x86, ppc, arm, sparc, mips

system emulation程 式 支援 : x86 , ppc , arm , sparc , mips qemu linux.img 也可

qemu linux.img: x86 , ppc , arm , sparc , mips system emulation 也可 分 別 指定

也可分 別 指定 kernel image 、 initrd ,及 相 關參數 指定 kernel image initrd ,及關參數

xscale 為例: xscale 為例:

使target ld-linux.so.2

~/poky/build/tmp$ file ./rootfs/bin/busybox

./rootfs/bin/busybox: ELF 32-bit LSB executable, ARM, version 1 (ARM), for GNU/Linux 2.4.0, dynamically linked (uses shared libs), for GNU/Linux 2.4.0, stripped ~/poky/build/tmp$ ./qemu-arm ./rootfs/lib/ld-linux.so.2 \ --library-path ./rootfs/lib ./rootfs/bin/busybox uname -a Linux venux 2.6.20-12-generic #2 SMP Sun Mar 18 03:07:14 UTC 2007 armv5tel unknown

Sun Mar 18 03:07:14 UTC 2007 armv5tel u n k n o w n Processor 變

Processor armv5te (Xscale)

0xlab – connect your device to application – http://0xlab.org/

QEMU 回顧 (3) gdb stub 考 慮 在 system emulation 模式下,該 如何喚起 gdb ? Remote

QEMU 回顧 (3)

gdb stub

慮 在 system emulation 模式下,該 如何喚起 gdb ? system emulation 模式下,該如何喚起 gdb

Remote Debugging : gdb 可透過 serial line 或 TCP/IP 進行遠端除錯 gdb 可透過 serial line TCP/IP 進行遠端除錯

開發平台 (Host) 完整GDB

0xlab – connect your device to application – http://0xlab.org/

gdb stub

Qemu 所模擬的機器

54

QEMU 回顧 (4) gdb stub :透過 TCP/IP (gdb) target remote localhost:1234 qemu 執行選項: ­s Wait

QEMU 回顧 (4)

gdb stub :透過 TCP/IP (gdb) target remote localhost:1234 qemu 執行選項: ­s Wait gdb connection to
gdb stub :透過 TCP/IP
(gdb) target remote localhost:1234
qemu 執行選項:
­s Wait gdb connection to port 1234.
­S Do not start CPU at startup
localhost:1234 gdb stub Qemu 所模擬的機器
localhost:1234
gdb stub
Qemu 所模擬的機器
開發平台 (Host) 運作完整的 GDB
開發平台 (Host)
運作完整的 GDB

0xlab – connect your device to application – http://0xlab.org/

55

[PLAN] 將自製的 CuRT 作業系統作於 PXA255 (emulated by QEMU) 透過 gdb stub TCP/IP ,與 host 端進行 Remote debugging

stub 及 TCP/IP ,與 host 端進行 Remote debugging # dd of=flash­image bs=1k count=16k if=/dev/zero # dd

# dd of=flash­image bs=1k count=16k if=/dev/zero

# dd of=flash­image bs=1k conv=notrunc if=curt_image.bin

qemu­system­arm ­M connex ­pflash flash­image ­serial stdio ­s ­S

#

wait gdb connection to port 1234.

Emulated by QEMU
Emulated by QEMU
­ S # wait gdb connection to port 1234. Emulated by QEMU Serial / JTAG /

Serial / JTAG / TCP-IP

CuRT 原始式碼: (BSD 授權 )

http://jserv.sayya.org/kernel/

56

0xlab – connect your device to application – http://0xlab.org/

CuRT 準 備動作 (1) # cd app/shell # make 取得 CodeSourcery GNU Toolchain 2009q1 解

CuRT 備動作 (1)

# cd app/shell # make
# cd app/shell
# make

取得 CodeSourcery GNU Toolchain 2009q1 裝於 /usr/local/csl 下 於兩個 X 終端機視設定要的 $PATH 環境變

… ( 參考的編譯畫面 ) arm­none­linux­gnueabi­ld ­nostdlib ­static ­e _start ­p ­­no­undefined ­X ­T
… ( 參考的編譯畫面 )
arm­none­linux­gnueabi­ld ­nostdlib ­static ­e _start ­p ­­no­undefined ­X ­T ld­
script.lds \
­o curt_image.elf \
./main.o
/
/device/serial.o
/
/lib/stdio.o
/
/arch/arm/mach­
pxa/port.o
/
/arch/arm/mach­pxa/start.o
/
/arch/arm/mach­pxa/asm_port.o
/
/kernel/kernel.o
/
/kernel/thread.o
/
/kernel/list.o
/
/kernel/sync.o
/
/kernel/ipc.o
arm­none­linux­gnueabi­objcopy ­O binary ­R .note ­R .note.gnu.build­id ­R .comment ­S
curt_image.elf curt_image.bin
檔案 curt_image.elf 為包含除錯資訊的 ELF 執行檔
#

0xlab – connect your device to application – http://0xlab.org/

57

CuRT 準 備動作 (2) # ./prepare_flash # # cgdb ­d arm­none­linux­gnueabi­gdb curt_image.elf cgdb 是 CURSES

CuRT 備動作 (2)

# ./prepare_flash # # cgdb ­d arm­none­linux­gnueabi­gdb curt_image.elf cgdb 是 CURSES 介面撰寫的 GNU GDB
#
./prepare_flash
#
# cgdb ­d arm­none­linux­gnueabi­gdb curt_image.elf
cgdb 是 CURSES 介面撰寫的 GNU GDB 前端,有著類似 vim 的操作環境
預先載入 CuRT 的除錯資訊檔案

./run­on­connex­debug

CuRT 的除錯資訊檔案 ./run­on­connex­debug 58 0xlab – connect your device to application –

58

0xlab – connect your device to application – http://0xlab.org/

CuRT 準 備動作 (3) QEMU ( 在 QEMU 視窗出現後,按下 Ctrl­Alt­2 組合鍵,可切換到 QEMU monitor

CuRT 備動作 (3)

QEMU ( 在 QEMU 視窗出現後,按下 Ctrl­Alt­2 組合鍵,可切換到 QEMU monitor 畫面 ) 一旦 qemu
QEMU
( 在 QEMU 視窗出現後,按下 Ctrl­Alt­2 組合鍵,可切換到 QEMU monitor 畫面 )
一旦 qemu 視窗出現,即可準備
remote gdb 連線,在 cgdb 下方
視窗敲入指令
連線到 qemu 後,按下 'c' 要求
繼續執行

qemu 動時加上 ­s ­S 參數,remote gdb 連線才會繼續執行

(gdb) target remote :1234

59

0xlab – connect your device to application – http://0xlab.org/

QEMU monitor ( 在 QEMU 視 窗 出現後, 按 下 Ctrl­Alt­2 組 合 鍵, 可

QEMU monitor

( 在 QEMU 出現後,Ctrl­Alt­2 鍵,換到 QEMU monitor 畫面 )

(qemu) info registers

切 換到 QEMU monitor 畫面 ) (qemu) info registers 在 gdb 中 按 下 Ctrl-C 組

gdb Ctrl-C 以搶得控制權

static void shell_thread_func(void *pdata){ … While (1) { gets(buf);
static void shell_thread_func(void *pdata){
While (1) {
gets(buf);

0xlab – connect your device to application – http://0xlab.org/

*pdata){ … While (1) { gets(buf); 0xlab – connect your device to application – http://0xlab.org/ Debugger
*pdata){ … While (1) { gets(buf); 0xlab – connect your device to application – http://0xlab.org/ Debugger
Debugger
Debugger

60

QEMU monitor (qemu) info registers R00=00000000 R01=00000020 R02=00000020 R03=00000000 R04=04040404 R05=05050505

QEMU monitor

QEMU monitor (qemu) info registers R00=00000000 R01=00000020 R02=00000020 R03=00000000 R04=04040404 R05=05050505

(qemu) info registers R00=00000000 R01=00000020 R02=00000020 R03=00000000 R04=04040404 R05=05050505 R06=06060606 R07=07070707 R08=08080808 R09=09090909 R10=10101010 R11=a000c438 R12=12121212 R13=a000c42c R14=a0001828 R15=a0000bbc PSR=60000013 ­ZC­ A svc32

r0

r1

r2

r3

r4

r5

r6

r7

r8

r9

r10

r11

r12

r13

r14

r15 (PC)

r9 r10 r11 r12 r13 r14 r15 (PC) ARM Registers 0xlab – connect your device to

ARM

Registers

0xlab – connect your device to application – http://0xlab.org/

31

0

CPSR

– Z C –
– Z C –

61

QEMU monitor Processor Mode svc : supervisor r0 r1 r2 r3 r4 r5 r6 r7
QEMU monitor
QEMU monitor
QEMU monitor Processor Mode svc : supervisor r0 r1 r2 r3 r4 r5 r6 r7 r8
QEMU monitor Processor Mode svc : supervisor r0 r1 r2 r3 r4 r5 r6 r7 r8
Processor Mode svc : supervisor
Processor Mode
svc : supervisor

r0

r1

r2

r3

r4

r5

r6

r7

r8

r9

r10

r11

r12

r13

r14

r15 (PC)

r9 r10 r11 r12 r13 r14 r15 (PC) ARM Regs 62 0xlab – connect your device

ARM

Regs

r10 r11 r12 r13 r14 r15 (PC) ARM Regs 62 0xlab – connect your device to

62

0xlab – connect your device to application – http://0xlab.org/

Basic Processor Modes User (usr) – Normal program execution modes FIQ (fiq) – Support a

Basic Processor Modes

User (usr) – Normal program execution modes (usr) – Normal program execution modes

FIQ (fiq) – Support a high­speed data transfer or channel process (fiq) – Support a high­speed data transfer or channel process

IRQ (irq) – Used for general­purpose interrupt handling (irq) – Used for general­purpose interrupt handling

Supervisor (svc) – A protected mode for OS entered on reset and when a Software Interrupt (svc) – A protected mode for OS entered on reset and when a Software Interrupt instruction executed.

Abort (abt) – Implements VM and/or memory protection (abt) – Implements VM and/or memory protection

Undefined (und) – Support software emulation of HW coprocessors (und) – Support software emulation of HW coprocessors

System: sys – Run privileged OS tasks : sys – Run privileged OS tasks

fiq, irq, svc, abt, und – exception modes

0xlab – connect your device to application – http://0xlab.org/

63

r0 r1 r2 r3 r4 r5 r6 r7 unbanked registers r8 r9 r10 r11 r12

r0

r1

r2

r3

r4

r5

r6

r7

unbanked registers

r8 r9 r10 r11 r12 r13 r14 r15 (PC)
r8
r9
r10
r11
r12
r13
r14
r15 (PC)

31

0

CPSR

r8 r9 r10 r11 r12 r13 r14 r15 (PC) 31 0 CPSR N Z C V
r8 r9 r10 r11 r12 r13 r14 r15 (PC) 31 0 CPSR N Z C V

N Z C V

Link register

banked registers

Every arithmetic, logical, or shifting operation may set CPSR (current program statues register ) bits: current program statues register) bits:

N (negative), Z (zero), C (carry), V (overflow).may set CPSR ( current program statues register ) bits: Examples: ­1 + 1 = 0:

Examples:) bits: N (negative), Z (zero), C (carry), V (overflow). ­1 + 1 = 0: 2

­1 + 1 = 0:N (negative), Z (zero), C (carry), V (overflow). Examples: 2 3 1 ­1+1 = ­2 3

2 3 1 ­1+1 = ­2 3 1 : 31 ­1+1 = ­2 31 :

NZCV = 0110. NZCV = 0101.

0xlab – connect your device to application – http://0xlab.org/

­1+1 = ­2 3 1 : NZCV = 0110. NZCV = 0101. 0xlab – connect your

64

ARM Register Set Current Visible Registers Current Visible Registers Current Visible Registers Current Visible Registers

ARM Register Set

Current Visible Registers

Current Visible Registers

Current Visible Registers

Current Visible Registers

Current Visible Registers

Current Visible Registers

SVC Mode

IRQFIQModeMode

Abort Mode

Undef Mode

User Mode

Mode IRQFIQModeMode Abort Mode Undef Mode User Mode r0 r0 r0 r0 r0 r0 r0 r1

r0

r0 r0

r0

r0

r0

r0

r1

r1 r1

r1

r1

r1

r1

r2

r2 r2

r2

r2

r2

r2

r3

r3 r3

r3

r3

r3

r3

r4

r4 r4

r4

r4

r4

r4

r5

r5 r5

r5

r5

r5

r5

r6

r6 r6

r6

r6

r6

r6

r7

r7 r7

r7

r7

r7

r7

r4 r4 r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r5 r6 r6 r6
r4 r4 r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r5 r6 r6 r6
r4 r4 r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r5 r6 r6 r6
r4 r4 r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r5 r6 r6 r6
r4 r4 r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r5 r6 r6 r6
r4 r4 r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r5 r6 r6 r6
r4 r4 r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r5 r6 r6 r6
r4 r4 r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r5 r6 r6 r6
r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r5 r6 r6 r6 r6 r6

User

User

User

User

User

FIQ

FIQ

FIQ

FIQ

FIQ

FIQ

r8 r8 r8 r8 r8 r8 r8 r8 r9 r9 r9 r9 r9 r9 r9
r8
r8
r8
r8
r8
r8 r8
r8
r9
r9
r9
r9
r9
r9 r9
r9
r10
r10
r10
r10
r10
r10
r10
r10
r11
r11
r11
r11
r11
r11
r11
r11
r12
r12
r12
r12
r12
r12
r12
r12
r13 (sp)
r13 (sp)
r13 (sp)
r13 (sp)
r13 (sp)
r13 (sp)
r13 (sp)
r13 (sp)
r13 (sp)
r13 (sp)
r13 (sp)
r13 (sp)
r14 (lr)
r14 (lr)
r14 (lr)
r14 (lr)
r14 (lr)
r14 (lr)
r14 (lr)
r14 (lr)
r14 (lr)
r14 (lr)
r14 (lr)
r14 (lr)
r15 (pc)
r15 (pc)
r15 (pc)
r15 (pc)
r15 (pc)
r15 (pc)
r15 (pc)
cpsr
cpsr
cpsr
cpsr
cpsr
cpsr
cpsr
spsr
spsr
spsr
spsr
spsr
cpsr cpsr cpsr cpsr cpsr spsr spsr spsr spsr spsr r8 r8 r8 r8 r8 r8
cpsr cpsr cpsr cpsr cpsr spsr spsr spsr spsr spsr r8 r8 r8 r8 r8 r8
cpsr cpsr cpsr cpsr cpsr spsr spsr spsr spsr spsr r8 r8 r8 r8 r8 r8
cpsr cpsr cpsr cpsr cpsr spsr spsr spsr spsr spsr r8 r8 r8 r8 r8 r8
cpsr cpsr cpsr cpsr cpsr spsr spsr spsr spsr spsr r8 r8 r8 r8 r8 r8

r8

r8

r8

r8

r8

r8

r9

r9

r9

r9

r9

r9

r10

r10

r10

r10

r10

r10

r11

r11

r11

r11

r11

r11

r12

r12

r12

r12

r12

r12

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

spsr

spsr

spsr

spsr

spsr

spsr

(lr) r14 (lr) spsr spsr spsr spsr spsr spsr 0xlab – connect your device to application

0xlab – connect your device to application – http://0xlab.org/

Banked out Registers

Banked out Registers

Banked out Registers

Banked out Registers

Banked out Registers

Banked out Registers

IRQ

IRQ

IRQ

IRQ

IRQ

IRQ

SVC

SVC

SVC

SVC

SVC

SVC

Undef

Undef

Undef

Undef

Undef

Undef

Abort

Abort

Abort

Abort

Abort

Abort

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

spsr

spsr

spsr

spsr

spsr

spsr

spsr

spsr

spsr

spsr

spsr

spsr

spsr

spsr

spsr

spsr

spsr

spsr

spsr

spsr

spsr

spsr

spsr

spsr

65

ARM Register Set – All modes User FIQ IRQ SVC Undef Abort r0 r1 r2

ARM Register Set – All modes

User

FIQ

IRQ

SVC

Undef

Abort

r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp)

r0

r1

r2

r3

r4

r5

r6

r7

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

r15 (pc)

User

mode

r0-r7,

r15,

and

cpsr

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

User mode r0-r7, r15, and cpsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr)

cpsr

cpsr spsr

spsr

User

User

User

User

mode

mode

mode

mode

r0-r12,

r0-r12,

r0-r12,

r0-r12,

r15,

r15,

r15,

r15,

and

and

and

and

cpsr

cpsr

cpsr

cpsr

r13 (sp)

r13 (sp)

r13 (sp)

r13 (sp)

r14 (lr)

r14 (lr)

r14 (lr)

r14 (lr)

r13 (sp) r14 (lr) r14 (lr) r14 (lr) r14 (lr) spsr spsr spsr spsr Note: System

spsr

(sp) r14 (lr) r14 (lr) r14 (lr) r14 (lr) spsr spsr spsr spsr Note: System mode

spsr

r14 (lr) r14 (lr) r14 (lr) r14 (lr) spsr spsr spsr spsr Note: System mode uses

spsr

r14 (lr) r14 (lr) r14 (lr) r14 (lr) spsr spsr spsr spsr Note: System mode uses

spsr

Note: System mode uses the User mode register set

0xlab – connect your device to application – http://0xlab.org/

Thumb state

Low

registers
registers

Thumb state High registers

66

ARM Registers ARM 有 37 個 暫存器, 皆 為 32­bit 長 度 個專屬 的 PC

ARM Registers

ARM 有 37 個 暫存器, 皆 為 32­bit 長 度 37 暫存器,32­bit

個專屬的 PC (program counter) PC (program counter)

個專屬的 CPSR (current program status register) CPSR (current program status register)

個專屬的 SPSR ( saved program status registers) SPSR ( saved program status registers)

1

1

5

30 個 通用的暫存器 通用的暫存器

規劃program status registers) 1 1 5 30 個 通用的暫存器 通用組 : r0­r12 registers 挪 作 特別使

通用組 : r0­r12 registers : r0­r12 registers

作 特別使 用 : r13 (stack pointer, sp ), r14 (link register, lr ) 特別使: r13 (stack pointer, sp), r14 (link register, lr)

program counter, r15 ( pc ) r15 (pc)

0xlab – connect your device to application – http://0xlab.org/

際僅16 個可見的暫存器

67

IRQ and FIQ • Program Status Register 31 30 29 28 27 … N Z

IRQ and FIQ

Program Status Register

31 30 29 28 27 … N Z C V
31 30 29 28 27
N
Z C
V

8

7 6 5 4 3 2 1 0 I F M4 M3 M2 M1 M0
7
6
5
4
3
2
1
0
I
F M4
M3
M2
M1
M0

若要抑制 interrupts ,將 "F” “ I” bit 設定為 1

一旦 interrupt 觸發,處理器將變更至 FIQ32_mode registers IRQ32_mode registers

Switch register banks

Copies CPSR to SPSR_mode (saves mode, interrupt flags, etc.)

Changes the CPSR mode bits (M[4:0])

Disables interrupts

Copies PC to R14_mode (to provide return address)

Sets the PC to the vector address of the exception handler

0xlab – connect your device to application – http://0xlab.org/

68

Interrupt Handlers • 當 interrupt 發生時,硬體會跳躍到 interrupt handler time user program user program

Interrupt Handlers

interrupt 發生時,硬體會跳躍到 interrupt handler

time user program user program Task IRQ Interrupt handler IRQ FIQ Interrupt • On interrupt,
time
user program
user program
Task
IRQ Interrupt handler
IRQ
FIQ
Interrupt
• On interrupt, the processor will set the
corresponding interrupt bit in the CPSR to
disable subsequent interrupts of the
same type from occurring.
• However, interrupts of a higher priority
can still occur.

0xlab – connect your device to application – http://0xlab.org/

69

Nested/Re­entrant Interrupts • 但, interrupts 也可能在執行 interrupt handlers 時被 觸發,此為 nested(
Nested/Re­entrant Interrupts
• 但, interrupts 也可能在執行 interrupt handlers 時被
觸發,此為 nested( 巢狀 ) interrupt
time
user program
user program
Task
IRQ Interrupt handler
IRQ
FIQ Interrupt handler
FIQ
Interrupt
• On interrupt, the processor will set the
corresponding interrupt bit in the CPSR to
disable subsequent interrupts of the
same type from occurring.
Second
Interrupt
• However, interrupts of a higher priority
can still occur.

0xlab – connect your device to application – http://0xlab.org/

70

Timing of Interrupts • 在 interrupt handler 實際運作前,必須保存目前程 式的 register (

Timing of Interrupts

interrupt handler 實際運作前,必須保存目前程

式的 register ( 若觸及這些 registers)

That's why the FIQ has lots of extra registers ­ to minimize CPU context saving overhead

extra registers ­ to minimize CPU context saving overhead Task IRQ FIQ user program user program

Task

IRQ

FIQ

user program

user program

saving overhead Task IRQ FIQ user program user program cpu context saved “servicing” interrupt Interrupt

cpu context saved

“servicing” interrupt Interrupt latency
“servicing” interrupt
Interrupt latency
context saved “servicing” interrupt Interrupt latency Interrupt Interrupt response cpu context restored 0xlab –

Interrupt

saved “servicing” interrupt Interrupt latency Interrupt Interrupt response cpu context restored 0xlab – connect
saved “servicing” interrupt Interrupt latency Interrupt Interrupt response cpu context restored 0xlab – connect

Interrupt response

cpu context restored

0xlab – connect your device to application – http://0xlab.org/

time

71

Exception Handling When an exception occurs, the ARM: Copies CPSR into SPSR_<mode> Sets appropriate CPSR

Exception Handling

Exception Handling When an exception occurs, the ARM: Copies CPSR into SPSR_<mode> Sets appropriate CPSR bits

When an exception occurs, the ARM:

Copies CPSR into SPSR_<mode>Exception Handling When an exception occurs, the ARM: Sets appropriate CPSR bits Change to ARM state

Sets appropriate CPSR bitsoccurs, the ARM: Copies CPSR into SPSR_<mode> Change to ARM state Change to exception mode Disable

CPSR into SPSR_<mode> Sets appropriate CPSR bits Change to ARM state Change to exception mode Disable

Change to ARM state Change to exception mode Disable interrupts (if appropriate)

Change to exception mode Disable interrupts (if appropriate)   0x1C 0x18 0x14 Stores the return address
 

0x1C

0x18

0x18

0x14

0x14

Stores the return address in LR_<mode>0x10

0x10

0x0C

Sets PC to vector address0x08

0x08

To return, exception handler needs to:

0x04

0x00

To return, exception handler needs to: 0x04 0x00 Restore CPSR from SPSR_<mode> Restore PC from

Restore CPSR from SPSR_<mode>

Restore PC from LR_<mode>This can only be done in ARM state. 0xlab – connect your device to application

This can only be done in ARM state.

0xlab – connect your device to application – http://0xlab.org/

FIQ

IRQ

(Reserved)

Data Abort

Prefetch Abort

Software Interrupt

Undefined Instruction