Arm 1 Overview 090720075211 Phpapp01

ARM SoC
PartIARM .SoC .
JimHuang(jserv) from0xlab July18,2009
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0xlabconnectyourdevicetoapplicationhttp://0xlab.org/
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ARM GNUToolchainCodeSourcery2009q1 QEMU0.10.5 CuRTv1( ARM ) ARMSoC Marvell/IntelPXA255
3
Agenda
ARM ARMSoC
4
ARM ARM ARM

ARMSoC
5
Part I
ARM
Most of the above devides are powered by ARM.
Darwin'sConcept
8
ARM
BBCMicro(BBCMicrocomputerSystem) BBC(Britsh BroadcastingCorporation) BBCComputerLiteracy Project 1980
TheComputerProgramme ,1982
programming,graphics,soundandmusic,Teletext, controllingexternalhardwareandartificialintelligence
( BBCMicro ) AcornComputers Atommicrocomputer Proton 2MHzMOSTechnology6502CPU 1982 Sinclair ZXSpectrum Acrom

9
ARM
19831985 AcornComputers ARMchip AcornRISCMachine 1990 AdvancedRISCMachine(ARM) 6502processor ARM1 VLSITechnology,Inc. (1985) ARM2 (1986) 32bitdatabus,26bitaddressspace(top6bitsusedasstatusflag) 1632bitregisters(1PC),30,000transistors Nomicrocode,cache,Lowpower NS32016 Acorn 1985 OlivettiIngetCie ARM3 4KBCache,25MHz(19891990)
10
ARMLtd.
1990 Acorn 1991 Apple,Acorn,VLSI ARMLtd. ARMLtd. ARM3 ARM6 ARM600 ARM610 AppleNewtonPDA(1998) 1992 3DO ( ) ARMLtd. ARM ARM ARM (IP) ARM ARM ARM7TDMI ARMcore
11
ARM
DEC ARMLtd. ARM6 233MHz StrongARM(SA1x ) PDA HPiPAQ 500mWattofpower@160MHz@.35 m DEC Intel Intel(1997) Intel StrongARM Xscale StrongARM Intel P.A.Semi (PaloAltoSemiconducto)(2003) Apple (2008) Intel XScale Marvell(2006)
12
ARM
ArchitectureVersions ARMV3,V4,V5,V6,V7 architecture ISA(InstructionSetArchitecture) Implementations( ) ARM6(1991),ARM7(1995),ARM9(1997) ARM10(1999),ARM11(2003) cores
13
14
0x41A(ARMLtd) Revision Identification, ARM 0x44D(DEC) 0x69I(IntelCorporation) Architecture version / # cat /proc/cpuinfo / # cat /proc/cpuinfo Processor : ARMv7 Processor rev 3 (v7l) Processor : ARMv7 Processor rev 3 (v7l) BogoMIPS : 471.61 BogoMIPS : 471.61 Features : swp half thumb fastmult vfp edsp thumbee neon Features : swp half thumb fastmult vfp edsp thumbee neon CPU implementer : 0x41 CPU implementer : 0x41 CPU architecture: 7 CPU architecture: 7 CPU variant : 0x1 CPU variant : 0x1 CPU part : 0xc08 CPU part : 0xc08 ARMISAfeature CPU revision : 3 CPU revision : 3 Hardware Hardware Revision Revision Serial Serial : : : : : : OMAP3 Beagle Board OMAP3 Beagle Board 0020 0020 0000000000000000 0000000000000000
Application Note Core Type &
ARM (IP) ARM

15
ARMv1
Implementation: ARM1 (ALU) Byte,halfword,word Load/Store (jump/branch) procedurecall (SWI) 64MB
16
ARMv2
Implementation:ARM2 ARM3(ARMv2a) (FIQ) SWP/SWPB 64MB(32bitdatabus,26bitaddress space(top6bitsusedasstatusflag)
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ARMv2::SWP
ARM word Twocycles singleatomicaction SupportforRTsemaphores
R0 R1 R2 R7 R8 R15
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ARMv3
32bit(4GB) CPSR SPSR Implementation:ARM6 AppleNewtonPDA
LDM Mi Mi+1 Mi+2 Mi+14 Mi+15 STM
MRS/MSR CPSR/SPSR R0
MRS CPSR SPSR MSR R1 R7 R8 R14 R15
R0 R1 R2 R14 R15
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ARMv3::MemoryAddressing
Byte:8bits Halfword:16bits
mustbealignedto2byteboundaries
Word:32bits
mustbealignedto4byteboundaries
bit 31
23 19 15 22 18 14 10 6 2 21 17 13 9 5 1
bit 0
20 16 12 8 4 0
ARMaddresscanbe32bitslong. Addressreferstobyte.
Address4startsatbyte4.
word16
littleor bigendianmode
bit31
half-word14 half-word12
11 7 3
littleendian
bit0
byte3 byte2 byte1 byte0 bit0 bigendian bit31

20
word8
byte6 half-word4
byte3 byte2 byte1 byte0
byte address byte0 byte1 byte2 byte3
ARMv4
ARM ARMv3 16bitThumb ( ) Implementation:ARM7,ARM9,StrongARM GameBoyAdvance,NintendoDS,iPod,LEGO NXT,OpenmokoGTA01/GTA02 16bitThumb (SWI) (SVC) user
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ARMv4::ARM/Thumb
32bitARMInstruction Sets 16bitThumbInstruction Set
cache
Allinstructionsare executedasARM Decompressorconverts ThumbtoequivalentARM instruction Decompressorpresentin thedecodestageofthe pipeline.

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ARMv5
Implementation:ARM10,Xscale HTCDream(GoogleG1Phone) BLX (ImprovedARMandThumbinterworking) CLZ (countleadingzeroes) BRK DSP (v5TE)
EenhancedDSPinstructionsincludingsaturatedarithmetic operationsand16bitmultiplyoperations
Jazelle
JsupportfornewJavastate,offeringhardwareand optimizedsoftwareaccelerationofbytecodeexecution.
coprocessor
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ARMv5::DSPExtension(E)
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ARMv5::coprocessor
Marvell/IntelXscaleWirelessMMXcoprocessor
x86 MMX/SSE Xscale coprocessor
ARM 16 coprocessor Xscale coprocessor0 coprocessor1 Xscalecoprocessorinstructions Coprocessordatatransfers Coprocessordataoperations Coprocessorregisterloadandstore

ARM Core
Co-processor
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ARMv6
Implementation:ARM11 AppleiPhone(1st/2nd) / 60 SIMD(SingleInstructionMultiple Data) 1.75 atomicoperations(LDREX/STREX) 30% MixedEndian (LittleEndianOS+BitEndian DataforTCP/IP) UnalignedData ( DSP )
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ARMv6::SIMDExtensions
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ARMv6::EndiannessSupport(Ebit)
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ARMv6::ByteReverseinstruction
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ARMv7
Implementation:CortexA8 ARMv7ISA implementation AdvancedSIMDMediaExtension(NEON) ARMv7 core Cortex Inorder,dualissuesuperscalarcore 13stageintegerpipeline 10stageNEONmediapipeline DedicatedL2with9cyclelatency Branchpredictorbasedonglobalhistory NEON:64/128bitSIMD,2x4xoverpriorARMv6SIMD ARMv7 Thumb2,ThumbEE(fordynamic/JITcompiler) 1GHz 300mW <4mm2at65nm( NEON,L2cache,ETM)
Source:WilliamsonofARMatFallprocessorForum05 0xlabconnectyourdevicetoapplicationhttp://0xlab.org/
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ARMv7::NEON
64/128bit SIMD Twoaliasedregisterfiles 32x64bit(D0D31) 16x128bit(Q0Q15) SharedwithVFP IntegerandSPFPprocessing 8,16,32,64bitintegers EncodedinARMandThumb2
D1.U8 128bit
D0 D1 D2 D3 Q0 Q1
D30 D31
Q15
Alias,samephysicalstructure 64bit D0.U8 Q0.F32
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Source:GrisenthwaiteofARM 0xlabconnectyourdevicetoapplicationhttp://0xlab.org/
vadd.I16 D0, D1, D2 D1 D2
vmul.I32.S16 Q0, D2, D3 D2 D3
+
64b
+
D0
*
128b
*
Q0
vshr.I16.I32 D0, Q1, #5 128b Q1
>> >> >> >>

D0
#5
32
Source:GrisenthwaiteofARM 0xlabconnectyourdevicetoapplicationhttp://0xlab.org/
NEONLoadorstore1elementor2,3,4elelmentstructure Handlecomplexnumber,coordinates,etc. EasyAoStoSoA
X0 Y0 Z0 X1 Y1 Z1
vld3.16 {D0, D1, D2}, [R0]! X3 Y3 vst3.16 {D0, D1, D2}, [R0]! Z3 X2 Y2 Z2 X1 Y1 Z1 X0 Y0 Z0 D0 D1 D2
No data swizzling needed! Fewer instruction, higher performance
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ARMv7::Thumb2
Thumb 16/32bit MostofThumb2areunconditional,similartoARM Newconditionalexecutioninstruction(IfThen)isintroduced (a.k.a.GuardedExecution) Enables1to4followinginstructionstobeconditional
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34
ARMcoreperformanceroadmap
Release AdvDevelopment 2500
ARMCortex IntelligentComputing
2000
CortexA8"Tiger"
1500
DMIPS
1000
750
x4
ARM1176JZFS ARM11MPCore ARM1136EJS ARM1026EJS ARM926EJS
500
250
Pre2005 Source:WilliamsonofARMatFallprocessorForum05
2005
2006
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CortexA8NEONPerformance
Cortex-A8 NEON performance vs. ARMv5 and ARMv6 implementations
1x 2x 3x 4x
MPEG4 GSMAMR MP3Decoder

ARM926EJS ARMv5TE ARM1136JS ARMv6
CortexA8 NEON
CPU bandwidth required for various applications: MPEG4 VGA decode1 MP3 decode, 320kbps 48kHz, worst case2 Quake 2-like application, CIF resolution3 H.264 (estimated)
1)MPEG4SimpleProfile@30fps512kbps,133MHzSDRAM10111memory 2)MP3Decoder@320kbps48kHz(worstcasemeanscoldstartoncontextswitch),133MHzSDRAM10111memory 3)Quake2likesimulator,fullsoftwaregraphicspipeline,FPimplementation133MHzSDRAM10111memory Source:ARMDeveloperconference
275 MHz 9.8 MHz 300 MHz 350 MHz
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ARM
ARMSoC

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SoC(SystemonChip)
IC
Programmableprocessor Onchipmemory HWacceleratingfunctionunits(DSP) Peripheralinterfaces(GPIO) Embeddedsoftware
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SoC
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DisplayDriverIC: TFT, OLED CameraChipset: CMOS - CCD Connectivity: WLAN, GPS, Bluetooth Processor: ARM
Modem: GSM/GPRS, WCDMA
SoC
RF/Analog: Rx/Tx, Zero IF

RAM: Mobile DRAM, SRAM, UtRAM
SmartCard: SIM SIP/MCP FlashMemory: Code/Data Storage
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ModemChipEvolutionforCellularPhone
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Moblestation::Baseband
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Moblestation::Software
WAP Browser
Applications (GVM, Wavelet, M-Commerce, LBS..)
G-APIs
Mobile Platform
T-APIs
APP Manager
Protocol Stack
Radio Comm. Interface
I/O Device Driver (HW Abstraction Layer)
Radio Telephony Device Control (CDMA/GSM/GPRS/WCDMA) Embedded OS (REX, VxWorks, Symbian) Embedded HW 44
ARMOnChipBus
ARM Core
On-Chip RAM AHB/ASB Bridge
UART
PIO
Memory Interface
APB
DMA Master
Timer
Keypad
A typical AMBA system
AHB: Advanced High-performance Bus ASB: Advanced System Bus APB: Advanced Peripheral Bus
** AMBA: Advanced Microcontroller Bus Architecture

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Example:GPRSPhone
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Example:Videophone
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ARM ARM ARM ARMSoC
PXA255SoC
CuRT UART
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QEMU
ARM (
Skyeye )
/ ARM instructionleveltracer gdbserver AndroidSDK/Emulator goldfish

QEMU
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OpenmokoGTA01/GTA02emulatedbyQEMU ARMv4t/SamsungS3C2410/2442 SharpPDAsemulatedbyQEMU ARMv5te/MarvellPXA2xx ARMVersatilePBboardemulatedbyQEMU ARM926ej Gumstix ARMv5te/MarvellPXA25x (hardwaremodel:connex)
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EmulatedbyQEMU
Serial / JTAG / TCP-IP
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QEMU (1)
Portabledynamictranslator
instructionsets+processor+peripherals x86, x86_64, ppc, arm, sparc, mips, nds( ) qemusystemarmM?
User,System
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QEMU (2)
usermodeemulation x86,ppc,arm,sparc,mips systememulation
qemulinux.img kernelimage initrd
target ld-linux.so.2 ~/poky/build/tmp$ file ./rootfs/bin/busybox ./rootfs/bin/busybox: ELF 32-bit LSB executable, ARM, version 1 (ARM), for GNU/Linux 2.4.0, dynamically linked (uses shared libs), for GNU/Linux 2.4.0, stripped ~/poky/build/tmp$ ./qemu-arm ./rootfs/lib/ld-linux.so.2 \ --library-path ./rootfs/lib ./rootfs/bin/busybox uname -a Linux venux 2.6.20-12-generic #2 SMP Sun Mar 18 03:07:14 UTC 2007 armv5tel unknown
xscale
Processor armv5te (Xscale) 53
QEMU (3)
gdbstub systememulation gdb RemoteDebugging gdb serialline TCP/IP
(Host) Qemu GDB 0xlabconnectyourdevicetoapplicationhttp://0xlab.org/
gdb stub
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QEMU (4)
gdbstub TCP/IP (gdb)targetremotelocalhost:1234 qemu sWaitgdbconnectiontoport1234. SDonotstartCPUatstartup
localhost:1234 (Host) GDB

gdb stub
Qemu
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[PLAN] CuRT PXA255(emulatedbyQEMU) gdbstub TCP/IP host Remotedebugging

#ddof=flashimagebs=1kcount=16kif=/dev/zero #ddof=flashimagebs=1kconv=notruncif=curt_image.bin #qemusystemarmMconnexpflashflashimageserialstdio sS
wait gdb connection to port 1234.
CuRT (BSD )
http://jserv.sayya.org/kernel/
EmulatedbyQEMU Serial / JTAG / TCP-IP
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CuRT (1)
CodeSourcery GNU Toolchain 2009q1 /usr/local/csl X $PATH
#cdapp/shell #make
( ) ...
armnonelinuxgnueabildnostdlibstatice_startpnoundefinedXTld script.lds\ ocurt_image.elf\ ./main.o../../device/serial.o../../lib/stdio.o../../arch/arm/mach pxa/port.o../../arch/arm/machpxa/start.o../../arch/arm/machpxa/asm_port.o ../../kernel/kernel.o../../kernel/thread.o../../kernel/list.o ../../kernel/sync.o../../kernel/ipc.o armnonelinuxgnueabiobjcopyObinaryR.noteR.note.gnu.buildidR.commentS curt_image.elfcurt_image.bin curt_image.elf ELF #
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CuRT (2)
#./prepare_flash #./runonconnexdebug
#cgdbdarmnonelinuxgnueabigdbcurt_image.elf
cgdb CURSES GNUGDB vim CuRT
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CuRT (3)
QEMU
qemu sS remotegdb
( QEMU CtrlAlt2 QEMUmonitor )
(gdb)targetremote:1234
qemu remotegdb cgdb qemu 'c'

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QEMUmonitor
( QEMU CtrlAlt2 QEMUmonitor )
(qemu) inforegisters
gdb Ctrl-C
staticvoidshell_thread_func(void*pdata){ While(1){ ... gets(buf);
Debugger
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QEMUmonitor
(qemu) inforegisters R00=00000000R01=00000020R02=00000020R03=00000000 R04=04040404R05=05050505R06=06060606R07=07070707 R08=08080808R09=09090909R10=10101010R11=a000c438 R12=12121212R13=a000c42cR14=a0001828R15=a0000bbc PSR=60000013ZCAsvc32
r0 r8 r1 r9 r2 r10 r3 r11 r4 r12 r5 r13 ARM Registers r6 r14 r7 r15(PC) 0xlabconnectyourdevicetoapplicationhttp://0xlab.org/
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CPSR
ZC
61
QEMUmonitor
ProcessorMode svc:supervisor
r0 r8 r1 r9 r2 r10 r3 r11 r4 r12 r5 r13 ARM r6 r15(PC) r14 Regs r7 0xlabconnectyourdevicetoapplicationhttp://0xlab.org/
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BasicProcessorModes
User(usr)Normalprogramexecutionmodes FIQ(fiq)Supportahighspeeddatatransferorchannel
process IRQ(irq)Usedforgeneralpurposeinterrupthandling
Supervisor(svc)AprotectedmodeforOS
enteredonresetandwhenaSoftwareInterrupt instructionexecuted. Abort(abt)ImplementsVMand/ormemoryprotection Undefined(und)SupportsoftwareemulationofHW coprocessors System:sysRunprivilegedOStasks
fiq, irq, svc, abt, und exception modes

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r0 r1 r2 r3 r4 r5 r6 r7
unbanked registers
r8 r9 r10 r11 r12 r13 r14 r15(PC)

banked registers
31
CPSR
NZCV
Link register
Everyarithmetic,logical,orshiftingoperationmaysetCPSR (currentprogramstatuesregister)bits:
N(negative),Z(zero),C(carry),V(overflow).
Examples:
1+1=0: NZCV=0110.
64
231 1+1=231 : NZCV=0101.
ARMRegisterSet
Current Visible Registers Current Visible Registers
Abort SVC Mode Undef Mode IRQ Mode UserMode FIQ Mode
r0 r0 r1 r1 r2 r2 r3 r3 r4 r4 r5 r5 r6 r6 r7 r7 r8 r8 r9 r9 r10 r10 r11 r11 r12 r12 r13 (sp) r13 (sp) r14 (lr) r14 (lr) r15 (pc) r15 (pc) cpsr cpsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr r8 r9 r10 r11 r12 r13 (sp) r13 (sp) r14 (lr) r14 (lr) r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r13 (sp) r13 (sp) r14 (lr) r14 (lr) r13 (sp) r13 (sp) r14 (lr) r14 (lr) r13 (sp) r13 (sp) r14 (lr) r14 (lr) r13 (sp) r13 (sp) r14 (lr) r14 (lr)
Banked out Registers Banked out Registers

User User FIQ IRQ IRQ SVC SVC Undef Undef Abort Abort
65
ARMRegisterSetAllmodes
User
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr spsr spsr spsr spsr spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) User mode r0-r7, r15, and cpsr
FIQ
IRQ
SVC
Undef
Abort
User mode r0-r12, r15, and cpsr
Thumb state Low registers
Thumb state High registers
Note: System mode uses the User mode register set 66

ARMRegisters
ARM 37 32bit
1 PC(programcounter) 1 CPSR(currentprogramstatusregister) 5 SPSR(savedprogramstatusregisters) 30
:r0r12registers :r13(stackpointer,sp),r14(linkregister,lr)
programcounter,r15(pc)
16
67
IRQandFIQ
ProgramStatusRegister 31 30 29 28 27 8 N Z C V
6 I
5 F
M4 M3 M2 M1 M0
interrupts "F Ibit 1
interrupt FIQ32_moderegisters IRQ32_moderegisters

Switchregisterbanks CopiesCPSRtoSPSR_mode(savesmode,interruptflags,etc.) ChangestheCPSRmodebits(M[4:0]) Disablesinterrupts CopiesPCtoR14_mode(toprovidereturnaddress) SetsthePCtothevectoraddressoftheexceptionhandler
68
InterruptHandlers
interrupt interrupthandler
time
Task IRQ FIQ
userprogram
IRQInterrupthandler
userprogram
Interrupt
Oninterrupt,theprocessorwillsetthe correspondinginterruptbitintheCPSRto disablesubsequentinterruptsofthe sametypefromoccurring. However,interruptsofahigherpriority canstilloccur.

69
Nested/ReentrantInterrupts
interrupts interrupthandlers nested( )interrupt
Task IRQ FIQ
userprogram
IRQInterrupthandler FIQInterrupthandler
time
userprogram
Interrupt Second Interrupt

Oninterrupt,theprocessorwillsetthe correspondinginterruptbitintheCPSRto disablesubsequentinterruptsofthe sametypefromoccurring. However,interruptsofahigherpriority canstilloccur.

70
TimingofInterrupts
interrupthandler register( registers)
That'swhytheFIQhaslotsofextraregisterstominimize CPUcontextsavingoverhead
time
Task IRQ FIQ
userprogram
cpucontextsaved
userprogram
servicinginterrupt cpucontextrestored
Interruptlatency
Interrupt
Interruptresponse
71
ExceptionHandling
Whenanexceptionoccurs,theARM:
CopiesCPSRintoSPSR_<mode> SetsappropriateCPSRbits
ChangetoARMstate Changetoexceptionmode Disableinterrupts(ifappropriate)
0x1C 0x18 0x14 0x10 0x0C 0x08 0x04 0x00
FIQ IRQ (Reserved) Data Abort Prefetch Abort

Software Interrupt Undefined Instruction
StoresthereturnaddressinLR_<mode> SetsPCtovectoraddress
Toreturn,exceptionhandlerneedsto:
RestoreCPSRfromSPSR_<mode> RestorePCfromLR_<mode>
Reset
Vector Table
Vector table can be at 0xFFFF0000 on ARM720T and on ARM9/10 family devices
ThiscanonlybedoneinARMstate.
72
Example:UsertoFIQmode
Registers in use
Registers in use
User Mode
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq r14_fiq
FIQ Mode
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq r14_fiq r15 (pc)
EXCEPTION
cpsr
Return address calculated from User mode PC value and stored in FIQ mode LR
spsr_fiq
cpsr spsr_fiq
User mode CPSR copied to FIQ mode SPSR
73
MichaelJordansaid... I can accept failure. Everyone fails at something. But I cannot accept not trying.
PartII CuRT PXA255 SoC

74
75
PXA255FunctionBlock
RTC OS Timer PWM(2) Interrupt Controller Clock & Power Man. I2S I2C AC97 FF_UART BT_UART
0x4400_0000
Memory Controller
PCMCIA & CF Control
XCVR Socket 0, 1
System Bus
Dynamic Memory Control
SDRAM/ SMROM 4 banks
Megacell Core
s u B l ar e h p r e P i
Write Buffer
Read Buffer
Variable Latency I/O Control
O / I e s o pr u P l ar e n e G
Slow lrDA Fast lrDA
Load/Store Data
e g d r B d n a r e l or t n o C A MD i l
DMMU
Addr Dcache (32 Kbytes)
ASIC CS #3,4,5
SSP NSSP
USB Client MMC
Minicache
IMMU Icache (32 Kbytes)
PC
XScale Core
Static Memory Control
Instructions
3.6864 MHz Osc 32.768 KHz Osc
ROM/ Flash SRAM 4 banks
CS #0,1,2 Color or Grayscale LCD Controller
76
PXA255MemoryModel
MMU Buffers Memory Memory Controller
On-chip Caches
Core
Physical Addresses
Virtual Addresses
Refer: http://www.intel.com/design/pca/prodbref/252780docs.htm
77
MemoryMap
0hFFFF FFFF 0hB000 0000 0hAC00 0000 0hA800 0000 0hA400 0000 0hA000 0000 0h4C00 0000 0h4800 0000 0h4400 0000 0h4000 0000 0h3000 0000 0h2000 0000 0h1800 0000 0h1400 0000 0h1000 0000 0h0C00 0000 0h0800 0000 0h0400 0000 0h0000 0000 Reserved (1280 Mbytes) SDRAM Bank 3 (64 Mbytes) SDRAM Bank 2 (64 Mbytes) SDRAM Bank 1 (64 Mbytes) SDRAM Bank 0 (64 Mbytes) Reserved (1344 Mbytes) Memory Mapped registers (Memory Control) Memory Mapped registers (LCD) Memory Mapped registers (Peripherals) PCMCIA/CF - Slot 1 (256 Mbytes) PCMCIA/CF - Slot 0 (256 Mbytes)
Dynamic Memory Interface 256 Mbytes
Memory Mapped registers Interface 192 Mbytes
PCMCIA Interface 512 Mbytes
Reserved (128 Mbytes)

Static Chip Select 5 (64 Mbytes) Static Chip Select 4 (64 Mbytes) Static Chip Select 3 (64 Mbytes) Static Chip Select 2 (64 Mbytes) Static Chip Select 1 (64 Mbytes) Static Chip Select 0 (64 Mbytes)
Static Memory Interface (ROM, Flash, SRAM) 384 Mbytes
0x4000000-0x4C00000 Memory Mapped
78
MemoryMap
0hFFFF FFFF 0hB000 0000 0hAC00 0000 0hA800 0000 0hA400 0000 0hA000 0000 0h4C00 0000 0h4800 0000 0h4400 0000 0h4000 0000 0h3000 0000 0h2000 0000 0h1800 0000 0h1400 0000 0h1000 0000 0h0C00 0000 0h0800 0000 0h0400 0000 0h0000 0000 Reserved (1280 Mbytes) SDRAM Bank 3 (64 Mbytes) SDRAM Bank 2 (64 Mbytes) SDRAM Bank 1 (64 Mbytes) SDRAM Bank 0 (64 Mbytes) Reserved (1344 Mbytes) Memory Mapped registers (Memory Control) Memory Mapped registers (LCD) Memory Mapped registers (Peripherals) PCMCIA/CF - Slot 1 (256 Mbytes) PCMCIA/CF - Slot 0 (256 Mbytes)
SoC (peripheral)
MMIO (Memory-Mapped Input/Output) Dynamic Memory Interface
256 Mbytes
Memory Mapped registers Interface 192 Mbytes
PCMCIA Interface 512 Mbytes
Reserved (128 Mbytes)

Static Chip Select 5 (64 Mbytes) Static Chip Select 4 (64 Mbytes) Static Chip Select 3 (64 Mbytes) Static Chip Select 2 (64 Mbytes) Static Chip Select 1 (64 Mbytes) Static Chip Select 0 (64 Mbytes)
Static Memory Interface (ROM, Flash, SRAM) 384 Mbytes
PXA255 0x0x4000000-0x4400000
79
PXA255coreFunctionDiagram
UDCL_DD(15:0) L_FCLK L_LCLK L_PCLK L_BIAS GP(27:0)
Serial Channel 0 (USB) Serial Channel 1 Serial Channel 2 (IrDA) Serial Channel 3 (UART)
UDC+ RXD_1 TXD_1 RXD_2 TXD_2 RXD_3 TXD_3 TXD_C RXD_C
LCD Control
nCAS/ DQM(3:0) nRAS/ nSDCS(3:0)

nOE nWE nCS(5:0) RDY
GPIO Ports
Serial Channel 4(CODEC)
SFRM_C SCLK_C BATT_FAULT
Memory Control
Power Management
VDD_FAULT PWR_EN TCK_BYP TESTCLK PEXTAL PXTAL TEXTAL
Intel XScale* PXA 250 [256-pins]
nSDRAS nSDCAS
SDCKE<1:0> SDCLK<2:0> RD/nWR

nPOE nPWE nPIOR nPIOW nPCE<2:1> PSKTSEL nPREG nPWAIT nIOIS16
Transceiver Control
Clocks, Reset and Test
TXTAL nRESET
PCMCIA Bus Signals
nRESET_OUT SMROM_EN
ROM_SEL TCK TDI TDO TMS nTRST
A<25:0>
D<31:0> VDD VDDX VSS/VSSX
Address Bus Data Bus Supply
JTAG
80
PXA255Serial/UART
UDCL_DD(15:0) L_FCLK L_LCLK L_PCLK L_BIAS GP(27:0)
Serial Channel 0 (USB) Serial Channel 1 Serial Channel 2 (IrDA) Serial Channel 3 (UART) Serial Channel 4(CODEC) Power Management
UDC+ RXD_1 TXD_1 RXD_2 TXD_2 RXD_3 TXD_3 TXD_C RXD_C SFRM_C SCLK_C BATT_FAULT VDD_FAULT PWR_EN
LCD Control GPIO Ports

nOE nWE nCS(5:0) RDY nSDRAS nSDCAS
UniversalAsynchronousReceiver/Transmitter(UART):controller
TCK_BYP TESTCLK PEXTAL PXTAL TEXTAL nPOE nPWE nPIOR nPIOW nPCE<2:1> PSKTSEL nPREG nPWAIT nIOIS16
Intel XScale* PXA 250 [256-pins]
Memory Control
Transceiver Control PCMCIA Bus Signals Address Bus Data Bus Supply
TXTAL nRESET
Computer CPU CPU
ParalleltoSerial TX ParalleltoSerial ROM_SEL Converter Converter TCK SerialtoParallel SerialtoParallel RX Converter Converter
JTAG
TDI TDO TMS nTRST
nRESET_OUT SMROM_EN
RX TX
Terminal
A<25:0>
Serial Link
81
UDC-
L_DD(15:0) L_FCLK L_LCLK L_PCLK L_BIAS GP(27:0)
Serial Channel 0 (USB) Serial Channel 1 Serial Channel 2 (IrDA) Serial Channel 3 (UART) Serial Channel 4(CODEC)
UDC+ RXD_1 TXD_1 RXD_2 TXD_2 RXD_3 TXD_3 TXD_C RXD_C SFRM_C SCLK_C BATT_FAULT
LCD Control GPIO Ports

nOE nWE nCS(5:0) RDY nSDRAS nSDCAS
Intel VDD_FAULT XScale* Power Management PWR_EN UniversalAsynchronousReceiver/Transmitter PXA 250 TCK_BYP [256-pins] (UART):controller
TESTCLK PEXTAL PXTAL TEXTAL
Memory Control

nPOE nPWE nPIOR nPIOW nPCE<2:1> PSKTSEL nPREG nPWAIT nIOIS16
Transceiver Control PCMCIA Bus Signals Address Bus Data Bus Supply
TXTAL nRESET
nRESET_OUT SMROM_EN
ROM_SEL TCK TDI TDO TMS nTRST
A<25:0>
JTAG
FFUART (Full function UART) (memory mapped) base address 0x40100000

82
DataCommunication
serialline
Dataisconvertedfromparallel(bytes)toserial(bits)inthebus interface Bitsaresentoverwire(TX)toterminal(orbackfromterminalto computer) Receivingend(RX)translatesbitstreambackintoparalleldata (bytes)
Computer CPU CPU
ParalleltoSerial TX ParalleltoSerial Converter Converter SerialtoParallel RX SerialtoParallel Converter Converter
RX
Terminal
TX
Serial Link
83
SerialPort
RxRegister FIFOBuffer
0 1 2 3 4 5 6 7
RxRegister FIFOBuffer
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 Clock 0 1 2 3 4 5 6 7
FIFOBuffer TxRegister FIFOBuffer
0 1 2 3 4 5 6 7 Clock 0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 Processor
TxRegister
0 1 2 3 4 5 6 7 Peripheral
84
SampleshellforCuRT
int main() int main() { { SerialInit(); SerialInit(); init_interrupt_control(); init_interrupt_control(); init_curt(); init_curt();
CuRT_v1/app/shell/main.c CuRT_v1/app/shell/main.c
... ... shell_tid = thread_create(&shell_thread, shell_tid = thread_create(&shell_thread, &thread_stk[0][THREAD_STACK_SIZE-1], &thread_stk[0][THREAD_STACK_SIZE-1], shell_thread_func, shell_thread_func, "shell_thread", "shell_thread", 5, NULL); 5, NULL);
static void shell_thread_func(void *pdata) static void shell_thread_func(void *pdata) { { ... ... char buf[80] = { '\0' }; char buf[80] = { '\0' }; while (1) { while (1) { printf("$ "); printf("$ "); gets(buf); gets(buf); printf("\n"); printf("\n"); ... ... else if (!strcmp(buf, "stat")) { else if (!strcmp(buf, "stat")) { thread_resume(stat_tid); thread_resume(stat_tid);
CuRT_v1/app/shell/main.c CuRT_v1/app/shell/main.c
85
SerialDriverinCuRT
void SerialInit(void) void SerialInit(void) { { /* GP39, GP40, GP41 UART(10) */ /* GP39, GP40, GP41 UART(10) */ GAFR1_L |= 0x000A8000; GAFR1_L |= 0x000A8000; GPDR1 |= 0x00000380; GPDR1 |= 0x00000380; /* 8-bit, 1 stop, no parity */ /* 8-bit, 1 stop, no parity */ rFFLCR = 0x00000003; rFFLCR = 0x00000003; /* Reset tx, rx FIFO. clear. FIFO enable */ /* Reset tx, rx FIFO. clear. FIFO enable */ rFFFCR = 0x00000007; rFFFCR = 0x00000007; /* UART Enable Interrupt */ /* UART Enable Interrupt */ rFFIER = 0x00000040; rFFIER = 0x00000040;
CuRT_v1/device/serial.c CuRT_v1/device/serial.c
FF_UART
XScale Core
ar e h p r e P i
PXA255 FF_UART (Full Function UART)

86
SerialDriverinCuRT
void SerialOutputByte(const char c) { void SerialOutputByte(const char c) { /* FIFO : wait for ready */ /* FIFO : wait for ready */ while ((rFFLSR & 0x00000020) == 0 ) while ((rFFLSR & 0x00000020) == 0 ) /* wait */; /* wait */; rFFTHR = ((ulong) c & 0xFF); rFFTHR = ((ulong) c & 0xFF); if (c == '\n') if (c == '\n') SerialOutputByte('\r'); SerialOutputByte('\r'); } } int SerialInputByte(char *c) { int SerialInputByte(char *c) { /* FIFO */ /* FIFO */ if ((rFFLSR & 0x00000001) == 0) { if ((rFFLSR & 0x00000001) == 0) { return 0; return 0; } } else { else { *(volatile char *) c = (char) rFFRBR; *(volatile char *) c = (char) rFFRBR; return 1; return 1; } } } }
CuRT_v1/device/serial.c CuRT_v1/device/serial.c
/** Full Function UART */ /** Full Function UART */ #define FFUART_BASE 0x40100000 #define FFUART_BASE 0x40100000 #define rFFTHR (*((volatile #define rFFTHR (*((volatile #define rFFLSR (*((volatile #define rFFLSR (*((volatile
CuRT_v1/includes/arch/arm/mach-pxa/pxa255.h CuRT_v1/includes/arch/arm/mach-pxa/pxa255.h ulong ulong ulong ulong *)(FFUART_BASE+0x00))) *)(FFUART_BASE+0x00))) *)(FFUART_BASE+0x14))) *)(FFUART_BASE+0x14)))
87
(qemu) print0x40100000+0x00 0x40100000 (qemu) x/1d0x40100000 0x40100000: 0 (qemu) x/1d0x40100000 0x40100000: 65

CuRT_v1/includes/arch/arm/mach-pxa/pxa255.h CuRT_v1/includes/arch/arm/mach-pxa/pxa255.h /** Full Function UART */ /** Full Function UART */ #define FFUART_BASE 0x40100000 #define FFUART_BASE 0x40100000 #define rFFTHR (*((volatile ulong *)(FFUART_BASE+0x00))) #define rFFTHR (*((volatile ulong *)(FFUART_BASE+0x00))) #define rFFLSR (*((volatile ulong *)(FFUART_BASE+0x14))) #define rFFLSR (*((volatile ulong *)(FFUART_BASE+0x14)))
CuRT serial 'A'
A = 0x41 = 65
CuRT serial driver is disabled

88
CuRT serial FIFOBuffer gdb 'c' CuRT
a = 0x61 = 97
89
PartI
ARM Architectureversionvs.Implementation ISAfeature ARMSoC
IC

90
PartII
ARM PXA255SoC CuRT ARMInterrupt,ISR,Exception PSR
91
Part II
92

ARM Limited ARM Architecture Reference Manual, Addison Wesley, June 2000 ARM Architecture Manual TrevorMartinTheInsidersGuideToThePhilipsARM7Based Microcontrollers,Hitex(UK)Ltd.,February2005 SteveFurberARMSystemOnChipArchitecture(2nd edition), AddisonWesley,March2000 IntelXscaleProgrammersReferenceManual CortexA8TechnicalReferenceManual TheDefinitiveGuidetotheARMCortexM3,JosephYiu
93

Arm 1 Overview 090720075211 Phpapp01

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ARM SoC

ARM ARM ARM

Most of the above devides are powered by ARM.

( BBCMicro ) AcornComputers Atommicrocomputer Proton 2MHzMOSTechnology6502CPU 1982 Sinclair ZXSpectrum Acrom

Application Note Core Type &

ARM (IP) ARM

byte3 byte2 byte1 byte0 bit0 bigendian bit31

byte3 byte2 byte1 byte0

byte address byte0 byte1 byte2 byte3

Allinstructionsare executedasARM Decompressorconverts ThumbtoequivalentARM instruction Decompressorpresentin thedecodestageofthe pipeline.

ARM 16 coprocessor Xscale coprocessor0 coprocessor1 Xscalecoprocessorinstructions Coprocessordatatransfers Coprocessordataoperations Coprocessorregisterloadandstore

Alias,samephysicalstructure 64bit D0.U8 Q0.F32

vadd.I16 D0, D1, D2 D1 D2

vmul.I32.S16 Q0, D2, D3 D2 D3

vshr.I16.I32 D0, Q1, #5 128b Q1

>> >> >> >>

NEONLoadorstore1elementor2,3,4elelmentstructure Handlecomplexnumber,coordinates,etc. EasyAoStoSoA

No data swizzling needed! Fewer instruction, higher performance

MPEG4 GSMAMR MP3Decoder

275 MHz 9.8 MHz 300 MHz 350 MHz

RF/Analog: Rx/Tx, Zero IF

SmartCard: SIM SIP/MCP FlashMemory: Code/Data Storage

Applications (GVM, Wavelet, M-Commerce, LBS..)

Radio Comm. Interface

I/O Device Driver (HW Abstraction Layer)

On-Chip RAM AHB/ASB Bridge

A typical AMBA system

** AMBA: Advanced Microcontroller Bus Architecture

ARM ARM ARM ARMSoC

/ ARM instructionleveltracer gdbserver AndroidSDK/Emulator goldfish

Serial / JTAG / TCP-IP

instructionsets+processor+peripherals x86, x86_64, ppc, arm, sparc, mips, nds( ) qemusystemarmM?

Processor armv5te (Xscale) 53

(Host) Qemu GDB 0xlabconnectyourdevicetoapplicationhttp://0xlab.org/

localhost:1234 (Host) GDB

[PLAN] CuRT PXA255(emulatedbyQEMU) gdbstub TCP/IP host Remotedebugging

wait gdb connection to port 1234.

CodeSourcery GNU Toolchain 2009q1 /usr/local/csl X $PATH

( QEMU CtrlAlt2 QEMUmonitor )

qemu remotegdb cgdb qemu 'c'

(qemu) inforegisters R00=00000000R01=00000020R02=00000020R03=00000000 R04=04040404R05=05050505R06=06060606R07=07070707 R08=08080808R09=09090909R10=10101010R11=a000c438 R12=12121212R13=a000c42cR14=a0001828R15=a0000bbc PSR=60000013ZCAsvc32

r0 r8 r1 r9 r2 r10 r3 r11 r4 r12 r5 r13 ARM Registers r6 r14 r7 r15(PC) 0xlabconnectyourdevicetoapplicationhttp://0xlab.org/

r0 r8 r1 r9 r2 r10 r3 r11 r4 r12 r5 r13 ARM r6 r15(PC) r14 Regs r7 0xlabconnectyourdevicetoapplicationhttp://0xlab.org/

enteredonresetandwhenaSoftwareInterrupt instructionexecuted. Abort(abt)ImplementsVMand/ormemoryprotection Undefined(und)SupportsoftwareemulationofHW coprocessors System:sysRunprivilegedOStasks

fiq, irq, svc, abt, und exception modes

r8 r9 r10 r11 r12 r13 r14 r15(PC)

231 1+1=231 : NZCV=0101.

Banked out Registers Banked out Registers

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

Thumb state Low registers

Thumb state High registers

Note: System mode uses the User mode register set 66

interrupts "F Ibit 1

interrupt FIQ32_moderegisters IRQ32_moderegisters

Task IRQ FIQ

Oninterrupt,theprocessorwillsetthe correspondinginterruptbitintheCPSRto disablesubsequentinterruptsofthe sametypefromoccurring. However,interruptsofahigherpriority canstilloccur.

Interrupt Second Interrupt

Oninterrupt,theprocessorwillsetthe correspondinginterruptbitintheCPSRto disablesubsequentinterruptsofthe sametypefromoccurring. However,interruptsofahigherpriority canstilloccur.

Task IRQ FIQ

FIQ IRQ (Reserved) Data Abort Prefetch Abort