2/13/2012

1
Small-signal Analysis
EE 21 Fundamentals of Electronics
1
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

AC Small-signal analysis
DC Analysis serves to establish the Q-point of
the network
The signal fed into an amplifier is AC
Transistor network amplifies AC signal
accordingly
Actually, signal has AC and DC components,
but we treat signal as AC only
Small signal analysis: considers only small
fluctuations / oscillations
2
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
2
Two-port system
Two pairs of terminals; one pair for input and
one pair for output




For CE configuration: input terminals are base
& emitter, output terminals are collector &
emitter (note the common-emitter)


3
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

The four important parameters
Measured at the terminals of the two-port
system being considered (that is, the amplifier
configuration only; external source and load
impedances are NOT included)

Input impedance, Zi
Output impedance, Zo
Voltage gain, Av
Current gain, Ai

4
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
3
Input impedance
Impedance seen AT the input terminals
Determines how much of the signal reaches
the amplifier configuration






*Rs is a source resistance (or measuring equipment resistance)


5
i
i
i
I
V
Z =
S
i S
i
R
V V
I

=
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Output Impedance
Impedance at the output terminals with applied
input signal set to 0.
Determines how much current reaches the load




6
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

S
O
i
R
V V
I

=
O
O
O
I
V
Z =
2/13/2012
4
Voltage gain
Ratio of output to input voltage; measure of
amplification
No-load voltage gain: amplifier network only


Voltage gain with respect to the source:

7
i
O
NL
V
V
Av =
|
|
.
|

\
|
|
|
.
|

\
|
= =
i
O
S
i
S
O
S
V
V
V
V
V
V
Av
Attenuation Factor
(for presence of source
Resistance)
No-load voltage gain
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Current Gain
Ratio of output to input current





8
L i
i O
i i
L O
i
O
i
R V
Z V
Z V
R V
I
I
A

=

= =
/
/
|
|
.
|

\
|
=
L
i
NL i
R
Z
Av A
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
5
Bipolar Junction Transistor Models
T-model
(hybrid-) model
H-model (r
e
model)

Discuss several models; networks will be analyzed
using a combination of the three models; focus on
CE configuration

Assume large enough r
o
(output impedance of the
transistor); r
o
is taken as the slope of the
transistors output characteristics

9
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

T-model








Recall the AC resistance of a diode:
10
R
IN
R
IN
I
B
D
I
mV
r
26
=
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
6
T-model
With equivalent diode resistance:
Input resistance/impedance:






(gm transconductance factor)
(r
e
transfer resistance factor)






11
R
IN
b
e e
B
be
IN
i
r i
I
V
R = =
( ) 1 +
=
|
e
b
i
i
( )
e IN
r R 1 + = |
m
e
g
r
1
=
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Transconductance
Trans involves a transfer/relationship
between input and output terminals

Conductance quotient of I/V; inverse of
resistance

Other terms such as transfer resistance or
transimpedance follow in the same manner
12
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
7
-model
13
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

-model
14
t
r I V
b be
=
( )
e e in
r r r Z | |
t
= + = = 1
t
r
V
I
be
B
=
Z
IN
m
e
g
r
1
=
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
8
-model
15
Z
IN
| |
m be
e
be
B
g V
r
V
I = =
|
|
.
|

\
|
= =
|
| |
m be
B C
g V
I I
m be C
g V I =
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

H-model (r
e
model)
h
ie
=

Combines the T and
pi models
Involves 4 hybrid
parameters:
h
i
-input resistance
h
o
-output
conductance
h
r
-reverse transfer
voltage ratio
h
f
-forward transfer
current ratio


16
h
fe
I
B
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
9
Relationships between models
One must be comfortable switching between
transistor models

17
e ie
r r h |
t
= =
Q
E
e
I
mV
r
26
=
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

| =
fe
h
AC Analysis of BJT CE
Networks
DC analysis is first performed to determine
emitter current for r
e
(The equations


will be frequently used instead of the assumption I
C
= I
E
AC analysis involves:
Remove DC sources and short out coupling capacitors at
the input and output
Relocate resistances according to their connections
(input and output side)
Bypass capacitors are replaced with shorts (assume
working at critical frequencies)
18
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

( )
B E
I I 1 + = | B E
I I
|
|
.
|

\
| +
=
|
| 1
2/13/2012
10
BJT Fixed Bias
19
AC analysis is started by removing the DC components and
replacing capacitors with short equivalents
Removal of components allows us to relocate R
B
and R
C


E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

BJT Fixed Bias: AC Equivalent
20
Note that Vi is the input signal to the network; right
after the capacitor.
r
o
can be assumed large enough to permit the parallel
combination r
o
//Rc Rc.

E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
11
BJT Fixed Bias: AC Analysis
Input impedance:



Output impedance:


21
ie B i
e B i
h R Z
r R Z
//
//
=
= |
C C o o
R R r Z ~ = //
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

BJT Fixed Bias: AC Analysis
Voltage gain, Av:







22
e
i
b
r
V
I
|
=
( )
o C b O
r R I V || | =
( )
o C
e
i
O
r R
r
V
V ||
|
|
.
|

\
|
=
|
|
( )
e
o C
i
O
r
r R
V
V
Av
||
= =
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
12
BJT Fixed Bias: AC Analysis
Current Gain, Ai:

23
( )( )
e B C o
o B
i
O
i
r R R r
r R
I
I
A
|
|
+ +
= =
( )
|
|
.
|

\
|
+
=
C o
o
b O
R r
r
I I |
|
|
.
|

\
|
+
=
e B
B
i b
r R
R
I I
|
|
|
.
|

\
|
=
C
i
NL i
R
Z
Av A
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

( )
|
|
|
~
+
= =
e B
B
i
O
i
r R
R
I
I
A
Example: Fixed-bias circuit
In the fixed-bias circuit, determine:
r
e
Zi, Zo, Av, Ai
Repeat the solution with r
o
negligible.
24
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
13
Emitter-Stabilized Bias
Two cases:
Bypassed R
E
Unbypassed R
E

25
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Emitter Stabilized Bias:
AC Equivalent Circuit - Bypassed
Bypass capacitor shorts out emitter resistance;
thus equivalent circuit (and corresponding
quantities) is the same with the fixed bias
circuit.
26
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
14
Unbypassed emitter resistance
27
*Analysis of unbypassed circuit assumes negligible r
o
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Unbypassed emitter resistance
28
*Reflected resistance shows Re in the input circuit and
only R
E
in the output side of the circuit

Note: h
ie
= r
e
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
15
Unbypassed R
E
Input impedance:



Alternatively we can label

Output impedance: (negligible r
o
)

29
( ) ( )
( ) ( )
E ie B i
E e B i
R h R Z
R r R Z
|
| |
+ =
+ =
||
||
C o
R Z =
( )
E e b
R r Z | | + =
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Unbypassed R
E

Voltage gain



30
C b C O O
R I R I V | = =
( )
E e
i
b
R r
V
I
+
=
|
( )
C
E e
i
O
R
R r
V
V
|
|
.
|

\
|
+
=
|
|
b
C
E e
C
v
Z
R
R r
R
A
|
=
+
=
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
16
Unbypassed R
E
Current Gain: using Z
b
=(r
e
+R
E
)

31
b B
B
i b
Z R
R
I I
+
=
B O
I I | =
|
|
.
|

\
|
+
=
b B
B
i O
Z R
R
I I |
b B
B
i
Z R
R
A
+
=
|
|
|
.
|

\
|
=
C
i
NL i
R
Z
Av A
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

DC significance of emitter resistance and
AC significance of bypass capacitor
DC analysis: the emitter resistance is added to
improve the stability of the transistor amplifier; i.e.
less sensitive to temperature

The bypass capacitor is open during AC analysis

AC analysis: presence of emitter resistance reduces
voltage (significantly) and current gain

Bypass capacitor shorts out the emitter resistance,
hence increasing the amplifiers voltage and current
gain
32
2/13/2012
17
Example: Emitter-Stabilized Bias
Determine:
(a) Zi and Zo
(b) Av
(c) Ai
(d) Repeat a,b, and c
without including
r
o
and the bypass
capacitor.

33
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

BJT Voltage Divider
We will first consider
only a voltage divider
network with a
bypassed emitter
resistance
Note: if r
o
is given, it can
be ignored if the
following condition is
met:



34
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

C O
R r 10 >
2/13/2012
18
BJT Voltage Divider:
AC Equivalent circuit (Bypassed R
E
)


35
Note that the significant difference is simply the presence of
an additional resistance at the input.

E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

BJT Voltage Divider:
AC Analysis (Bypassed R
E
)


Input impedance:


Output impedance:

36
( )
e i
r R R Z | || ||
2 1
=
( )
C o C O
R r R Z ~ = ||
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
19
BJT Voltage Divider:
AC Analysis (Bypassed R
E
)

Voltage gain



Current gain: Let R = R
1
||R
2
and applying CDR:





The right equation is used when r
o
can be ignored.

37
e
o C
v
r
r R
A
||
=
( )( )
e e C o
o
i
r R
R
r R R r
r R
A
|
|
|
|
+
~
+ +
=
'
'
'
'
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Unbypassed Emitter Resistance
(r
o
disregarded)
38
Note: h
ie
= r
e
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
20
Unbypassed Emitter Resistance
(r
o
disregarded)
Input impedance



Output impedance:



39
( ) ( )
( )
b i
E e i
Z R Z
R r R R Z
|| '
|| ||
2 1
=
+ = | |
C O
R Z =
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Unbypassed Emitter Resistance
(r
o
disregarded)
Voltage Gain

40
C b O
R I V | =
( )
E e
i
b
i
b
R r
V
Z
V
I
+
= =
|
( )
C
E e
i
O
R
R r
V
V
|
|
.
|

\
|
+
=
|
|
( )
E e
C
v
R r
R
A
+
=
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
21
Unbypassed Emitter Resistance
(r
o
disregarded)
Current Gain
41
b O
I I | =
( )
( ) ( )
E e
i
b
i b
R r R R
R R
I
Z R
R
I I
+ +
=
+
=
|
2 1
2 1
||
||
'
'
( )
( ) ( )
b E e
i
Z R
R
R r R R
R R
A
+
=
+ +
=
'
'
||
||
2 1
2 1
|
|
|
|
|
.
|

\
|
=
C
i
NL i
R
Z
Av A
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Example: Voltage Divider Bias
Ignoring r
o
, determine
the input and output
impedances as well as
the voltage and
current gains of the
voltage divider
network. Repeat
without the bypass
capacitor.
42
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
22
Field Effect Transistor Model
Recall: FET is a voltage-controlled device with
a very high input impedance
Transconductance: shows relationship
between change in collector current
corresponding to a change in gate-to-source
voltage:




43
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

gs m d
V g I A = A
gs
d
m
V
I
g
A
A
=
Graphical interpretation
44
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
23
Mathematical determination of g
m
Derivative: slope of the tangent line at a point

45
. . pt Q
gs
d
pt Q
gs
d
m
dV
dI
V
I
g

=
A
A
=
(
(

|
|
.
|

\
|
=
2
1
p
gs
DSS
gs
V
V
I
dV
d
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Mathematical determination of g
m







46
|
|
.
|

\
|

|
|
.
|

\
|
=
|
|
.
|

\
|
=
P
GS
GS P
GS
DSS
P
GS
GS
DSS
V
V
dV
d
V
V
I
V
V
dV
d
I 1 1 2 1
2
|
|
.
|

\
|

|
|
.
|

\
|
=
P P
GS
DSS
V V
V
I
1
0 1 2
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
24
Mathematical determination of g
m







47
|
|
.
|

\
|

|
|
.
|

\
|
=
|
|
.
|

\
|
=
P
GS
GS P
GS
DSS
P
GS
GS
DSS
V
V
dV
d
V
V
I
V
V
dV
d
I 1 1 2 1
2
|
|
.
|

\
|

|
|
.
|

\
|
=
P P
GS
DSS
V V
V
I
1
0 1 2
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Mathematical determination of g
m

Manipulating the previous equation to yield
only positive values of g
m
:



Maximum slope occurs when V
GS
= 0, thus:

48
|
|
.
|

\
|
=
P
GS
P
DSS
m
V
V
V
I
g 1
2
P
DSS
P P
DSS
m
V
I
V V
I
g
2 0
1
2
0
=
|
|
.
|

\
|
=
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
25
Mathematical determination of g
m
The equation for transconductance can thus be
simplified to:



Where



Specification sheets often use notation y
fs

DC analysis is required to obtain g
m
at Q-point.
49
|
|
.
|

\
|
=
P
GS
m m
V
V
g g 1
0
P
DSS
m
V
I
g
2
0
=
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

FET AC Equivalent circuit
g
m
: amplification factor ( in BJTs)
r
d
: FET output impedance
Measured using output characteristics
Specification sheets use label y
os
and r
d
is taken as
inverse
50
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
26
FET AC Equivalent Circuit
Removing r
d
yields a much manageble
equivalent circuit:
51
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

AC Analysis of FET networks
DC analysis is performed to determine Q-point
location, also for transconductance value (V
GSQ
is
required in the equation for g
m
)

AC analysis similar to BJT (relocation of resistances,
determining of input and output impedances, etc)

Equivalent circuits presented will include r
d
as a
general illustration; can later be ignored

Only gain considered in FET networks is voltage gain;
current gain is undefined (why?)

52
2/13/2012
27
FET Fixed Bias
53
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

FET Fixed Bias: AC equivalent
54
Note the defined polarity of V
gs
as it appears on the usual
configuration. If V
gs
becomes negative, the current source
changes direction as well.
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
28
FET Fixed Bias: AC Analysis
Input impedance:


Output impedance:


55
G i
R Z =
( )
D D d O
R R r Z ~ = ||
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

FET Fixed Bias: AC Analysis
Voltage gain

56
( )
D d gs m O
R r V g V || =
i gs
V V =
( )
D d i m O
R r V g V || =
( )
D m D d m v
R g R r g A ~ = ||
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
29
Example: JFET Fixed Bias
For the JFET fixed bias
circuit, determine the
following:
g
m

Z
i
and Z
o

Voltage gain, A
v

57
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

FET Self-bias
Will be analyzed with
and without bypass
capacitor

For unbypassed, r
d
will
be removed (including
r
d
is left as a reading
assignment)
58
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
30
FET Self-bias: bypassed R
S
Equivalent network with the source resistance
bypassed by capacitor yields same equivalent
circuit as that of the fixed bias circuit (thus with
the same Zi, Zo, and Av)
59
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Unbypassed R
S
(r
d
removed)

60
Input impedance:
G i
R Z =
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
31
Unbypassed R
S
(r
d
removed)
For output impedance, consider the circuit
below, with V
i
set to 0:
61
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Unbypassed R
S
(r
d
removed)
Applying KCL:

62
O D gs m
I I V g + =
S D O gs
R I I V ) ( + =
( )
S D m S O m S D O m D O
R I g R I g R I I g I I = + = + ) (
( ) ( )
S m D S m O
R g I R g I + = + 1 1
D O
I I =
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
32
Unbypassed R
S
(r
d
removed)
The output voltage is calculated as:


The output impedance is defined by:




63
O
O
O
I
V
Z =
D O D D O
R I R I V = =
D O
O
D O
O
R Z
I
R I
Z
=
=
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Unbypassed R
S
(r
d
removed)
For the voltage gain:

64
0 =
Rs GS i
V V V
S D i GS
R I V V =
gs m D
V g I =
S gs m i GS
R V g V V =
( )
S m gs i
S gs m gs i
R g V V
R V g V V
+ =
+ =
1
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
33
Unbypassed R
S
(r
d
removed)
Manipulating Vi and V
gs
:





65
S m
i
gs
R g
V
V
+
=
1
D gs m R O
R V g V V
D
= =
D
S m
i
m
R
R g
V
g
|
|
.
|

\
|
+
=
1
S m
D m
i
O
v
R g
R g
V
V
A
+
= =
1
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Example: FET Self-bias
Determine the
following:
(a) g
m

(b) Zi and Zo
(c) Av
(d) Output voltage if V
in
is
a sinusoidal 10mV.
66
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
34
FET Voltage Divider
Consider only the
bypassed source
resistance case
67
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

FET Voltage divider AC equivalent
68
Only difference from fixed-bias circuit is the input
impedance Zi:

( )
2 1
|| R R Z
i
=
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
35
Systems Approach:
Effects of source and load impedance
Previous examples were solved using circuit analysis
of corresponding transistor models; all gains were no-
load gains

Two-port system provides alternate solution to the
same problem

Solution varies slightly; two-port model is effective in
inspecting effects of source and load impedance,
which arent parts of the amplifier network
69
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2-port system model for
transistor (both BJT and JFET)
Recall: Two-port system:



Applying Thevenins theorem to the output side of the
circuit yields the following:



, thus,



70
O TH
Z Z =
i
O
NL
v
V
V
A = i vNL O TH
V A V E = =
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
36
Two-port equivalent circuit
Substituting the TEC yields the following circuit:







This is the two-port model for any transistor amplifier
network (the values used are Zi, Zo, and Av
NL
, which
we know how to solve for)

71
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Effect of load impedance R
L
Load impedance has an effect on AC analysisusing two
port model:

72
Ii Io
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
37
Effect of load impedance, R
L
Applying VDR:


73
Ii Io
|
|
.
|

\
|
+
=
L O
L
i NL v O
R Z
R
V A V
|
|
.
|

\
|
+
=
L O
L
NL v v
R Z
R
A A
In general:
As the load resistance R
L

increases, the voltage gain
increases.

E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Effect of load impedance R
L
Input impedance is not affected by R
L

However, the transistor 2-port system still provides
the following equations:






Where Av is the loaded voltage gain, Zi and Zo are
parameters of the network, and R
L
the load impedance

74
i
i
i
i
i
R
V
Z
V
I = =
O
O
O
O
O
R
V
Z
V
I =

=
L
i
v i
R
Z
A A =
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
38
Example: Effect of R
L

Determine the voltage and current gain for the
fixed-bias transistor amplifier using the two-port
model and the circuit analysis done previously.
Compare the obtained values.
75
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

The AC load line
Recall that in DC analysis a load line was drawn in a
graph of the output characteristics

Load resistance R
L
doesnt contribute since it is
isolated by a coupling capacitor

The AC load line incorporates the load resistance R
L
,
which is parallel to the collector resistance, that is:

76
L C L
R R R || ' =
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
39
T
h
e

A
C

a
n
d

D
C

l
o
a
d

l
i
n
e


77
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Effect of signal source
resistance R
S
Not to be confused with FET source resistance, which
has the same label (most books also use Rs)





Source resistance affects how much of the source
signal reaches amplifier inputs; Rs may also come
from bleeder resistors aside from signal sources

78
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
40
Effect of source resistance R
S

By inspection,






The voltage gain
is thus altered as:

79
i vNL O
V A V =
i S
i
S i
Z R
Z
V V
+
=
|
|
.
|

\
|
+
= =
S i
i
vNL
S
O
vS
R Z
Z
A
V
V
A
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Effect of source resistance R
S

In addition, the input current is also altered
since there is an additional resistor in series:



Note: the parameters Z
i
and A
vNL
of a two-port
system are unaffected by the internal
resistance Rs. These are parameters of the
transistor amplifier, which doesnt see Rs.

80
S i
i
i
R Z
V
I
+
=
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
41
Example: Effect of R
S

Consider the previous example, this time removing R
L

and assuming a source internal resistance of 500 ohms.
a. Determine the voltage gain Av
s
. Use the previously
solved quantities of the transistor amplifier network.
b. What percent of the applied signal appears at the
input terminals of the amplifier?
c. Determine the voltage gain Av
s
using the H/r
e
model.
81
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Combined effect of R
L
and R
S







Note: the load and source impedances do not change the
parameters of the transistor amplifier network (esp. using
two-port analysis) but they are included in the entire
circuit analysis (if solution using H-model is to be
implemented).
82
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
42
Combined effect of R
L
and R
S

At the input side:



At the output side: (where Ro = Zo)


83
S i
i
S i
R Z
Z
V V
+
=
O L
L
vNL O
Z R
R
A V
+
=
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Combined effect of R
L
and R
S

For the total voltage gain, Av
S
:

84
|
|
.
|

\
|
|
|
.
|

\
|
= =
S
i
i
O
S
O
vS
V
V
V
V
V
V
A
|
|
.
|

\
|
+
|
|
.
|

\
|
+
= =
S i
i
O L
L
vNL
S
O
vS
R Z
Z
Z R
R
A
V
V
A
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
43
Combined effect of R
L
and R
S

The current gain can be solved using two equations:

, where





Where A
vS
is the total voltage gain (including the effects
of both source and load resistances)


85
L
i
v i
R
Z
A A =
L O
L
vNL
i
O
v
R Z
R
A
V
V
A
+
= =
L
S i
vS
S
i
R
R Z
A A
+
=
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Example: Combined effects of
Rs and R
L
86
For the fixed-bias circuit, determine the total voltage gain
A
vS
, loaded voltage gain A
v
= Vo/Vi, and the total current
gain Ai using both formulas. The solved parameters of the
transistor amplifier are as follows: Z
i
= 1.071k, Zo=3k,
and Av
NL
= -280.11

E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
44
Generalizations of R
S
and R
L
effects
R
S
and R
L
effects can easily be extended to the
analysis of the other networks

R
S
affects the voltage input, Vi, by voltage
division; it also affects the input current, Ii, by
increasing the series resistance

R
L
adds a parallel resistance to the output side;
it affects the voltage and current gains of the
transistor amplifier

87
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Example: FET network
Determine the voltage gain of the FET voltage divider
network. The transconductance is given as 2.2 mS.
88
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
45
Cascaded Systems
Consists of transistor amplifier networks connected to
each other





Input impedance to succeeding network acts as the
load impedance to the previous network when
computing for its loaded gain A
v
, similar to effects of R
L

Note that effects of source resistance are applied as
necessary
89
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Cascaded Systems
Av
1
, Av
2
, Av
N
are all loaded gains Vi/Vo of each
individually analyzed network
Total voltage gain:



Where

90
vN v v v vT
A A A A A
3 2 1
=
( ) 1
,

= =
k O k i
k i
Ok
k
V V
V
V
Av
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
46
Cascaded Systems
Total current gain:



If source resistance is present, previous equation can
be applied:
91
L
i
vT iT
R
Z
A A
1
=
L
S i
S vT
S T
i
R
R Z
A A
+
=
) (
) (
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

Decibel representation of gains
Voltage gains can be represented in decibels:




The total gain (in decibels) is the algebraic sum of
individual decibel gains:







92
|
|
.
|

\
|
= =
i
O
v dB v
V
V
A A log 20 log 20
) (
) ( ) ( 3 ) ( 2 ) ( 1 ) ( dB vN dB v dB v dB v dB vT
A A A A A + + + + =
E
E

2
1

S
l
i
d
e
s

(
A
A
M
S
)

2/13/2012
47
Example 1. Determine the total voltage and current
gains of the BJT-BJT cascaded amplifier.
93
Example 1. Determine the total voltage gain of the
FET-BJT cascaded amplifier. Repeat with the load
resistance R
L
.
94