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Core of the embedded system

Core of the embedded system


Embedded systems are domain and application specific and are built around a central core. The core of the embedded system fall into any one of the following categories: General purpose and domain specific processors Micro-processors Micro-controllers Digital signal processors Application specific integrated circuits (ASIC) Programmable logic devices (PLD) Commercial off the shelf components (COTS)

General purpose and domain specific processors


Almost 80% of the embedded systems are micro controller/ microprocessor based.

Microprocessor 1971 - intel 4004 4 bit processor 16, 4bit GPR Clock 740kHz 46 instructions 1K DM, 4K PM, 12 bit PC Designed for old days calculators.

1972 1972 1974

- 4040 14 more instructions added to 4004 8K PM Interrupt capabilities added to it. - 8008 14 bit PC - 8080 8 bit microprocessor 16 bit address bus 16 bit PC 7, 8 bit registers Commonly used in industrial control & other embedded applications. Motorola 6800 - different architecture & instruction set compared to 8080.

1976 - 8085 2 newly added instructions 3 interrupt pins Serial i/o Clock generator (built in) Bus controller circuits (built in) Power supply part modified to single +5 supply 1976 - Zilog entered the microprocessor market (Z80) It is an improved version of 8080 80 more instructions 8 bit data bus, 16 bit add. Bus. Brought out the concept of register banking.

Then 16, 32, 64 bit processors come into the place of 8 bit microprocessor. The initial 2MHz clock is now GHz range. Intel, AMD, Freescale, IBM, TI, Cyrix, Hitachi etc.. Different instruction set and system architecture are available for microprocessor design. Harvard and von-neuman CISC and RISC

General purpose (GPP) vs Application specific instruction set processors (ASIP)


GPP Designed for general computational tasks Contains ALU, CU ASIP Architecture & instruction set optimized to specific application Most of the emb- s/m are built around ASIP Some microcontrollers are examples of ASIP Incorporate a processor & on chip peripherals demanded by the app.

micro-controller
Highly integrated chip that contains CPU SFR, GPR RAM, ROM / FLASH Timers Interrupt control unit Dedicated i/o ports Cheap, cost effective, readily available in market

1974 - TI's TMS 1000 known as the 1st micro-controller TI followed the Intel's 4004/4040 design And added some RAM, ROM & i/o support on a single chip. 1977 - Intel - MCS48 family 8038HL, 8039HL, 8040AHL, 8048H, 8049H,8050AH 8048 Intel's 1st micro-controller Used in the IBM-PC keyboards Harvard architecture

1980 - MCS51 Intel's 8 bit micro-controller domain Almost 75% of the micro-controllers used in emb- domain uses 8051 family based controllers during 1980s to 1990s. 8051 processor core are used in more than 100 devices by more than 20 independent manufacturers, under the license from Intel. PIC family micro-controller From microchip technologies High performance RISC processor

Infineon, Freescale, Atmel, Maxim, Microchip etc.. are the key suppliers of 16 bit micro-controllers. Added more and more functionality like: SPI I2C USB ADC Networking capabilities etc.. ARM - high processing speed micro-controller families. The instruction set architecture of micro-controller can be RISC or CISC

Micro-processor
A silicon chip representing a CPU which es capable of performing arithmetic as well as logical operations. It is a dependent unit. It requires the combination of other chips. Most time, general purpose in design & operation Doesn't contain a built in i/o port. Targeted for high end market where performance is important. Limited power saving options compared to uc.

Micro-controller
It is a highly integrated chip that contains CPU, RAM, ROM, SFE, GPR, timers, int-control unit, I/O ports etc It is a self contained unit. Mostly application-oriented. Most of the processors contain multiple built-in i/o ports. Targeted for embedded market where performance is not so critical Includes lot of power saving features.

DSP
Powerful special purpose 8/16/32 bit micro-processor. Designed specifically to meet the computational demands & power constrains of today's embedded audio video & communications applications. DSP are 2 to 3 times faster than the general purpose microprocessor in s/l processing applications. This is because of the architectural diff- b/w the two. DSP implements algorithms in h/w which speeds up the execution. General purpose up- implements algorithms in firmware & speed of execution depends primarily on the clock for the processors. A typical DSP incorporates the following units: PM, DM, I/O units, computational engine.

RISC
Lesser no. of instructions Instruction pipe-lining & increased execution speed Orthogonal instruction set. Large no. of reg-s available. Operations are performed on reg- only. Programmer needs to write more code to execute a task since the instructions are simpler ones. Single fixed length inst-. Less silicon usage & pins. With Harvard architecture.

CISC
Greater no. of instructions. Generally no instruction pipelining feature. Non-orthogonal. Limited no. GPR. Operations are performed on reg- or memory dependent on the instruction. Programmer can achieve the desired functionality with a single instruction. Variable length instructions. More silicon usage since more additional decoder logic is required. Harvard or von-neuman.

Harvard
Separate buses for inst- & data fetching. Easier to pipe-lining . So high performance can be achieved. Comparatively high cost. No memory alignment problem. Since DM & PM are stored physically in diff- locations, no chance for accidental corruption of PM.

Von-neuman
Single shared bus. Low performance while compared to Harvard arch-. Cheaper Allows self modifying codes. Chance for accidental corruption of PM.

Big Endian vs Little Endian


Endiannes specifies the order in which the data is stored in the memory by processor operations in a multi-byte s/m. Little Endian: The lower order byte of the data is stored in memory at the lower address & the higher order byte at the highest address. Big Endian: The higher order byte of the data is stored in memory at the lower address & the lower order byte at the higher address.

Instruction pipe-lining

Application specific integrated circuits (ASIC)


A microchip designed to perform a specific or unique application. It is used as replacement to conventional general purpose logic chips. It integrates several fun-s to a single chip & there by reduces the s/m development cost. Consumes a very small area. ASIC can be pre-fabricated for a special application or it can be custom fabricated. Profitable only for large volume commercial production.

Programmable logic devices


Logic devices provide specific functions. Logic devices can be classified into 2 categories: Fixed & programmable Fixed logic devices are permanent They perform one function or set of functions. Once manufactured they can't be changed. Programmable logic devices offer: Customize a wide range of logic capacity, features, speed & voltage characterizes & these devices can be re-configured to perform any no. of function at any time.

CPLD & FPGA


2 major type of PLD s. FPGA offer the highest amount of logic density, the most features & the highest performance. used in a wide variety of application ranging from data processing & storage to instrumentation, telecommunication & DSP. CPLD offer much smaller amounts of logic, up to about 10000 gates. offer very predictable timing characteristics & are therefore ideal for critical control applications.

Commercial off-the shelf components (COTS)


COTS product are designed in such a way to provide easy integration & interoperability with existing system components. The COTS components itself may be developed around a general purpose or domain specific processor or an ASIC or PLD. The major problem faced by end user is that there are no operational & manufacturing standards.

Memory

Memory Type of memory interface Memory shadowing Memory selection for embedded system

Memory
On-chip memory External memory

ROM
FLASH NVRAM PROM (OTP) Masked ROM (MROM) EPROM EEPROM

MROM
One time programmable device Device factory programmed by masking & Metallization process at the time of production itself. Advantage Low cost (least expensive type) High volume production Different mechanisms used for the masking process: Creation of an enhancement or depletion mode transistor through channel impact. By creating the memory cell either using a standard transistor or a high threshold transistor.

PROM / OTP
One time programmable memory (OTP) or PROM. It is not pre-programmed by the manufacturer. The end user is responsible for programming the device. It has nichrome(nickel-chromium resistance wires) or polysilicon wires arranged in a matrix. These wires can be functionally viewed or fuses. It is programmed by a PROM programmer which selectively burns the fuses according to the bit pattern to be stored. The fuses which are not blown/burned represents a logic 1. So the default state is 1.

EPROM
OTPs are not useful & worth for development purpose. Flexibility to re-program the same chip. Stores the info- by changing the floating gate of an FET. Stored by using EPROM programmer which applies high voltage to charge the floating gate. EPROM contains quartz crystal window for erasing the stored information. If the window is exposed to UV ray for a fixed duration, the entire memory will be erased. (20 30 minutes)

EEPROM
Memory can be altered by sing electrical s/l at the register / byte level. These chips include a chip erase mode & in this mode they can be erased in a few ms. It provides greater flexibility for s/m design. Limitation: Capacity is limited when compared with the standard ROM

FLASH
Latest and most popular ROM technology. It is a version of EEPROM technology. It combines the re-programmablity of EEPROM & high capacity of standard ROM s. FLASH memory is organized as sectors (blocks) or pages. Stores info- in an array of floating gate MOSFET transistors. Erasing of memory can be done at sector/page level without affecting the other sector/page. Each sector/page should be erased before reprogramming Typical erasable capacity of FLASH is 1000 cycles.

NVRAM
It is a RAM with battery backup. It contains static RAM based memory & a minute battery for providing supply to the memory in the absence of external power supply. Memory & battery are packed together in a single package.

RAM
Data memory Working memory RAM is volatile RAM: SRAM DRAM NVRAM

SRAM

They are made up of flip-flops Fastest form of RAM. SRAM cell (bit) is realized using 6 transistors (MOSFET) 4 of the transistors are used for building FF part of the memory & 2 controlling the access. Limitation: Low capacity High cost

DRAM
Made up of a MOS transistor gate. Advantage: High density Low cost Disadvantage: Since the info- is stored as charge, it get leaked of with time & to prevent this they need to refreshed periodically. DRAM controllers are used for refreshing. Refresh operation is done periodically in ms interval MOSFET act as gate for incoming & outgoing data.

SRAM

DRAM

Made up of 6 CMOS transistors. Doesn't require refreshing. Low capacity. Fast in operation. Typical access time 10ns.

Made up of a MOSFET & a capacitor. Require refreshing. High capacity. Slow in operation, due to refreshing requirement. Typical access time 60ns.

NVRAM
Non-volatile RAM With battery backup.

Type of memory interface


Parallel interface Serial interface I2C SPI Serial interface commonly used in EEPROM Memory density of a serial memory is usually expressed in terms of kilo bits. For parallel interface memory is expressed in terms of kilobytes.

Memory shadowing
ROM access time is (120 200 ns) RAM access time is (40 70 ns)

Eg: Manufacturers included a RAM behind the logical layer of BIOS at its same address as a shadow to BIOS & the 1st step that happens during the boot up is copying the BIOS to the shadowed RAM & write protecting the RAM then disabling the BIOS reading.

Memory selection for embedded system


Embedded system require PM and DM. Factors need to be considered when selecting the type & size of memory for emb- s/m: Application (on-chip memory may be sufficient for designing the total s/m) s/m requirement is based on the type of processor For 8051 and PIC: For RTOS:

2 parameters for representing an memory Size of the memory Mem-chip comes with standard size 4Kb, 8Kb, 16Kb,32Kb etc. Address range supported by processor Word size of the memory no. of bits that can be read/write together 4, 8, 12, 16, 24, 32 etc. Word size should be matched for memory and processor.

FLASH FLASH is the popular choice for ROM in emb. s/m FLASH comes with 2 major versions NAND FLASH NOR FLASH NAND FLASH High density, Low cost Non-volatile Can be used for storing programs & data Dose not support XIP (execute in place) NOR FLASH Less density, Expensive It supports XIP technology. Can be used for storing boot-loader or for even complete program code.

EEPROM It comes with parallel or serial interface. If the controller/processor supports serial interface & the amount of data write and read to and from the device is less, it is better to have a serial EEPROM chip. Serial EEPROM is usually expressed in bits and kilo-bits (512 bits, 1 Kbits, 2 Kbits etc.)

Sensors And Actuators

Sensors And Actuators


Sensors A sensor is a transducer device that converts energy from one form to another for any measurement or control purpose. Actuators Actuator is a transducer device (mechanical or electrical) which converts signal to corresponding physical action (motion). I/O Subsystem The i/o subsystem of the embedded system facilitates the interaction of the embedded system with the external world.

LED 7 segment display Optocoupler Stepper motor Relay Piezo-buzzer Push button switch Keyboard PPI

LED
For visual indication in any embedded s/m. Eg: device ON, Battery low, Charging of battery. P-n junction diode (having anode & cathode).

7-Segment Display
An o/p device for displaying alpha numeric characters. It contains 8 LED segments arranged in a special form. In it 7 are used for displaying alpha numeric character & 1 for representing 'decimal point'.

Common anode Common cathode

Optocoupler
To isolate 2 parts of a circuit

Stepper Motor
Produces discrete rotation in response to the dc voltage applied to it. Based on the coil winding arrangement, it is classified in to: Unipolar
Contains 2 winding per phase. Direction of rotation is controlled by changing the direction of current flow. Contains 1 winding per phase. For reversing the motor rotation the current flow through the winding is reversed dynamically.

Bipolar

Stepping the stepper motor can be implemented in diffways by changing the sequence of activation of the stator windings Different stepping modes: Full step Both the phases are energized simultaneously. Wave step Only one phase is energized at a time & each coils of the phase is energized alternatively. Half step Combination of wave & full step. It has the highest torque and stability.

Rotation of the stepper motor can be reversed by reversing the order in which the coil is energized. 2 phase stepper motors are the popular choice for embedded applications. The current requirement for stepper motor is little high & hence the port pins of a micro-controller may not be able to drive them directly. Also supply voltage required to operate stepper motor varies. So depending on the current and voltage requirements, special driving circuits are required to interface the stepper motor with micro-controller. Eg: ULN2803, ULN2003 etc.

Relay
Relay Configurations : Single pole single throw normally open Single pole single throw normally closed Single pole double throw Free wheeling diode. Used to free-wheeling the voltage produced in the opposite direction, when the relay coil is deenergized.

Piezo Buzzer
For generating audio indications in embedded application. It contains a piezoelectric diaphragm which produces audible sound in response to the voltage applied to it. Available in two types: Self driving
Contains all the necessary components to generate sound in response to the voltage applied to it. It will generate a tone on applying the voltage. Supports the generation of diff- tones. Tones can be varied by applying a variable pulse train.

External driving

Push Button Switch


Switch : Push to make Push to break

Keyboard
Keyboards are organized in a matrix of rows and columns The CPU accesses both rows and columns through ports Therefore, with two 8-bit ports, an 8 x 8 matrix of keys can be connected to a microprocessor When a key is pressed, a row and a column make a contact. Otherwise, there is no connection between rows and columns

Programmable Peripheral Interface (PPI)


8255

PA0 - PA7 (8-bit port A) Can be programmed as all input or output, or all bits as bidirectional input/output PB0 - PB7 (8-bit port B) Can be programmed as all input or output, but cannot be used as a bidirectional port PC0 PC7 (8-bit port C) Can be all input or output Can also be split into two parts: CU (upper bits PC4 - PC7) CL (lower bits PC0 PC3) each can be used for input or output Any of bits PC0 to PC7 can be programmed individually

RD and WR
These two active-low control s/l s are inputs to the 8255 connected to the data pins of the microcontroller allowing it to send data back and forth between the controller and the 8255 chip An active-high signal input Used to clear the control register When RESET is activated, all ports are initialized as input ports CS is active-low. CS selects the entire chip, it is A0 and A1 that select specific ports These 3 pins are used to access port A, B, C, or the control register

D0 D7

RESET

A0, A1, and CS (chip select)


modes
Mode 0, simple I/O Any of the ports can be programmed as i/p or o/p All bits are out or all are in Mode 1 Port A and B can be used as input or output ports with handshaking capabilities Handshaking s/l s are provided by the bits of port C Mode 2 Port A can be used as a bidirectional I/O port with handshaking capabilities provided by port C Port B can be used either in mode 0 or mode 1 4. BSR (bit set/reset) mode Only the individual bits of port C can be programmed

BSR mode Bit set/reset, applicable to PC only. One bit is S/R at a time. Control word:

I/O mode

Communication Interface

Communication Interface
For communicating with various subsystems of the embedded system and with the external world. For an embedded product, the communication interface can be viewed in two different perspectives: device/board level communication interface (on-board communication interface) Product level communication interface

On-board communication interface


I2C
Developed by Philips Semiconductor in 1980 s. Synchronous bi-directional half duplex. 2 wire serial interface bus: SDA, SCL Master & Slave Both bus lines should be pulled up to the supply voltage. Address of the I2C devices assigned at the time of design.

3 different data rate: Standard mode: up to 100kbps Fast mode: up to 400kbps High speed mode: up to 3.4Mbps Sequence of operations for communicating with an I2C slave device are: 1. clock 2. start 3. address (MSB first) 4. R/W bit 5. wait for acknowledgment 6. slave giving acknowledgment 7. 8 bit data 8. acknowledgment 9. stop

SPI
Motorola Synchronous bi-directional full duplex 4 wire serial MOSI MISO SCLK SS (active low) Single-master multi-slave s/m.

Having configuration register for: master/slave selection Baud-rate selection Clock control LSB/MSB transmits first (configurable) Status register SPI works in the principle of shift-register. Size of the shift-register is device dependent Normally it is a multiple of 8

UART
Asynchronous No clock (baud-rate) LSB first Start bit Informs the receiver that a data byte is about to arrive. Data Stop bit Eg: 8250

1-wire interface
Asynchronous half-duplex Having single wire DQ Supports single master and multiple slave 1-wire device contain identifier Unique 64bit identifier no. stored within it. Used to address the device. Identifier has 3 parts. 8 bit family code. 48 bit serial no. 8 bit CRC command.

The sequence of operation for communication are: 1. master device sends a reset pulse on the bus. 2. slave device responds with presence pulse. 3. master sends a ROM command. (net add-command followed by the 64bit add- of the device) 4. master sends a read/write function command to read/write the internal memory of the device. The master initiates the read/write from/to the device

Communication over the 1-wire bus is divided into time slots of 60 micro-seconds. Reset pulse: Occurs 8 time slots. Pulling the bus LOW for 8 time slots (480 micro seconds) Presence pulse: Within 60 micro seconds of the release of the reset

Writing a bit 1: Master pulls the bus for 1-15 micro seconds & then releases the bus for the rest of the time. Writing a bit 0: Master pulling the bus for 1-2 time slots (60-120 micro seconds). Read a bit: Master pull the bus LOW for 1-15 micro seconds. If slave want to sent 1: It releases the bus reset of the time. If slave want to sent 0: It pulls the bus LOW for rest of the time.

Parallel interface
Normally used for communicating with peripheral devices which are memory mapped to the host of the system. Controlled by control signal. Read / write Device select Address decoder can be used for generating the chip select s/l for device. When the address selected by the processor is within the range assigned for the device the decoder ckt- activates the chip select. Data bus width: 4bit, 8bit, 16bit, 32bit, 64bit etc. Eg: ADC

External communication interface


RS232
Full duplex, Wired, Asynchronous serial communication. Logic 0 (space): represented with voltage b/w +3 & +25v. Logic 1 (mark) : represented with voltage b/w -3 & -25v. RS232 supports 2 diff- type of connectors: DB9 , DB25 Standard baud-rates: 300bps, 1200bps, 2400bps, 4800bps, 9600bps, 11.52kbps, 19.2kbps etc.

Maximum operating distance is: 50 feet at highest supported baud-rate. RS232 supports point to point communication (not suitable for malty-drop communication) Level converter In embedded s/m requires level translator to convert UART to RS232. MAX232

MAX232

RS422
Supports data rate up to 100kbps. Distance up to 400 ft. The same RS232 connector is used at the device end & an RS232 to RS422 converter is plugged in the transmission line & reverse operation in the receiver side. Supports malty-drop communication. With 1 transmitter device & receiver device up to 10. RS485: Enhanced version of RS422 & supports maltydrop communication with up to 32 devices. Uses addressing mechanism to identify s/m devices.

USB
1st version USB released in 1995. USB com. s/m follows: Star topology USB host at the center One or more USB slave peripheral / devices connected to it. Supports connections up to 127. USB transmits data in packet format. Diff. Standards for implementing the USB host: Open host control interface (OHCI) Universal host control interface (UHCI)

USB cable: up to 5 meters 2 type of connectors:


Type A: for upstream connection (connection with host) Type B: for downstream connection (connection with slave) Both having 4 pins: 1. Vbus 2. Ddifferential data carrier line 3. D+ differential data carrier line 4. GND uses differential voltage. It improves noise immunity.

For data transmission


Power supply:It can supply 500mA at 5V.

Each USB device contains:


Product ID (PID) Vendor ID (VID)

Supports 4 type of data transfer: Control -for query, configure & issue commands to the
USB device Bulk -for sending block of data Isochronous -for real time data communication, dose not support error checking & re-transmission Interrupt-for transmitting small amount of data. Eg: mouse, keyboard etc. Low speed -1.5Mbps Full speed -12Mbps High speed -480Mbps Super speed-4.8Gbps -defined by USB 1.0 -defined by USB 1.0 -defined by USB 2.0 -defined by USB 3.0

Supports 4 diff. Data rates:


IEEE 1394 (fire-wire)


Wired, isochronous high speed serial comm- bus. Also known as high performance serial bus. (HPSB) It can support a cable length of 15 ft. Uses diff- data transfer (through a pair of twisted cables) It increases noise immunity. 3 type of connectors 4 pin 6 pin (alpha connector) 9 pin (beta connector) 6 & 9 pin connectors carry power also It can supply unregulated power in the range of 24-30v

Pin name Power GND TPBTPB+ TPATPA+ TPA(s) TPB(s) NC

pin no. pin no. pin no. 4 pin 6 pin 9 pin _ _ 1 2 3 4 _ _ _ 1 2 3 4 5 6 _ _ _ 8 6 1 2 3 4 5 9 7

2 differential data transfer lines A, B per connector.

IrDA (infrared)
Serial, half-duplex IrDA support:
Point to point Point to malty-point But range can be increased by increasing transmitting power of IR

Range: 10cm 1m

Data rate: 9600bps 16Mbps Depending up on the speed, it is classified as:


Serial IR (SIR) Medium IR (MIR) Fast IR (FIR) Very fast IR (VFIR) Ultra fast IR (UFIR) : 9600bps to 115.2kbps : 0.576Mbps - 1.152Mbps : up to 4Mbps : up to 16Mbps : up to 100Mbps

Bluetooth (BT)
Low cost, low power, short range wireless tech. Operates at 2.4GHz. Supports data rate up to 1Mbps. Range is approximately 30 ft. It has 2 essential parts
Physical link part - responsible for physical transmission Protocol part - defining the rules of communication

Each bluetooth device will have a 48bit unique identifier no. It follows packet based data transfer. Supports
Point to point Point to malty-point

Bluetooth standards: GAP (generic access profile) Defines the requirements for detecting a bluetooth device & establishing a connection with it. SPP (serial port profile) For serial data communication. FTP (file transfer protocol) For file transfer b/w devices. HID (human interface device) For supporting human interface devices like keyboard, mouse etc.

Wi-Fi
Popular wireless communication technique for n/w comm. of devices. Wi-Fi follows the IEEE 802.11 standard. It is integrated for n/w comm. & it supports IP. Wi-Fi operates at 2.4GHz or 5GHz of radio frequency. When the Wi-Fi radio is ON, searches the available Wi-Fi n/w s & lists out the service set identifier (SSID). If the n/w is security enabled, a password may be required to connect to the SSID.

Wi-Fi employs different security mechanisms: WEP (wired equivalency privacy) WPA (wireless protected access) Supporting data rate: 1Mbps 150Mbps depending up on the Standards (802.11 a/b/g/n) & modulation method Depending upon the antenna (indoor/outdoor): Wi-Fi offers range of 100 300 ft.

ZigBee
Low power, low cost, wireless n/w communication protocol. Based on IEEE 802.15.4 standard. Applications for wireless personal area networking (WPAN) Radio spectrum: 2.4 2.484GHz 902 928MHz 868 868.6MHz Distance : 100m Data rate : 20 250kbps. ZigBee device falls under any one of the following: ZigBee coordinator (ZC) / n/w coordinater ZigBee Router (ZR) / full function device ZigBee end device (ZED) / reduced function device

GPRS
Comm- tech- for transferring data over a mobile commn/w like GSM. Data is sent as packets. Transfer rate : maximum 171.2kbps. GPRS comm- divides the channel into 8 time slots & transmits data over available channels. GPRS supports : IP, PPP, X.25 protocols. Mainly used by mobile enabled embedded devices. Device should support the necessary:
GPRS modem & GPRS radio.

New generation data comm- tech- are

EDGE HSDPA(high speed down-link packet access) these offers higher bandwidth for communication.

Embedded Firmware

Embedded Firmware
It refers to the control algorithm (program instructions) and or the configuration settings that an embedded system developer dumps int the PM of the embedded system. Various methods for developing the embedded s/m: High level language Assembly language Instruction set for diff- controller/processor are diff- & program written in any of the methods.

Hex file creation Cross compiler High level language Easy portable Assembly language Time consuming. Need to know about all the instruction set. 2 types of control algorithm design: Infinite loop or super loop. Splitting the functions to be executed into tasks & running these tasks using a scheduler which is part of GPOS / RTOS.

System Components

System Components
It refer to the components/ circuits/ IC s which are necessary for the proper functioning of the embedded system. Eg:

Reset oscillator Watchdog timer Brown-out protection RTC

Reset circuit
To ensure that the device is not operating at a voltage level where the device is not guaranteed to operate, during s/m power ON. Reset s/l brings the internal registers & the diff- h/w s/m s of the processor/controller to a known state & starts the firmware execution from the reset vector. Normally from vector address 0x0000 for conventional processor/controller. The rest vector can be relocated to an address for processors/controllers supporting bootloader. The reset s/l can be either: Active high or Active low

Brown-out protection circuit


It prevents the processor/ controller from unexpected program execution behavior when the supply voltage to the processor/ controller falls below a specified voltage. Brown-out protection circuit holds the processor/ controller in reset state, when the operation voltage falls below the threshold, until it rises above the threshold voltage. Some processors/ controllers supports built in brownout protection circuit.

Oscillator Unit
The instruction execution of a processor/ controller occurs in sync- with a clock signal. Certain processors/ controllers integrate a built-in oscillator unit & simply require an external quartz crystal for producing the necessary clock s/l. Certain devices may not contain a built-in oscillator unit & require the clock pulses to be generated & supplied externally. We can't increase the clock frequency blindly for increasing the speed of execution. The total s/m power consumption increases with increase in clock frequency.

RTC
RTC is a s/m component responsible for keeping track of time. RTC holds information like: Current time (in hours, minute & seconds) in 12/24 hour format Date, month, year, day of the week etc. It is intended to function even in the absence of power. The RTC chip contains: A microchip for holding the time & date related information & Backup battery cell for functioning in the absence of power.

Watchdog timer

Characteristics & Quality Attributes

CHARACTERISTICS OF AN EMBEDDED SYSTEM


Some of the important characteristics of the embedded s/m are : Application & domain specific Reactive & real time Operates in harsh environments Distributed Small size & weight Power concerns

Application and domain specific


Each embedded s/m is having certain functions to perform & they are developed in such a manner to do the intended fun- only.

Reactive and real time


Embedded s/m s are in constant interaction with the real world through sensors & user-defined i/p devices which are connected to the i/p port of the s/m. Any changes happening in the real world are captured by the sensors or i/p devices in real time & the control algorithm running inside the unit reacts in a designed manner to bring the controlled o/p variables to the desired level. The events may be periodic or aperiodic one.

Operates in harsh environment


The environment in which the embedded s/m deployed may be a dusty one or a high temp- zone or an area subject to vibrations and shock. s/m should capable of withstand all those adverse operating conditions. The design should take care of the operating conditions of the area where the s/m is going to implement.

Distributed
Distributed means that embedded s/m may be a part of larger s/m. Many no. of such distributed embedded s/m s form a single large embedded control unit.

Small size and weight


The product aesthetics (size, weight, shape, style, etc.) will be one of the deciding factors to choose a product. It is convenient to handle a compact device than a bulky product. In embedded domain also compactness is a significant deciding factor.

Power concerns
Power management is another important factor. Embedded s/m should be designed in such a way as to minimize the heat dissipation by the s/m. The production of high amount of heat demands cooling requirements, in turn occupies additional space and make the s/m bulky. Select the design according to the low power components and controllers/processors with power saving modes.

QUALITY ATTRIBUTES OF EMBEDDED SYSTEMS


The quality attributes are the non-functional requirements that need to be documented properly in any s/m design. Operational quality attributes Non-operational quality attributes

Operational quality attributes


It represent the relevant quality attributes related to the embedded s/m when it is in the operational mode. 1. Response 2. Throughput 3. Reliability 4. Maintainability 5. Security 6. Safety

Response
It gives an idea about how fast your s/m is tracking the changes in i/p variables.

Eg: an embedded s/m deployed in flight control application should respond in a real time manner. It is not necessary that all embedded s/m s should be real time in response.

Eg: toy

Throughput
It deals with the efficiency of a s/m. It can be defined as the rate of production or operation of a defined process over a stated period of time. Eg: In the case of a card reader, throughput means how many transactions the reader can perform in a minute or in an hour or in a day. Throughput is generally measured in terms of benchmark. benchmark can be a set of performance criteria that a product is expected to meet or a standard product that can be used for comparing other products of the same product line.

Reliability
Reliability is a measure of how much % you can rely upon the proper functioning of the s/m or what is the % susceptibility of the s/m to failures. Mean time b/w failure (MTBF) and mean time to repair (MTTR) are the terms used in defining s/m reliability. For an embedded s/m with critical application need, it should be of the order of minutes.

Maintainability
It deal with support & maintenance to the end user or client in case of technical issues and product failures or on the basis of a routine s/m checkup.

Security
3 major measures of information security: Confidentiality Protection of data & application from unauthorized disclosure. Integrity Protection of data & application from unauthorized modification. Availability Protection from unauthorized users.

Safety
It deals with the possible damages that can happen to the operators, public & the environment due to the breakdown of an embedded s/m or due to the emission of radioactive or hazardous materials from the embedded products. The breakdown of an embedded s/m may occur due to a h/w or firmware failure. Safety analysis is a must in product engineering.

Non-operational quality attributes


The quality attributes that needs to be addressed for the product not on the basis of operational aspects are grouped under this category. Testability & debug-ability Evolvability Portability Time to prototype and market Per unit and total cost

Testability & Debug-ability


It deals with how easily one can test his design, application & by which means he can test it. Testability is applicable to both the embedded h/w & f/w. h/w testing ensures that the peripherals & the total h/w functions in the desired manner. f/w testing ensures the f/w is functioning in the expected way. Debug-ability: h/w debugging Used for figuring out the issues created by h/w problems. f/w debugging To figure out the probable errors that appear as a result of flaws in a firmware.

Evolvability
It refers to the ease with which the embedded product (including h/w & f/w) can be modified to take advantage of new f/w or h/w technologies.

Portability
It is a measure of s/m independence. An embedded product is said to be portable if the product is capable of functioning 'as such' in various Environments, Target processors/controllers & Embedded OS.

Time-to-prototype and market


It is the time elapsed b/w the conceptualisation of a product & the time at which the product is ready for selling or use. Time to market the product is a critical factor in the success of a commercial embedded product.

Per unit cost & Revenue


Cost is a highly sensitive factor for commercial products. Any failure to position the cost of a commercial product at a nominal rate may lead to the failure of the product in the market. Proper market study & cost benefit analysis should be carried out before taking a decision on the per-unit cost of the embedded product. The budget & total s/m cost should be properly balanced to provide a marginal profit.