Z80Microprocessor

Addressing Modes

Immediate
Immediate Extended
Modified Page Zero Addressing (rst p)
Relative Addressing
Jump Relative (2 byte)
One Byte Op Code
8-Bit Twos Complement Displacement (A+2)

Extended Addressing
Absolutejump
Onebyteopcode
2byteaddress

Indexed Addressing
(Index Register + Displacement) (IX+d)
2byteopcode
1bytedisplacement

Addressing Modes(cont.)
Register Addressing
LD C,B

Implied Addressing
Op Code implies other operand(s)
ADD E

Register Indirect Addressing

16-bit CPU register pair as pointer (such as
HL)
ADD (HL)

Bit Addressing
set, reset, and test instructions.
SET 3,A
RES 7,B

Minimal Configuration of a
Z80 Microcomputer

Z80Memoryconnec<on
CPU16bitaddressbus64kmemory(max)
CPU8bitdatabus8bitdatawidth
Generallyshouldbeconnected
Datatodata
Addresstoaddress
Wrtowr
Rdtord
Mreqtocs

Memory connection (cont.)

If only one RAM chip Full size (64 kb capacity)

D7~D0

D7~D0

A15~A0

A15~A0

Z80
CPU

RAM
64kb

Memory connection (cont.)

If RAM capacity was 32 kb
A15 composed with MREQ
RAM area is from 0000h to 7FFFh

D7~D0

D7~D0

A14~A0

A14~A0

Z80
CPU

A15

RAM
32kb

Memory connection (cont.)

Thereistwo32kbRAM
Problem:BusConict.Thetwomemorychips
willprovidedataatthesame<mewhen
microprocessorperformsamemoryread.
Solu<on:UseaddresslineA15asanarbiter.
IfA15outputsalogic1theuppermemoryis
enabled(andthelowermemoryisdisabled)
andviceversa.

Memory connection (cont.)

There is two 32 kb RAM
A15 applied to select one RAM chip
TwoRAM area is from 0000h to 7FFFh (RAM1)
and 8000h to FFFFh(RAM1)

D7~D0

D7~D0

A14~A0

A14~A0

Z80
CPU

A15

RAM
32kb

D7~D0
A14~A0

RAM
32kb

Memory connection (cont.)

32 kb ROM and 32 kb RAM
ROM doesnt have wr signal

D7~D0

D7~D0

A14~A0

A14~A0

Z80
CPU

A15

ROM
32kb

D7~D0
A14~A0

RAM
32kb

Memory connection (cont.)

There is 4 memory chip
A14 and A15 applied to chip selection

D7~D0
Z80
A13~A0
CPU

D7~D0
ROM
16kb

D7~D0

A13~A0

A13~A0

A14
A15

En
S0
S1

RAM
16kb

D7~D0

RAM
16kb

A13~A0

D7~D0

RAM
16kb

A13~A0

Address Bit Map

Selects chip

Selects location within chips

A15 to A0
(HEX)

AA AA
11 11
54 32

AAAA
1198
10

AAAA
7654

AAAA
3210

0000h

00 00

0000

0000

0000

3FFFh

00 11

1111

1111

1111

4000h

01 00

0000

0000

0000

7FFFh

01 11

1111

1111

1111

8000h

10 00

0000

0000

0000

BFFFh

10 11

1111

1111

1111

C000h

11 00

0000

0000

0000

FFFFh

11 11

1111

1111

1111

Memory
Chip
ROM
RAM1
RAM2
RAM3

Memory Map
0000h

Representsthememorytype
Addressareaofeachmemorychip

3FFFh

Emptyarea
D7~D0

4000h

D7~D0

D7~D0
ROM
16kb

A13~A0

A13~A0

D7~D0
RAM
16kb

A13~A0

D7~D0
RAM
16kb

RAM
16kb
A13~A0

7FFFh

A13~A0

8000h
BFFFh

A14
A15

En

C000h

S0
S1

FFFFh

ROM
16k

RAM1
16k

RAM2
16k

RAM3
16k

Memory Map
0000h

EmptyAreacanntwriteandread
Readop.returnsFFhvalue(usualy)

ROM

3FFFh

Writeop.canntstoreanyvalueonit

4000h
Empty

D7~D0

D7~D0

D7~D0
ROM
16kb

A13~A0

A13~A0

RAM
16kb

RAM
16kb
A13~A0

7FFFh

D7~D0

A13~A0

8000h

RAM2

BFFFh
A14
A15

En

C000h

S0
S1

FFFFh

RAM3

Memory Map
0000h

EmptyAreacanntwriteandread
Readop.returnsFFhvalue(usualy)
Writeop.canntstoreanyvalueonit

ROM

3FFFh
4000h
Empty

D7~D0

D7~D0
ROM
16kb

A13~A0

A13~A0

7FFFh

D7~D0
RAM
16kb
A13~A0

8000h

RAM

BFFFh
A14
A15

En

C000h

S0
S1

Empty

FFFFh

Full and Partial Decoding

Full(exhaust)Decoding
Alloftheaddresslinesareconnectedtoanymemory/deviceto
performselec<on
Absoluteaddress:anymemoryloca<onhasoneaddress

Par<alDecoding
Whensomeoftheaddresslinesareconnectedthememory/deviceto
performselec<on
Usingthistypeofdecodingresultsintorolloveraddresses(foldback
orshading).
rolloveraddress:anymemoryloca<onhasmorethanoneaddress

Partial Decoding
A15~A12hasnoconnec<on
Thendoesntplayanyroleinaddressing
WhatistheMemoryandAddressBitmap?

D7~D0

D7~D0

A11~A0

A11~A0

A15~A12
Z80
CPU

RAM
4kb

Partial Decoding
Every memory location has more than one address
For example first RAM location has addresses:
0000h
1000h
2000h
Roll-over Address
3000h

0000h
0FFFh
1000h
1FFFh
2000h
2FFFh
3000h
3FFFh

.
.

F000h

F000h

FFFFh
D7~D0

A15 to A0
(HEX)

AAAA
1111
5432

AAAA
1198
10

AAAA
7654

AAAA
3210

X000h

xxxx

0000

0000

0000

XFFFh

xxxx

1111

1111

1111

Memory
Chip

RAM

Z80
CPU

RAM
RAM
RAM

RAM

D7~D0

A11~A0

A11~A0
A15~A12

RAM

RAM
4kb

Partial Decoding
A12onlyconnectedtoRAM
A13hasnoconnec<on
Whatisthememorymap?

D7~D0

D7~D0

A12~A0

A11~A0

A13
Z80
CPU

ROM
4kb

D7~D0
A12~A0

RAM
8kb

A15
A14

Partial Decoding
8rolloveraddressforROM
4rolloveraddressforRAM

D7~D0

D7~D0

D7~D0

ROM
4kb
A11~A0

A12~A0

Z80 A13
CPU

RAM
8kb
A12~A0

A15
A14

AAAA
1111
5432

AAAA
1198
10

AAAA
7654

AAAA
3210

0xxx

0000

0000

0000

0xxx

1111

1111

1111

X0x0

0000

0000

0000

X0x1

1111

1111

1111

Memory
Chip

ROM

RAM

Partial Decoding

0000h

0000h

RAM

D7~D0

ROM
4kb
A11~A0

A12~A0

Z80 A13
CPU

RAM
8kb
A12~A0

Conflict ROM
1FFFh

2000h

RAM

D7~D0
3FFFh

2FFFh
3000h
3FFFh

4000h

4000h
4FFFh

5000h

5FFFh

5FFFh

6000h

6000h

A15
A14

6FFFh

AAAA
1111
5432

AAAA
1198
10

AAAA
7654

0xxx

0000

0000

AAAA
3210
0000

0xxx

1111

1111

1111

X0x0

0000

0000

0000

X0x1

1111

1111

1111

Memory
Chip

7FFFh

7000h
7FFFh

8000h

F000h

RAM
9FFFh
A000h

RAM

4k

ROM

BFFFh
C000h

8k

RAM

DFFFh
E000h
FFFFh
FFFFh

ROM

1000h

1FFFh
2000h

D7~D0

0FFFh

ROM
ROM
ROM
ROM
ROM
ROM

Partial Decoding

0000h

0000h
0FFFh
1000h

1FFFh

1FFFh

2000h
D7~D0

D7~D0

Z80 A13
CPU

2FFFh

D7~D0

ROM
4kb
A11~A0

A12~A0

2000h

RAM
8kb
A12~A0

3000h

3FFFh

3FFFh

4000h

4000h

RAM

X
5FFFh

Conflict
5000h

5FFFh

6000h

6000h

A15
A14

RAM

AAAA
1111
5432

AAAA
1198
10

AAAA
7654

0xxx

0000

0000

AAAA
3210
0000

0xxx

1111

1111

1111

X1x0

0000

0000

0000

X1x1

1111

1111

1111

Memory
Chip

4FFFh

6FFFh

7FFFh

7000h
7FFFh

8000h

F000h

9FFFh
A000h

4k

ROM

BFFFh
C000h

RAM

8k

RAM

DFFFh
E000h

RAM
FFFFh

FFFFh

ROM
ROM
ROM
ROM
ROM
ROM
ROM
ROM

Full (exhaustive) decoding

AAAA
1111
5432

AAAA
1198
10

AAAA
7654

AAAA
3210

0000

0000

0000

0000

0001

1111

1111

1111

0010

0000

0000

0000

0010

0111

1111

1111

Memory
Chip

A12~A0
ROM

A12~A0
D7~D0
2764
EPROM
8k8

RAM

D7~D0
A13

A12

A11

Y1 0800h-0FFFh

Y2 1000h-17FFh

Y0

74138

Y3
Y4

A15

G2A

Y5

A14

G2B

Y6

G1

Y7

0000h-07FFh

1800h-1FFFh
2000h-27FFh

7421

A10~A0

A10~A0
D7~D0
6116
RWM
2k8

Partial decoding
AAAA
1111
5432

AAAA
1198
10

AAAA
7654

AAAA
3210

0000

0000

0000

0000

0001

1111

1111

1111

001x

x000

0000

0000

001x

x111

1111

1111

Memory
Chip

A12~A0
ROM

A12~A0
D7~D0
2764
EPROM
8k8

RAM

D7~D0
A15

A14

A13

Y1 2000h-3FFFh

Y2

Y0

74138

Y3
Y4

G2A

Y5

GND

G2B

Y6

VCC

G1

Y7

0000h-1FFFh

A10~A0

A10~A0
D7~D0
6116
RWM
2k8

1 Bit Memory With Separated I/O

D7-D0
D7

D1

Din
A11-A0

A11~A0
2147
RWM
4k1

Dout

D0

Din

Din
A11-A0

A11~A0
2147
RWM
4k1

Dout

A11~A0
A11-A0

2147
RWM
4k1

Dout

What is the memory(addr. bit) map

A12~A0
2764
EPROM
8k8

A15

A14

Y1

A13

Y2

Y0

74138

0000h-1FFFh
2000h-3FFFh

D7-D0

Y3
Y4

G2A

Y5

GND

G2B

Y6

VCC

G1

Y7

D7~D0

D7

Din
A11-A0

A11~A0 Dout
2147
RWM
4k1

D0

D1

Din

Din
A11-A0

A11~A0 Dout
2147
RWM
4k1

A11-A0

A11~A0 Dout
2147
RWM
4k1

Adding RAM & ROM

Minimum Z80 Computer System

Z80PFamily(TypicalEnvironment)

Z80 Input Output

Z80 at most could have 256 input port and 256 output
8 bit port address is placed on A7A0 pin to select the
I/O device
OUT (n), A
n is 8 bit port address

Content of A is data

OUT (C), r
Content of C is a port address

r is a data register

IN A, (n)
n is 8 bit port address

Data is transfered to A

IN r (C)
Content of Reg C is a port address

Input data is transfered to r (data reg)

Remember IO read/write cycle

Z80 and simple output port

D7
D6
D5
D4
D3
D2
D1
D0

A15
A14
:
A0

Z80
CPU

OUT(03),A

LE

WR
IORQ

IOWR

OE

D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
74LS373 Q4
D5
Q5
D6
Q6
D7
Q7

AAAA AAAA
7654 3210

Z80 and simple input port

D7
D6
D5
D4
D3
D2
D1
D0

A15
A14
:
A0

Z80
CPU

5V

INA,(02)

Y0
A0
Y1
A1
Y2
A2
Y3
A3
Y4 74LS244 A4
Y5
A5
Y6
A6
Y7
A7

G1 G2

RD
IORQ

IORD

AAAA AAAA
7654 3210

8088 and simple output port

D7
D6
D5
D4
D3
D2
8088 D1
Minimum D0
A19
A18
:
A0

Mode

IOR
IOW

LE

OE

D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
74LS373 Q4
D5
Q5
D6
Q6
D7
Q7

AAAAAAAAAAAAAAAAIOW
1 111119 87654 3210
5 43210

8088 and simple input port

Whatisthis?

D7
D6
D5
D4
D3
D2
8088 D1
Minimum D0
A19
A18
:
A0

Mode

IOR
IOW

5V

Y0
A0
Y1
A1
Y2
A2
Y3
A3
Y4 74LS244 A4
Y5
A5
Y6
A6
Y7
A7

G1 G2

AAAAAAAAAAAAAAAAIOW
1 111119 87654 3210
5 43210

Simplified Drawing of 8088 Minimum Mode

A7 - A0

E
DIR

D7 - D0

DEN
DT / R

AD7 - AD0

GND

A15 - A8

A19/S6 - A16/
S3

RD
IO / M
WR
ALE

D7-D0

A7-A0

A15-A8

A19-A16

Q7 - Q0

Q7 - Q0

Q7 - Q4
Q3 - Q0

74LS373

OE
LE

74LS373

OE
LE

D7 - D4
D3 - D0
GND

74LS245

D7 - D0
GND

8088

B7 - B0

74LS373

OE
LE

MEMR
MEMW
IOR
IOW

Minimum Mode
220 bytes or 1MB memory

D7 - D0

A19 - A0

D7 - D0

A19 - A0

Simplified
Drawing of
8088 Minimum
Mode

1 MB
Memory

MEMR

RD

MEMW

WR

CS

Whatarethememoryloca<onsofa1MB
(220bytes)Memory?
A19 to
A0
(HEX)

AAAA
1111
9876

AAAA
1111
5432

AAAA
1198
10

AAAA
7654

AAAA
3210

00000

0000

0000

0000

0000

0000

FFFFF

1111

1111

1111

1111

1111

Example: 34FD0
0011 0100 11111 1101 0000

Minimum Mode
512 kB memory

D7 - D0
A19

What do we do with A19?

D7 - D0

A18 - A0

A18 - A0

1) Dont connect it
2) Connect to cs

Simplified
Drawing of
8088 Minimum
Mode

512 kB
Memory

What is the difference?

MEMR

RD

MEMW

WR

CS

512 kB Memory Map

Dontconnectit

A19isnotconnectedtothe
memorysoevenifthe8088
microprocessoroutputsa
logic1,thememorycannot
seeit.
A19=0isthesameasA19=1
forMemory

Connecttocs

IfA19=0Memorychipact
normalfanc<on

00000h
7FFFFh

80000h
FFFFFh

00000h
7FFFFh

512k
Mem

512k
Mem

512k
Mem

80000h
FFFFFh

Empty

2 512 kB memory

D7 - D0
A19

D7 - D0

512 kB
RAM1

A18 - A0

MEMR

MEMR
MEMW

MEMW

A18 - A0

RD
WR

CS

D7 - D0

Simplified
Drawing of
8088 Minimum
Mode

512 kB
RAM2

MEMR
MEMW

A18 - A0

RD
WR

CS

2 512 kB memory
What are the memory locations of two
consecutive 512KB (219 bytes) Memory?

00000h

512k
RAM1
AAAA
1111
9876

AAAA
1111
5432

AAAA
1198
10

AAAA
7654

AAAA
3210

0000

0000

0000

0000

0000

0111

1111

1111

1111

1111

1000

0000

0000

0000

0000

1111

1111

1111

1111

1111

Memory
Chip

7FFFFh
80000h

ROM
512k
RAM2

RAM
FFFFFh

Interfacingfour256KMemory
Chipsto
the8088Microprocessor

A17
:

:
D0
RD
WR
CS
A0
D7

A17
:
A0
D7
:
D0
MEMR
MEMW
A19
A18

8088
Minimum
Mode

A17
:

256KB
#4

:
D0
RD
WR
CS
A0
D7

A17
:

256KB
#3

:
D0
RD
WR
CS
A0
D7

A17
:

:
D0
RD
WR
CS
A0
D7

256KB
#2

256KB
#1

Interfacingfour256KMemory
Chipsto
the8088Microprocessor

A17
:

:
D0
RD
WR
CS
A0
D7

A17
:
A0
D7
:
D0
MEMR
MEMW
A19
A18

8088
Minimum
Mode

A17
:

256KB
#4

:
D0
RD
WR
CS
A0
D7

A17
:

256KB
#3

:
D0
RD
WR
CS
A0
D7

A17
:

:
D0
RD
WR
CS
A0
D7

256KB
#2

256KB
#1

Memory chip#__ is mapped to:

AAAA
1111
9876

AAAA
1111
5432

AAAA
1198
10

AAAA
7654

AAAA
3210

Memory
Chip
RAM#1
RAM#2
RAM#3
RAM#4

A12
:

Interfacing
several 8K
Memory
Chips to the
8088 P

A12
:
A0
D7
:
D0
MEMR
8088 MEMW
Minimum
Mode
A19
A18
A17
A16
A15
A14
A13

:
D0
RD
WR
CS
A0
D7

8KB
#?

:
:
A12
:

:
D0
RD
WR
CS
A0
D7

A12
:

:
D0
RD
WR
CS
A0
D7

8KB
#2

8KB
#1

Interfacing
128
8K Memory
Chips to the
8088 P

A12
:

A12
:
A0
D7
:
D0
MEMR
8088 MEMW
Minimum
Mode
A19
A18
A17
A16
A15
A14
A13

:
D0
RD
WR
CS
A0
D7

8KB
#128

:
:
A12
:

:
D0
RD
WR
CS
A0
D7

A12
:

:
D0
RD
WR
CS
A0
D7

8KB
#2

8KB
#1

A12
:

Interfacing
128
8K Memory
Chips to the
8088 P

A12
:
A0
D7
:
D0
MEMR
8088 MEMW
Minimum
Mode
A19
A18
A17
A16
A15
A14
A13

:
D0
RD
WR
CS
A0
D7

8KB
#128

:
:
A12
:

:
D0
RD
WR
CS
A0
D7

A12
:

:
D0
RD
WR
CS
A0
D7

8KB
#2

8KB
#1

Memory chip#__ is mapped to:

AAAA
1111
9876

AAAA
1111
5432

AAAA
1198
10

AAAA
7654

AAAA
3210

Memory
Chip
RAM#1
RAM#2

RAM#126
RAM#127
RAM#128

What is the Memory and Address Bit map?

A12~A0

A12~A0
D7~D0
2764
EPROM
8k8

D7~D0

A14

A13

A12

Y1

Y2

Y0

74138

Y3
Y4

G2A

Y5

A15

G2B

Y6

VCC

G1

Y7

7408

A10~A0

A10~A0
D7~D0
6116
RWM
2k8

74244

input