Data Acquisition Systems

(Hardware Aspects)

Dr. Harshal Nemade Assistant Professor Department of Electronics and Communication Engineering

Data Acquisition Systems

(Hardware Aspects) Components of a data acquisition system Electrical characteristics of major components Associated programming issues

Data Acquisition Systems

(Hardware Aspects) A Typical Add-on Card for PC
e.g. PCL-818HG by Dynalog (India) Pvt. Ltd.

Blocks in Data Acquisition System

Analog Inputs Analog MUX PGA S/H A/D FIFO Digital Latch Internal Bus D/A Analog Output

Digital Inputs

Tristate Buffer

PC Interface

Digital Latch

Digital Outputs

PC Bus

Blocks in Data Acquisition System

Analog Inputs Analog MUX PGA S/H A/D FIFO Digital Latch Internal Bus D/A Analog Output

Digital Inputs

Tristate Buffer

PC Interface

Digital Latch

Digital Outputs

PC Bus

Blocks in Data Acquisition System

Analog Inputs Analog MUX PGA S/H A/D FIFO Digital Latch Internal Bus D/A Analog Output

Digital Inputs

Tristate Buffer

PC Interface

Digital Latch

Digital Outputs

PC Bus

Blocks in Data Acquisition System

Analog Inputs Analog MUX PGA S/H A/D FIFO Digital Latch Internal Bus D/A Analog Output

Digital Inputs

Tristate Buffer

PC Interface

Digital Latch

Digital Outputs

PC Bus

Blocks in Data Acquisition System

Analog Inputs Analog MUX PGA S/H A/D FIFO Digital Latch Internal Bus D/A Analog Output

Digital Inputs

Tristate Buffer

PC Interface

Digital Latch

Digital Outputs

PC Bus

Blocks in Data Acquisition System

Analog Inputs Analog MUX PGA S/H A/D FIFO Digital Latch Internal Bus D/A Analog Output

Digital Inputs

Tristate Buffer

PC Interface

Digital Latch

Digital Outputs

PC Bus

Analog Inputs

Analog MUX

PGA

S/H

A/D

FIFO

Digital Latch

Internal Bus

D/A

Analog Output

Digital Inputs

Tristate Buffer

PC Interface

Digital Latch

Digital Outputs

PC Bus

Analog Multiplexer
CH 1 CH 2 CH 3

1 of 16 Analog
Analog Inputs Output

1 out of 16 analog channels selected according to the 4 bit channel select input Features: Break-before-make type Delay between break and make slows down switching time Inputs may swing beyond the supply range

MUX

CH 16

A3 A2 A1 A0

Channel Select

Analog Inputs

Analog MUX

PGA

S/H

A/D

FIFO

Digital Latch

Internal Bus

D/A

Analog Output

Digital Inputs

Tristate Buffer

PC Interface

Digital Latch

Digital Outputs

PC Bus

Analog Inputs

Analog MUX

PGA

S/H

A/D

FIFO

Digital Latch

Internal Bus

D/A

Analog Output

Digital Inputs

Tristate Buffer

PC Interface

Digital Latch

Digital Outputs

PC Bus

Programmable Gain Amplifier (PGA)

The gain is selected by gain select binary inputs. Features:
Analog Input

PGA

Analog Output

Decides the input range of data acquisition system Input range = ADC range X PGA gain e.g. If ADC has fixed input range of 5 V,
PGA Gain 2 0.2 0.1 DAS input range

A2 A1 A0

Gain Select

10 V 1 V 0.5 V

Analog Inputs

Analog MUX

PGA

S/H

A/D

FIFO

Digital Latch

Internal Bus

D/A

Analog Output

Digital Inputs

Tristate Buffer

PC Interface

Digital Latch

Digital Outputs

PC Bus

Analog Inputs

Analog MUX

PGA

S/H

A/D

FIFO

Digital Latch

Internal Bus

D/A

Analog Output

Digital Inputs

Tristate Buffer

PC Interface

Digital Latch

Digital Outputs

PC Bus

Sample-and-Hold (S/H)
Analog Input S/H Output S/H HOLD SAMPLE HOLD
Aperture delay

Hold Capacitor

Input

Output follows Input

Droop Rate

Output
Hold to Sample switch delay Sample to Hold Settling Time Hold Time

Input Buffer

S/H

Output Buffer

Acquisition Time

t1 t2

Sample-and-Hold (S/H)
S/H Output

Acquisition time

1. Current sourcing and sinking capacity of input buffer 2. Value of hold capacitor

Analog Input

Hold Capacitor

Droop rate

1. Input resistance of output buffer 2. Value of hold capacitor

Input Buffer

S/H

Output Buffer

Analog Inputs

Analog MUX

PGA

S/H

A/D

FIFO

Digital Latch

Internal Bus

D/A

Analog Output

Digital Inputs

Tristate Buffer

PC Interface

Digital Latch

Digital Outputs

PC Bus

Analog Inputs

Analog MUX

PGA

S/H

A/D

FIFO

Digital Latch

Internal Bus

D/A

Analog Output

Digital Inputs

Tristate Buffer

PC Interface

Digital Latch

Digital Outputs

PC Bus

Analog-to-Digital Converter (ADC)

Digital output for n-bit ADC= Vin X 2n / Vref Analog Input Digital Output

ADC

Features: Resolution = Vref / 2n Finite conversion time Digital output valid only after end of conversion

Start of Conversion

End of Conversion

Sampling Analog Signal

Analog Inputs Analog MUX Internal Bus PGA S/H A/D

Channel Select

Gain Select (Select Input Range) Start of Conversion End of Conversion PC Interface

PC Bus

Sampling Analog Signal

Analog Inputs Analog MUX Internal Bus PGA S/H A/D

5 Read data

Channel Select 2

Gain Select (Select Input Range) 1 Start of Conversion 3 1. Software trigger 2. Pacer trigger 3. External trigger

End of Conversion 4 1. Polling 2. Interrupt 3. DMA

PC Interface

PC Bus

Analog Inputs

Analog MUX

PGA

S/H

A/D

FIFO

Digital Latch

Internal Bus

D/A

Analog Output

Digital Inputs

Tristate Buffer

PC Interface

Digital Latch

Digital Outputs

PC Bus

Analog Inputs

Analog MUX

PGA

S/H

A/D

FIFO

Digital Latch

Internal Bus

D/A

Analog Output

Digital Inputs

Tristate Buffer

PC Interface

Digital Latch

Digital Outputs

PC Bus

Analog Output Section

Digital Latch DAC Analog Output

For n-bit DAC Analog N Vref = Output 2n Features: 1. Period of Output rate >> Settling time of DAC 2. Low pass filter may be required

PC Interface

PC Bus

Internal Bus

Latch

Analog Inputs

Analog MUX

PGA

S/H

A/D

FIFO

Digital Latch

Internal Bus

D/A

Analog Output

Digital Inputs

Tristate Buffer

PC Interface

Digital Latch

Digital Outputs

PC Bus

Analog Inputs

Analog MUX

PGA

S/H

A/D

FIFO

Digital Latch

Internal Bus

D/A

Analog Output

Digital Inputs

Tristate Buffer

PC Interface

Digital Latch

Digital Outputs

PC Bus

Digital Input Section

Internal Bus Digital Inputs Tristate Buffer

EN PC Interface

PC Bus

Analog Inputs

Analog MUX

PGA

S/H

A/D

FIFO

Digital Latch

Internal Bus

D/A

Analog Output

Digital Inputs

Tristate Buffer

PC Interface

Digital Latch

Digital Outputs

PC Bus

Analog Inputs

Analog MUX

PGA

S/H

A/D

FIFO

Digital Latch

Internal Bus

D/A

Analog Output

Digital Inputs

Tristate Buffer

PC Interface

Digital Latch

Digital Outputs

PC Bus

Digital Output Section

Internal Bus PC Interface PC Bus

Digital Latch

Digital Outputs

Latch

Software for Data Acquisition System

Board Register Level Programming
Write series of binary code to the registers using C or Basic Does not require drivers provided by the manufacturer Maximum flexibility Difficult for interrupt or DMA based data acquisition

Using Driver Software

Recommended for data acquisition using interrupt and DMA

Demonstration of data acquisition using board level programming today afternoon

References
1. J. G. Whitaker, Electronic Handbook. CRC Press, 2002. Systems Maintenance

2. P. Horowitz and W. Hill, The art of Electronics. Cambridge University Press, 2003. 3. PCL818HG User's Manual. Dynalog (India) Pvt. Ltd.

Thank you for your attention