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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ncoR is
- Top level Entity
7.
generic
8.
(
9.
size : integer := 20
10.
);
11.
12.
port
13.
(
14.
clk
: in std_logic;
15.
reset
: in std_logic;
16.
x0
: in std_logic_vector (size-1 downto 0);
17.
y0
: in std_logic_vector (size-1 downto 0);
18.
z0
: in std_logic_vector (size-1 downto 0);
19.
phase
: out std_logic_vector (size-1 downto 0);
20.
quad
: out std_logic_vector (size-1 downto 0);
21.
angle
: buffer std_logic_vector (size-1 downto 0);
22.
start
: in std_logic;
23.
done
: out std_logic
24.
);
25.
26. end ncoR ;
27.
28. architecture arch of ncoR is
29.
30.
signal cnt
: std_logic_vector(4 downto 0);
31.
signal newx : std_logic_vector(size-1 downto 0);
32.
signal newy : std_logic_vector(size-1 downto 0);
33.
signal newz : std_logic_vector(size-1 downto 0);
34.
signal xreg : std_logic_vector(size-1 downto 0);
35.
signal yreg : std_logic_vector(size-1 downto 0);
36.
signal zreg : std_logic_vector(size-1 downto 0);
37.
signal sxreg : std_logic_vector(size-1 downto 0);
38.
signal syreg : std_logic_vector(size-1 downto 0);
39.
signal atan : std_logic_vector(size-1 downto 0);
40.
signal fin
: std_logic;
41.
signal nxt
: std_logic;
42.
signal as
: std_logic;
43.
signal nas
: std_logic;
44.
45.
-- Component declarations
46.
47.
component addsubR
-- Adder
48.
generic
49.
(
50.
size : integer := 20
51.
);
52.
53.
port
54.
(
55.
dataa : in
std_logic_vector (size-1 downto 0);
56.
datab : in
std_logic_vector (size-1 downto 0);
57.
result : out
std_logic_vector (size-1 downto 0);
58.
as
: in
std_logic
59.
);
60.
end component;
61.

62.

component anglelut
-- Angle
Look-Up Table
63.
generic
64.
(
65.
size : integer := 20
66.
);
67.
68.
port
69.
(
70.
index
: in std_logic_vector (4 downto 0);
71.
atan
: out std_logic_vector (size-1 downto 0)
72.
);
73.
end component;
74.
75.
component fsmR
-- Finite
State Machine
76.
77.
port
78.
(
79.
clk
: in std_logic ;
80.
reset : in std_logic ;
81.
start : in std_logic ;
82.
cnt
: in std_logic_vector (4 downto 0);
83.
initial : out std_logic ;
84.
nxt : out std_logic ;
85.
done : out std_logic
86.
);
87.
88.
end component;
89.
90.
component shiftR
-- Shifter
91.
generic
92.
(
93.
size : integer := 20
94.
);
95.
96.
port
97.
(
98.
data : in
std_logic_vector (size-1 downto 0);
99.
sdata : out
std_logic_vector (size-1 downto 0);
100.
n
: in
std_logic_vector (4 downto 0)
101.
);
102.
end component;
103.
104. begin
105.
106.
process (clk,newx,newy,newz,z0,nxt,fin)
107.
begin
108.
if (rising_edge(clk)) then
109.
if fin='1' then
110.
xreg <= x0;
111.
yreg <= y0;
112.
zreg <= z0;
113.
cnt<=(others=> '0');
114.
elsif nxt='1' then
115.
xreg <= newx;
116.
yreg <= newy;
117.
zreg <= newz;
118.
cnt <= cnt + '1';
119.
end if;
120.
end if;
121.
end process;

122.
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179.

as <= yreg(size-1);
MSB of y register
phase
<= yreg;
quad <= xreg;
angle <= zreg;
nas <= not(as);

addx : addsubR
Accumulator for x register
generic map
(
size => size
)

port map
(
dataa => xreg,
datab => syreg,
result => newx,
as
=> as
);
addy : addsubR
Accumulator for y register
generic map
(
size => size
)

port map
(
dataa => yreg,
datab => sxreg,
result => newy,
as
=> nas
);
addz : addsubR
Accumulator for z register
generic map
(
size => size
)
port map
(
dataa => zreg,
datab => atan,
result => newz,
as
=> as
);
lut : anglelut
generic map
(
size => size
)
port map
(

180.
index
=> cnt,
181.
atan => atan
182.
);
183.
184.
state_mach : fsmR
185.
port map
186.
(
187.
clk
=> clk,
188.
reset => reset,
189.
start => start,
190.
cnt
=> cnt,
191.
initial => fin,
192.
nxt => nxt,
193.
done => done
194.
);
195.
196.
shiftx : shiftR
Shifting x value
197.
generic map
198.
(
199.
size => size
200.
)
201.
202.
port map
203.
(
204.
data => xreg,
205.
sdata => sxreg,
206.
n
=> cnt
207.
);
208.
209.
shifty : shiftR
Shifting y value
210.
generic map
211.
(
212.
size => size
213.
)
214.
215.
port map
216.
(
217.
data => yreg,
218.
sdata => syreg,
219.
n
=> cnt
220.
);
221.
222. end arch;
223.
224. Lookup table
225.
226. library IEEE;
227. use IEEE.Std_Logic_1164.all;
228. use IEEE.Std_Logic_arith.all;
229.
230.
231. entity anglelut is
232.
233.
generic
234.
(
235.
size : positive := 20
236.
);
237.
port
238.
(
239.
index
: in std_logic_vector (4 downto 0);

--

--

240.
atan
: out std_logic_vector (size-1 downto 0)
241.
);
242.
243. end anglelut ;
244.
245.
246. architecture table of anglelut Is
247.
248.
signal tinfo : std_logic_vector(19 downto 0);
249.
250. begin
251.
252.
atan <= tinfo;
253.
process(index)
254.
begin
255.
256.
case index is
257.
when "00000" => tinfo <= X"3243F"; -- 45
258.
when "00001" => tinfo <= X"1DAC6"; -- 26.565
259.
when "00010" => tinfo <= X"0FADB"; -- 14.036
260.
when "00011" => tinfo <= X"07F56"; -- 7.125
261.
when "00100" => tinfo <= X"03FEA"; -- 3.576
262.
when "00101" => tinfo <= X"01FFD"; -- 1.789
263.
when "00110" => tinfo <= X"00FFF"; -- 0.8951
264.
when "00111" => tinfo <= X"007FF"; -- 0.4476
265.
when "01000" => tinfo <= X"003FF"; -- 0.2238
266.
when "01001" => tinfo <= X"001FF"; -- 0.1119
267.
when "01010" => tinfo <= X"000FF"; -- 0.0559
268.
when "01011" => tinfo <= X"0007F"; -- 0.0279
269.
when "01100" => tinfo <= X"0003F"; -- 0.0139
270.
when "01101" => tinfo <= X"0001F"; -0.00699
271.
when "01110" => tinfo <= X"0000F"; -0.00349
272.
when "01111" => tinfo <= X"00007"; -0.00174
273.
when "10000" => tinfo <= X"00003"; -0.00087
274.
when "10001" => tinfo <= X"00001"; -0.00043
275.
when "10010" => tinfo <= X"00000"; -0.00021
276.
when "10011" => tinfo <= X"00000"; -0.00010
277.
when others => tinfo <= "-------------------";
278.
279.
end case;
280.
end process;
end table;

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