n inputs

Combinational circuit

m outputs

Fig. 4-1 Block Diagram of Combinational Circuit

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

A B C A B C

T2 F1 T1

T3 F2 A B A C F2

B C Fig. 4-2 Logic Diagram for Analysis Example 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

AB 00 01 11 A 10

CD 00 1 1 X 1

C 01 11 10 1 1 B X X X D z D X A X 10 11 AB 00 01

CD 00 1 1 X 1

C 01 11 1 1 B X X X D CD C D C 01 11 10 X X 10

y C CD 00

AB 00 01 11 A 10

CD 00

01 1

11 1

10 1

AB 00 01 B

1 X X 1 X X D BD X A X

1 X 1 X 1 D BC

1 X X

1 X X

11 10

BC

BC D

BD

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

Fig. 4-3 Maps for BCD to Excess-3 Code Converter

D C

CD

(C C B D

D)

A Fig. 4-4 Logic Diagram for BCD to Excess-3 Code Converter 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

x y S x y x y (a) S C xy xy xy (b) S C xy xy C x y S

Fig. 4-5 Implementation of Half-Adder

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

x 0 x 1

yz 00

y 01 1 11 10 1 1 z x x 0 1

yz 00

y 01 11 1 1 z 1 1 10

xyz

x yz

xy z

xyz

xy xy

xz yz xy z x yz

Fig. 4-6 Maps for Full Adder

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

x y z x y z S x y z

x y

x z C

y x y z z

Fig. 4-7 Implementation of Full Adder in Sum of Products

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

x y

z Fig. 4-8 Implementation of Full Adder with Two Half Adders and an OR Gate

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

B3

A3

B2

A2

B1

A1

B0

A0

FA

C3

FA

C2

FA

C1

FA

C0

C4

S3

S2

S1 Fig. 4-9 4-Bit Adder

S0

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

Ai Bi

Pi Si

Gi

Ci

Ci Fig. 4-10 Full Adder with P and G Shown

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

C3

P2 G2

C2 P1 G1

P0 G0 C0 Fig. 4-11 Logic Diagram of Carry Lookahead Generator 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

C1

C4 B3 A3 P3 P3 G3 C3

C4

S3

B2 A2

P2 C2 G2 Carry Look ahead generator

P2

S2

B1 A1

P1 G1

P1 C1

S1

B0 A0

P0 G0

P0

S0

C0

C0

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

Fig. 4-12 4-Bit Adder with Carry Lookahead

B3

A3

B2

A2

B1

A1

B0

A0

C4 C FA

C3

FA

C2

FA

C1

FA

C0

S3

S2

S1

S0

Fig. 4-13 4-Bit Adder Subtractor

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

Addend

Augend

Carry out

4- bit binary adder Z8 Z4 Z2 Z1

Carry in

Output carry

4- bit binary adder

S8 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

S4

S2

S1

Fig. 4-14 Block Diagram of a BCD Adder

B1 A1 A0B1 A1B1 C3 C2 A1B0 C1

B0 A0 A 0B 0

A0

B1

B0

C0

A1

B1

B0

HA

HA

C3 C2 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e. Fig. 4-15 2-Bit by 2-Bit Binary Multiplier

C1

C0

A0

B3

B2

B1

B0

A1

B3

B2

B1

B0

0 Addend 4-bit adder Sum and output carry Augend

A2

B3

B2

B1

B0

Addend 4-bit adder

Augend

Sum and output carry

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

C6

C5

C4

C3

C2

C1

C0

Fig. 4-16 4-Bit by 3-Bit Binary Multiplier

A3 x3 B3

A2 x2 B2

(A A1 x1

B)

B1

A0 x0 B0 (A B)

(A

B)

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

Fig. 4-17 4-Bit Magnitude Comparator

D0

xyz

D1

xyz

D2 y D3

x yz

x yz

D4

xy z

D5

xy z

D6

xyz

D7 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

xyz

Fig. 4-18 3-to-8-Line Decoder

D0 E D1 A D2 B D3 E (a) Logic diagram Fig. 4-19 2-to-4-Line Decoder with Enable Input (b) Truth table 1 0 0 0 0 A X 0 0 1 1 B X 0 1 0 1 D0 D1 D2 D3 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

x y z w 3 8 decoder E D 0 to D 7

3 8 decoder E

D 8 to D 15

Fig. 4-20 4

16 Decoder Constructed with Two 3

8 Decoders

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

0 1 x y z 22 21 20 3 8 decoder 2 3 4 5 6 7 C S

Fig. 4-21 Implementation of a Full Adder with a Decoder

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

D2 00 00 01 X 01 1 1 1 1 D3 x D2 D3 Fig. 4-22 Maps for a Priority Encoder y D3 11 1 1 1 1 10 1 1 D1 11 D0 10 1 1 D0 10 1 D3 D1D 1 11 1 1 1 00 01 00 X 1 01 1 1 11 1 1

D2 10 1 1 D1 1 1

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

D3 D2 D1 y

D0 Fig. 4-23 4-Input Priority Encoder

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

I0 I0 Y I1 I1 1 0 MUX Y

(a) Logic diagram Fig. 4-24 2-to-1-Line Multiplexer

(b) Block diagram

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

I0

s1 0 0 1 1 Y

s0 0 1 0 1

Y I0 I1 I2 I3

I1

I2

(b) Function table

I3

s1 s0 (a) Logic diagram 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e. Fig. 4-25 4-to-1-Line Multiplexer

A0 Y0 A1 Y1 A2 Y2 A3 Y3

B0 Function table B1 E 1 0 0 S X 0 1 Output Y all 0's select A select B

B2 B3

S (select) E (enable)

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

Fig. 4-26 Quadruple 2-to-1-Line Multiplexer

4 y x x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 F 0 1 1 0 0 0 1 1 S0 S1

1 MUX

F F F F

z z 0 1

z z 0 1

0 1 2 3

(a) Truth table

(b) Multiplexer implementation

Fig. 4-27 Implementing a Boolean Function with a Multiplexer

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

8 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 F 0 1 0 1 1 0 0 0 0 0 0 1 1 1 1 1 C F F F F F F F F D D D 0 0 D 1 1 1 0 B A D S0 S1 S2 0 1 2 3 4 5 6 7

1 MUX

Fig. 4-28 Implementing a 4-Input Function with a Multiplexer

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

Normal input A Control input C

Output Y A if C Highimpedance if C

1 0

Fig. 4-29 Graphic Symbol for a Three-State Buffer

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

I0

I1

I2

I3 0 2 4 decoder 1 2 3

B Select

Select Enable

S1 S0 EN

(a) 2-to-1- line mux

(b) 4 - to - 1 line mux

Fig. 4-30 Multiplexers with Three-State Gates

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

in control bufifl

out

in control bufif0

out

in control notifl

out

in control notif0

out

Fig. 4-31 Three-State Gates

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

out

B select Fig. 4-32 2-to-1-Line Multiplexer with Three-State Buffers

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

Stimulus module

Design module

module testcircuit reg TA, TB; wire TC; circuit cr (TA, TB, TC);

module circuit (A, B, C); input A, B; output C;

Fig. 4-33 Stimulus and Design Modules Interaction

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

A B C T1

T3

F1 T2

T4

F2

Fig. P4-1

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

A F

B C G D Fig. P4-2

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

a f e g d b b c c

(a) Segment designation

(b) Numerical designation for display Fig. P4-9

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

C1

B0 S0 A0 C0 Fig. P4-17 First Stage of a Parallel Adder

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.