Design a divide-by-3 sequential circuit with 50% duty circle?

What are the different Adder circuits you studied? Give a circuit to divide frequency of clock cycle by two ? What are set up time & hold time constraints What do they signify Which one is c ritical for estimating maximum clock frequency of a circuit? Explain about setup time and hold time, what will happen if there is setup time and hold tine violation, how to overcome this? What is skew, what are problems associated with it and how to minimize it? What is the function of a D flip-flop, whose inverted output is connected to its input ? Design a circuit to divide input frequency by 2. Design a divide-by-3 sequential circuit with 50% duty cycle. Design a divide-by-5 sequential circuit with 50% duty cycle. What are the different types of adder implementations ? Draw a Transmission Gate-based D-Latch.