Optimization of Bosch Etch Process for Through Wafer Interconnects

Linda Kenoyer, Rex Oxford, and Amy Moll College of Engineering Boise State University 1910 University Avenue, Boise ID 83725-2075

shorter than chip-to-chip connections in two dimensions. Advanced processing techniques are being developed to make 3-D packaging possible. High aspect-ratio through-

SFB CsFs

1 I

1 Etch Cycle
100sccm 1 sccm

I Deposition Cycle I I sccm

I 35 sccm

Decreasing RF power during etch made it worse, whereas decreasing passivation flows and times, particularly paired with more aggressive etch, has improved results.

Figure 4 shows that the polymer build-up at the top of the via is gone. The characteristic Bosch process scallop lines are now seen in the sidewalls. The process has been consistent and reproducible over several months and 8 cleaning cycles.

resulted in deeply veined sidewalls and built-up polymer at the top ofthe via.

In the course of process development, we noted that instability in the flow control of SF6during the deposition cycle resulted in improved process performance. Based on this observation, the process parameters in Table I1 were tested.

Figure 4. A close up of the top o f one of the vias from Figure 3 shows no build-up of polymer at the top of the via. Characteristic Bosch scalloping lines can be seen in the sidewalls.

Iv.
SF6 C~FR

CONCLUSIONS

1 Etch Cycle 1 100

11

Deposition Cycle 5 100

A small amount of SF6 flow during the deposition step of the Bosch etch process can be very effective in eliminating problems created by excess polymer deposition. Useable through-wafer vias have been repeatedly achieved using this new process. Further work to understand the dynamics of the process and more thoroughly characterize the effects of the many process parameters is underway.
ACKNOWLEDGEMENTS

This project is supported by the DAWA MTO office and administered by SPAWAR SYSNCENiSan Diego. CA under Grant N66001-00-1-8950
REFERENCES:

IllRobert Bosch Gmbh, U.S. Patent 4,855,017 and 4,784,420

[2]A. Ayan, R. Braff, R. Bap, H. Sawin, and M. Schmidt, 1. Electrochemical Society, 146, 339(1999)

[3]Walker, M., Proc. SPIE MEMS Canf. ,89, (2001)

I
Figure 3. These vias are 50 ptn in diameter, and have been etched 311 pm deep. They show excellent profile, clean sidewalls, and no prass.

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