Stop Band 100 40 10

//Copyright (c) 2006 Quickfilter Technologies, Inc
//
//
Thursday, July 16, 2009
//
//------------------------------------------------------------------------// Group 1 is Active
//------------------------------------------------------------------------//////////////////////////////////////////////////////////////////////////
//
// Configuration Information:
//
//////////////////////////////////////////////////////////////////////////
//
// ChipType = QF4A512
//
// Export from file: C:\Documents and Settings\Owner\Desktop\ECG\filter\filter d
esign\Stop_band_100_40_10.qfp
//
// AutoConfig is not set
//
// AutoStart is not set
//
// SPI Bandwidth = 40.000000 MBits/sec
//
// External clock = 20.000000 MHz
//
ADC Clock Rate = 3
//
ADC Clock = 12.500000 MHz
//
Channel 1 - Filter Name: Parks-McClellan: Bandstop
//
Sample Frequency = 2000.640205 Hz
//
Number of Taps = 261
//
GainIC = 24209
//
R Value = 1562
//
AAF Value = 500000
//
AfeFcsel Value = 0
//
Output is enabled
//
Optimize Power is off
//
Over-sampling ratio = 0
//////////////////////////////////////////////////////////////////////////
// CONTROL SEQUENCES:
//
// To control Quickfilter's chip, set the chip's register values (8 bits)
// at the indicated address to the listed values
// x: don't care bit
// -: maintain the existing bit value
//
//////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////
// INITIALIZATION SEQUENCES
//////////////////////////////////////////////////////////////////////////
//------------------------------------------------------------------------// 1. Reset Chip: Perform a hard reset on chip
//------------------------------------------------------------------------//------------------------------------------------------------------------// 2. Stop Chip: Make sure chip is in the configuration mode: run_mode and ram_r
un_mode are OFF (0)
//-------------------------------------------------------------------------
// Address(Hex)
04
15
Value (Hex)
00
48
//------------------------------------------------------------------------// 3. Download configuration file

//------------------------------------------------------------------------//------------------------------------------------------------------------// Register values
//------------------------------------------------------------------------Address
RegisterName
RegisterValue(Hex)
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
000A
000B
000C
000D
000E
000F
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
001A
001B
001C
001D
001E
001F
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
002A
002B
002C
002D
002E
GLBL_SW
GLBL_ID
GLBL_TOP_RST
GLBL_CH_CTRL
SIF_RUN_MODE
SPIM_CTRL_0
IGC_CTRL_0
STARTUP_0
STARTUP_1
ENABLE_0
ENABLE_1
ENABLE_2
PLL_SIF_STAT
SPIM_EE_STAT
SPIM_STAT
ADC_STATUS_0
ADC_STATUS_1
PLL_CTRL_0
PLL_CTRL_1
ADC_CLK_RATE
SYS_CLK_CTRL
SIF_CTRL
SPIM_MON
SPIM_EE_STADDR_0
SPIM_EE_STADDR_1
SPIM_SIF_STADDR_0
SPIM_SIF_STADDR_1
SPIM_RX_ENDADDR_0
SPIM_RX_ENDADDR_1
GLBL_SCRATCH_PAD_0
GLBL_SCRATCH_PAD_1
GLBL_SCRATCH_PAD_2
GLBL_SCRATCH_PAD_3
GLBL_SCRATCH_PAD_4
GLBL_SCRATCH_PAD_5
GLBL_SCRATCH_PAD_6
GLBL_SCRATCH_PAD_7
DBG_SULOCK
GLBL_SRST
ADC_CTRL
AREC_CTRL
PMUX_MNTNC
DBG_MODE
PCG_MNTNC
CAL_AFE
BIST_CTRL
BIST_STATUS0
00
A0
00
00
00
00
00
40
80
13
31
11
00
00
00
00
00
41
0A
03
15
48
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
09
00
00
00
01
00
00
002F
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
003A
003B
003C
003D
003E
003F
0040
0041
0042
0043
0044
0045
0046
0047
0048
0049
004A
004B
004C
004D
004E
004F
0050
0051
0052
0053
0054
0055
0056
0057
0058
0059
0060
0061
0062
0063
0064
0065
0066
0067
0068
0069
006A
006B
006C
006D
006E
006F
0070
BIST_STATUS1
CH0_RUN
CH0_STAT
CH0_CFG
AREC_CH0_GNC_0
AREC_CH0_GNC_1
CHPC_DIV0_0
CHPC_DIV0_1
CIC0_R_0
CIC0_R_1
CIC0_R_2
CIC_SW_SHIFT_0
FIR_0_0_CTRL1
FIR_0_0_NMIN_F1
FIR_0_0_NMAX_F1
FIR_0_0_CMIN_F1
FIR_0_0_CMAX_F1
FIR_0_0_NMIN_F2
FIR_0_0_NMAX_F2
FIR_0_0_CMIN_F2
FIR_0_0_CMAX_F2
FIR_0_1_CTRL1
FIR_0_1_NMIN_F1_0
FIR_0_1_NMIN_F1_1
FIR_0_1_NMAX_F1_0
FIR_0_1_NMAX_F1_1
FIR_0_1_CMIN_F1
FIR_0_1_CMAX_F1
FIR_0_1_NMIN_F2_0
FIR_0_1_NMIN_F2_1
FIR_0_1_NMAX_F2_0
FIR_0_1_NMAX_F2_1
FIR_0_1_CMIN_F2
FIR_0_1_CMAX_F2
CH0_SRST
CAL_0_CHP_OFF_0
CAL_0_CHP_OFF_1
AREC_CH0_OFC_0
AREC_CH0_OFC_1
CAL_0_OFF_0
CAL_0_OFF_1
CAL_0_GAIN_0
CAL_0_GAIN_1
CH1_RUN
CH1_STAT
CH1_CFG
AREC_CH1_GNC_0
AREC_CH1_GNC_1
CHPC_DIV1_0
CHPC_DIV1_1
CIC1_R_0
CIC1_R_1
CIC1_R_2
CIC_SW_SHIFT_1
FIR_1_0_CTRL1
FIR_1_0_NMIN_F1
FIR_1_0_NMAX_F1
FIR_1_0_CMIN_F1
FIR_1_0_CMAX_F1
FIR_1_0_NMIN_F2
00
00
00
60
91
5E
34
0C
19
06
00
1B
57
00
0E
00
07
0F
7D
08
3F
02
00
00
04
01
00
82
00
00
FF
01
00
FF
00
0F
00
00
C0
00
00
00
80
10
00
F0
00
40
00
00
08
00
00
00
00
00
7F
00
3F
00
0071
0072
0073
0074
0075
0076
0077
0078
0079
007A
007B
007C
007D
007E
007F
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
0090
0091
0092
0093
0094
0095
0096
0097
0098
0099
009A
009B
009C
009D
009E
009F
00A0
00A1
00A2
00A3
00A4
00A5
00A6
00A7
00A8
00A9
00AA
00AB
00AC
00AD
00AE
00AF
00B0
00B1
00B2
FIR_1_0_NMAX_F2
FIR_1_0_CMIN_F2
FIR_1_0_CMAX_F2
FIR_1_1_CTRL1
FIR_1_1_NMIN_F1_0
FIR_1_1_NMIN_F1_1
FIR_1_1_NMAX_F1_0
FIR_1_1_NMAX_F1_1
FIR_1_1_CMIN_F1
FIR_1_1_CMAX_F1
FIR_1_1_NMIN_F2_0
FIR_1_1_NMIN_F2_1
FIR_1_1_NMAX_F2_0
FIR_1_1_NMAX_F2_1
FIR_1_1_CMIN_F2
FIR_1_1_CMAX_F2
CH1_SRST
CAL_1_CHP_OFF_0
CAL_1_CHP_OFF_1
AREC_CH1_OFC_0
AREC_CH1_OFC_1
CAL_1_OFF_0
CAL_1_OFF_1
CAL_1_GAIN_0
CAL_1_GAIN_1
CH2_RUN
CH2_STAT
CH2_CFG
AREC_CH2_GNC_0
AREC_CH2_GNC_1
CHPC_DIV2_0
CHPC_DIV2_1
CIC2_R_0
CIC2_R_1
CIC2_R_2
CIC_SW_SHIFT_2
FIR_2_0_CTRL1
FIR_2_0_NMIN_F1
FIR_2_0_NMAX_F1
FIR_2_0_CMIN_F1
FIR_2_0_CMAX_F1
FIR_2_0_NMIN_F2
FIR_2_0_NMAX_F2
FIR_2_0_CMIN_F2
FIR_2_0_CMAX_F2
FIR_2_1_CTRL1
FIR_2_1_NMIN_F1_0
FIR_2_1_NMIN_F1_1
FIR_2_1_NMAX_F1_0
FIR_2_1_NMAX_F1_1
FIR_2_1_CMIN_F1
FIR_2_1_CMAX_F1
FIR_2_1_NMIN_F2_0
FIR_2_1_NMIN_F2_1
FIR_2_1_NMAX_F2_0
FIR_2_1_NMAX_F2_1
FIR_2_1_CMIN_F2
FIR_2_1_CMAX_F2
CH2_SRST
CAL_2_CHP_OFF_0
7F
00
3F
00
00
00
FF
01
00
FF
00
00
FF
01
00
FF
00
95
00
00
C0
00
00
00
80
10
00
F0
00
40
00
00
08
00
00
00
00
00
7F
00
3F
00
7F
00
3F
00
00
00
FF
01
00
FF
00
00
FF
01
00
FF
00
95
00B3
00B4
00B5
00B6
00B7
00B8
00B9
00C0
00C1
00C2
00C3
00C4
00C5
00C6
00C7
00C8
00C9
00CA
00CB
00CC
00CD
00CE
00CF
00D0
00D1
00D2
00D3
00D4
00D5
00D6
00D7
00D8
00D9
00DA
00DB
00DC
00DD
00DE
00DF
00E0
00E1
00E2
00E3
00E4
00E5
00E6
00E7
00E8
00E9
00EA
00EB
00EC
00ED
00EE
00EF
CAL_2_CHP_OFF_1
AREC_CH2_OFC_0
AREC_CH2_OFC_1
CAL_2_OFF_0
CAL_2_OFF_1
CAL_2_GAIN_0
CAL_2_GAIN_1
CH3_RUN
CH3_STAT
CH3_CFG
AREC_CH3_GNC_0
AREC_CH3_GNC_1
CHPC_DIV3_0
CHPC_DIV3_1
CIC3_R_0
CIC3_R_1
CIC3_R_2
CIC_SW_SHIFT_3
FIR_3_0_CTRL1
FIR_3_0_NMIN_F1
FIR_3_0_NMAX_F1
FIR_3_0_CMIN_F1
FIR_3_0_CMAX_F1
FIR_3_0_NMIN_F2
FIR_3_0_NMAX_F2
FIR_3_0_CMIN_F2
FIR_3_0_CMAX_F2
FIR_3_1_CTRL1
FIR_3_1_NMIN_F1_0
FIR_3_1_NMIN_F1_1
FIR_3_1_NMAX_F1_0
FIR_3_1_NMAX_F1_1
FIR_3_1_CMIN_F1
FIR_3_1_CMAX_F1
FIR_3_1_NMIN_F2_0
FIR_3_1_NMIN_F2_1
FIR_3_1_NMAX_F2_0
FIR_3_1_NMAX_F2_1
FIR_3_1_CMIN_F2
FIR_3_1_CMAX_F2
CH3_SRST
CAL_3_CHP_OFF_0
CAL_3_CHP_OFF_1
AREC_CH3_OFC_0
AREC_CH3_OFC_1
CAL_3_OFF_0
CAL_3_OFF_1
CAL_3_GAIN_0
CAL_3_GAIN_1
SPIN_ID
IGC_SEQADDR_0
IGC_SEQADDR_1
CAL_CTRL
CAL_DTGT_0
CAL_DTGT_1
00
00
C0
00
00
00
80
10
00
F0
00
40
00
00
08
00
00
00
00
00
7F
00
3F
00
7F
00
3F
00
00
00
FF
01
00
FF
00
00
FF
01
00
FF
00
95
00
00
C0
00
00
00
80
00
00
0F
00
00
00
//------------------------------------------------------------------------// 4. Download G&H coefficients

//-------------------------------------------------------------------------
//------------------------------------------------------------------------//
G & H coefficient values
//------------------------------------------------------------------------Address
Channel
Coefficient
Value (Hex)
0100
0102
0104
0106
0108
010A
010C
010E
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
1
1
1
1
1
1
1
1
G
G
G
G
G
G
G
G
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
01
02
03
04
05
06
07
08
00A5
0206
FEF5
F843
FA02
0C6B
2661
32C3
//------------------------------------------------------------------------// 5. Download FIR coefficients

//------------------------------------------------------------------------//------------------------------------------------------------------------// FIR coefficient values
//------------------------------------------------------------------------Address
0300
0303
0306
0309
030C
030F
0312
0315
0318
031B
031E
0321
0324
0327
032A
032D
0330
0333
0336
0339
033C
033F
0342
0345
0348
034B
034E
0351
0354
0357
035A
035D
0360
0363
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Coefficient
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Value (Hex)
001
002
003
004
005
006
007
008
009
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031
032
033
034
0281D
016FD
FE85C
00BCE
FF426
007AC
FFBEF
006C3
000E1
0069D
00342
005BD
00333
0038A
00123
0003F
FFE03
FFCC7
FFB20
FFA5D
FF9C6
FFA0C
FFABF
FFC29
FFDF0
00016
00247
0045F
00615
00743
007BD
00774
00667
004AD
0366
0369
036C
036F
0372
0375
0378
037B
037E
0381
0384
0387
038A
038D
0390
0393
0396
0399
039C
039F
03A2
03A5
03A8
03AB
03AE
03B1
03B4
03B7
03BA
03BD
03C0
03C3
03C6
03C9
03CC
03CF
03D2
03D5
03D8
03DB
03DE
03E1
03E4
03E7
03EA
03ED
03F0
03F3
03F6
03F9
03FC
03FF
0402
0405
0408
040B
040E
0411
0414
0417
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
035
036
037
038
039
040
041
042
043
044
045
046
047
048
049
050
051
052
053
054
055
056
057
058
059
060
061
062
063
064
065
066
067
068
069
070
071
072
073
074
075
076
077
078
079
080
081
082
083
084
085
086
087
088
089
090
091
092
093
094
00271
FFFEC
FFD5F
FFB10
FF93B
FF815
FF7BA
FF833
FF973
FFB52
FFD9D
00011
0026A
00468
005D8
0069A
006A3
005FF
004CE
00340
00191
FFFF7
FFEA8
FFDC5
FFD64
FFD7A
FFDF7
FFEAB
FFF69
FFFFB
00036
FFFFD
FFF49
FFE2B
FFCCA
FFB64
FFA40
FF9A5
FF9D3
FFAF3
FFD0F
0000F
003B5
007A2
00B60
00E6C
0104B
01094
00F07
00B94
00669
FFFE7
FF8A6
FF161
FEAEA
FE613
FE387
FE3C5
FE703
FED2B
041A
041D
0420
0423
0426
0429
042C
042F
0432
0435
0438
043B
043E
0441
0444
0447
044A
044D
0450
0453
0456
0459
045C
045F
0462
0465
0468
046B
046E
0471
0474
0477
047A
047D
0480
0483
0486
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
FIR
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
Coeff
095
096
097
098
099
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
FF5C8
0001E
00B36
015ED
01F14
0259F
028B2
027C4
022B4
019D4
00DDB
FFFE2
FF148
FE383
FD810
FD031
FCCD8
FCE8B
FD547
FE084
FEF42
00015
01158
02149
02E43
036E2
03A34
037C8
02FC6
022EB
01270
FFFF8
FED59
FDC71
FCEF8
FC64D
7C34D
//------------------------------------------------------------------------// 6. Turn the channels clock off (0) if channels are inactive
//------------------------------------------------------------------------// Address(Hex)
Value (Hex)
09
13
//------------------------------------------------------------------------// 7. Turn ram_run_mode ON in order to clear status bits
//------------------------------------------------------------------------// Address(Hex)
Value (Hex)
15
49
//------------------------------------------------------------------------// 8. Clear status bits
//------------------------------------------------------------------------// Address(Hex)
Value (Hex)
31
00
61
00
91
00
C1
00
//------------------------------------------------------------------------// 9. Start the chip: turn ram_run_mode and sif_run_mode ON

//------------------------------------------------------------------------// Address(Hex)
Value (Hex)
15
49
04
01
//////////////////////////////////////////////////////////////////////////
// TO START/STOP THE CHIP SEQUENCES
//////////////////////////////////////////////////////////////////////////
//------------------------------------------------------------------------//
To stop the chip for register operations (Read/Write)
//------------------------------------------------------------------------////// Set SifRunMode to 0
////// 1.Read Register
Address(Hex)
Value (Hex)
04
ReadData
////// 2. LOGICAL OR the ReadData with 0x01
WriteData = ReadData | 0x01
////// 3.Write Register
Address(Hex)
Value (Hex)
04
WriteData
//------------------------------------------------------------------------//
To stop the chip for memory operations (Read/Write)
Address(Hex)
Value (Hex)
04
ReadData
////// 2. LOGICAL AND the read data with 0xFE
WriteData = ReadData & 0xFE
Address(Hex)
Value (Hex)
04
WriteData
////// Set RamRunMode to 0
Address(Hex)
Value (Hex)
15
ReadData
Address(Hex)
Value (Hex)
15
WriteData
//------------------------------------------------------------------------//
To start the chip
Address(Hex)
15
Value (Hex)
ReadData

Address(Hex)
Value (Hex)
15
WriteData
Address(Hex)
Value (Hex)
04
ReadData
Address(Hex)
Value (Hex)
04
WriteData
//////////////////////////////////////////////////////////////////////////
// TO SET/UNSET AUTOCONFIG SEQUENCES
//////////////////////////////////////////////////////////////////////////
//------------------------------------------------------------------------// 1. If chip is in run mode => Stop the chip
Address(Hex)
Value (Hex)
04
ReadData
Address(Hex)
Value (Hex)
04
WriteData
//------------------------------------------------------------------------// 2. To set AutoConfig
//------------------------------------------------------------------------////// 1.Read Register
Address(Hex)
Value (Hex)
07
ReadData
Address(Hex)
Value (Hex)
07
WriteData
//------------------------------------------------------------------------// 3. To unset AutoConfig
//------------------------------------------------------------------------////// 1.Read Register

Address(Hex)
Value (Hex)
07
ReadData
Address(Hex)
Value (Hex)
07
WriteData
//////////////////////////////////////////////////////////////////////////
// TO SET/UNSET AUTOSTART SEQUENCES
//////////////////////////////////////////////////////////////////////////
Address(Hex)
Value (Hex)
04
ReadData
Address(Hex)
Value (Hex)
04
WriteData
//------------------------------------------------------------------------// 2. To set AutoStart
//------------------------------------------------------------------------////// 1.Read Register
Address(Hex)
Value (Hex)
07
ReadData
Address(Hex)
Value (Hex)
07
WriteData
//------------------------------------------------------------------------// 3. To unset AutoStart
//------------------------------------------------------------------------////// 1.Read Register
Address(Hex)
Value (Hex)
07
ReadData
////// 2. LOGICAL AND the read data with 0xFD
WriteData = ReadData & 0xFD
Address(Hex)
Value (Hex)
07
WriteData
//////////////////////////////////////////////////////////////////////////
// TO READ STATUS REGISTERS SEQUENCES
//////////////////////////////////////////////////////////////////////////
Address(Hex)
Value (Hex)
04
ReadData
Address(Hex)
Value (Hex)
04
WriteData
//------------------------------------------------------------------------// 2. Read Global Status Register. If the value is > 0 => Everything is OK
// If the value in global status register is 0 => Read other registers for detai
l status
//------------------------------------------------------------------------// Address(Hex)
Value (Hex)
0C
Read
//------------------------------------------------------------------------// 3. Read ADC out of range real time status
// If Bit n is 1 => Channel n ADC Real Time High bit is set
// If Bit n+4 is 1 => Channel n ADC Real Time Low bit is set
// Refer to DataSheet for more detail
//------------------------------------------------------------------------// Address(Hex)
Value (Hex)
31
Read
61
Read
91
Read
C1
Read
//------------------------------------------------------------------------// 4. Read ADC out of range high latched status for each channel
//------------------------------------------------------------------------// Channel 1: If read data & 2 == 1 => ADC out of range high latched is set
//
Address(Hex)
Value (Hex)
31
Read
// Channel 2: If read data & 2 == 1 => ADC out of range high latched is set
//
Address(Hex)
Value (Hex)
61
Read
//
Address(Hex)
Value (Hex)
91
Read
//
Address(Hex)
Value (Hex)
C1
Read
//------------------------------------------------------------------------// 5. Read ADC out of range low latched status for each channel
//
Address(Hex)
Value (Hex)
31
Read
//
Address(Hex)
Value (Hex)
61
Read
//
Address(Hex)
Value (Hex)
91
Read
//
Address(Hex)
Value (Hex)
C1
Read
//------------------------------------------------------------------------// 6. Read G & H Input buffer overflow status for each channel
//
Address(Hex)
Value (Hex)
31
Read
//
Address(Hex)
Value (Hex)
61
Read
//
Address(Hex)
Value (Hex)
91
Read
//
Address(Hex)
Value (Hex)
C1
Read
//------------------------------------------------------------------------// 7. Read Fir Input buffer overflow status for each channel
//
Address(Hex)
Value (Hex)
31
Read
//
Address(Hex)
Value (Hex)
61
Read
//
Address(Hex)
Value (Hex)
91
Read
//
Address(Hex)
Value (Hex)
C1
Read
//////////////////////////////////////////////////////////////////////////
// TO CLEAR STATUS REGISTERS SEQUENCES
//////////////////////////////////////////////////////////////////////////
Address(Hex)
04
Value (Hex)
ReadData

Address(Hex)
Value (Hex)
04
WriteData
//------------------------------------------------------------------------// 1. Clear channel status registers
//------------------------------------------------------------------------////// 1.Read Register
Address(Hex)
Value (Hex)
31
ReadData
Address(Hex)
Value (Hex)
31
WriteData
Address(Hex)
Value (Hex)
61
ReadData
Address(Hex)
Value (Hex)
61
WriteData
Address(Hex)
Value (Hex)
91
ReadData
Address(Hex)
Value (Hex)
91
WriteData
Address(Hex)
Value (Hex)
C1
ReadData
Address(Hex)
Value (Hex)
C1
WriteData
/////////////////////////////////////////////////////////////////////////
// TO POWER UP/POWER DOWN A CHANNEL AFE SEQUENCES

//////////////////////////////////////////////////////////////////////////
Address(Hex)
Value (Hex)
04
ReadData
Address(Hex)
Value (Hex)
04
WriteData
//------------------------------------------------------------------------// 2. Only channels in the INACTIVE group can be powered UP or powered DOWN.
// All channels in the ACTIVE group have to be powered UP
//------------------------------------------------------------------------////// Read Register to find out if channel 1 is in active group
////// If ReadData LOGICAL AND with 1 is equal 0 then channel 1 is in INACTI
VE group
Address(Hex)
Value (Hex)
0B
ReadData
////// To Power Up channel 1
Address(Hex)
Value (Hex)
0A
ReadData
////// 2. LOGICAL OR the ReadData with 0x0F
WriteData = ReadData | 0x0F
Address(Hex)
Value (Hex)
0A
WriteData
////// To Power Down channel 1
Address(Hex)
Value (Hex)
0A
ReadData
////// 2. LOGICAL AND the read data with 0xF0
WriteData = ReadData & 0xF0
Address(Hex)
Value (Hex)
0A
WriteData
//////////////////////////////////////////////////////////////////////////
// TO ENABLE/DISABLE CHANNEL OUTPUT SEQUENCES
//////////////////////////////////////////////////////////////////////////

Address(Hex)
Value (Hex)
04
ReadData
Address(Hex)
Value (Hex)
04
WriteData
//------------------------------------------------------------------------// 2. Can only ENABLE/DISABLE output of channels in the ACTIVE group.
//------------------------------------------------------------------------////// Read Register to find out if channel 1 is in active group
////// If ReadData LOGICAL AND with 1 is equal 1 then channel 1 is in ACTIVE
group
Address(Hex)
Value (Hex)
0B
ReadData
////// To enable channel 1 output
Address(Hex)
Value (Hex)
0B
ReadData
////// 2. LOGICAL OR the ReadData with 0xF0
WriteData = ReadData | 0xF0
Address(Hex)
Value (Hex)
0B
WriteData
////// To disable channel 1 output
Address(Hex)
Value (Hex)
0B
ReadData
////// 2. LOGICAL AND the read data with 0x0F
WriteData = ReadData & 0x0F
Address(Hex)
Value (Hex)
0B
WriteData
//------------------------------------------------------------------------// 3. Set the fastest channel in the ACTIVE group based on Sample Frequency.
// Select the fastest channel of the OUTPUT ENABLED channels in the ACTIVE group
.
//------------------------------------------------------------------------////// Read Register to find out if channel 1 is in ACTIVE group
////// If ReadActiveData LOGICAL AND with 1 is equal 1 then channel 1 is in a
ctive group
Address(Hex)
Value (Hex)
0B
ReadActiveData
////// Read Register to find out if channel 1 output is ENABLED
////// If ReadEnabledData LOGICAL AND with 1 is equal 1 then channel 1 output

is enabled
Address(Hex)
Value (Hex)
0B
ReadEnabledData
////// Select the fastest channel of the output enabled channel in the active
group based on Sample Frequency
////// To set channel n to be the fastest channel where n is 0, 1, 2, 3 for c
hannel 1, 2, 3, 4 respectly
////// 1. Read Register
Address(Hex)
Value (Hex)
15
ReadData
////// 2. LOGICAL OR the read data with 0x1 shift left by (4 + n bits)
WriteData = ReadData | (0x1 << (4 + n)
////// 3. Write Register
Address(Hex)
Value (Hex)
15
WriteData
//////////////////////////////////////////////////////////////////////////
// SWITCH GROUPS SEQUENCES
//////////////////////////////////////////////////////////////////////////
Address(Hex)
Value (Hex)
04
ReadData
Address(Hex)
Value (Hex)
04
WriteData
//------------------------------------------------------------------------// 2. Switch group:
// - Note: when switching group. All output for the channels in that group will
be set
//
as defined in the C:\Documents and Settings\Owner\Desktop\ECG\filter\filte
r design\Stop_band_100_40_10.qfp
//
To enable/disable channel output, see the ENABLE/DISABLE channel output se
quences
// - Note that when switching group. All channels AFE Power in the INACTIVE gro
up will be set
//
as defined in the C:\Documents and Settings\Owner\Desktop\ECG\filter\filte
r design\Stop_band_100_40_10.qfp
//
To power up/power down channel AFE, see the POWER UP/POWER DOWN a channel
AFE sequences
//------------------------------------------------------------------------//------------------------------------------------------------------------// To Switch group 1 to active group, write the below values to registers
//-------------------------------------------------------------------------
Address(Hex)
09
0B
0A
13
14
15
Value (Hex)
13
11
31
03
15
49
//////////////////////////////////////////////////////////////////////////
// TO RESET THE REGISTER VALUES TO DEFAULT VALUES SEQUENCES
//////////////////////////////////////////////////////////////////////////
Address(Hex)
Value (Hex)
04
ReadData
Address(Hex)
Value (Hex)
04
WriteData
Address(Hex)
Value (Hex)
15
ReadData
Address(Hex)
Value (Hex)
15
WriteData
//------------------------------------------------------------------------// 2. Write reset values to the registers
//------------------------------------------------------------------------// Address(Hex)
Value (Hex)
00
00
01
A0
02
00
03
00
04
00
05
00
06
00
07
40
08
80
09
01
0A
00
0B
00
0C
00
0D
00
0E
00
0F
00
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
00
41
0A
00
10
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
09
00
00
00
01
00
00
00
10
00
F0
00
40
00
00
08
00
00
00
00
00
7F
00
3F
00
7F
00
3F
00
00
00
FF
01
00
FF
00
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
90
91
92
93
00
FF
01
00
FF
00
95
00
00
C0
00
00
00
80
10
00
F0
00
40
00
00
08
00
00
00
00
00
7F
00
3F
00
7F
00
3F
00
00
00
FF
01
00
FF
00
00
FF
01
00
FF
00
95
00
00
C0
00
00
00
80
10
00
F0
00
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
40
00
00
08
00
00
00
00
00
7F
00
3F
00
7F
00
3F
00
00
00
FF
01
00
FF
00
00
FF
01
00
FF
00
95
00
00
C0
00
00
00
80
10
00
F0
00
40
00
00
08
00
00
00
00
00
7F
00
3F
00
7F
00
3F
00
00
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
00
FF
01
00
FF
00
00
FF
01
00
FF
00
95
00
00
C0
00
00
00
80
00
00
0F
00
00
00

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//Copyright (c) 2006 Quickfilter Technologies, Inc

//------------------------------------------------------------------------// 3. Download configuration file

//------------------------------------------------------------------------// 4. Download G&H coefficients

//------------------------------------------------------------------------// 5. Download FIR coefficients

//------------------------------------------------------------------------// 9. Start the chip: turn ram_run_mode and sif_run_mode ON

////// 2. LOGICAL OR the ReadData with 0x01

//------------------------------------------------------------------------////// 1.Read Register

////// 2. LOGICAL AND the read data with 0xFE

// TO POWER UP/POWER DOWN A CHANNEL AFE SEQUENCES

//------------------------------------------------------------------------////// Set SifRunMode to 0

////// If ReadEnabledData LOGICAL AND with 1 is equal 1 then channel 1 output

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