LWG2-D Block Diagram (Discrete) Mobile CPU

A
LWG2-D
Block Diagram
(Discrete)
Mobile CPU
CLK GEN.
IDT CV125PA
Project code: 91.4Q801.001

PCB P/N
: 55.4Q801.XXX
REVISION
: 06210-2
(Hannstar, ACCL)
G792
Yonah 478
1.83G/2G/2.16G
4, 5
19
PCB STACKUP
TOP
TVO
HOST BUS
400/533/667MHz
LVDS
DDR2
533/667MHz
533 MHz
11,12
DDR2
Calistoga
Ver.:A3 :71.945PM.A0U / QK58
KI.94501.006 / SL8Z4
533/667MHz
533 MHz
6,7,8,9,10
PCI Express x16

M56 Ver.: B24
M52 Ver.: A12
M54 Ver.: A12
100MHz
Codec
29
G1432
TSP2220A
27
CARDBUS
1394
CardReader
1394
CONN
1D8V_S3
TPS51100
1D8V_S3
VCC
40
DDR_VREF_S0
3D3V_S0
40
2D5V_S0
APL5912-U
1D8V_S3
26
802.11A/B/G
MAXIM CHARGER
MAX8725
39
OUTPUTS
CHG_PWR
MS/MMC/SD
3 in 1
40
1D5V_S0
INPUTS
Ver. : B0, 71.ICH7M.A0U / QK65

KI.80101.017 / SL8YB
DCBATOUT
18V
4.0A
UP+5V
26
5V
100mA
30
CPU DC/DC
Giga LAN
29
BCM5789/5787M
TXFM
22
23
PCIEx1
OP AMP
29
1D05V_S0
Support
TypeII
27
Mini-PCI
Line Out
OUTPUTS
DCBATOUT
PCMCIA
SLOT
PWR SW
24,25
OP AMP
38
TPS51124
BOTTOM
ICH7M
INT.SPKR
SYSTEM DC/DC
APL5332KAC
28
INT.MIC
29
GND
TI
PCI 7412
PCI BUS
3D3V_S5
ALC883
MIC In
5V_S5
DCBATOUT
42,43,44,45
PCMCIA I/F
AZALIA
OUTPUTS
14
128/256M
DMI I/F
INPUTS
CRT
37
TPS51120
INPUTS
GND
14"WSXGA+
LCD
13
RGB CRT
ATI
M54P / M52P
14
VRAM x4
47,48
11,12
SYSTEM DC/DC
Mini Card*1
802.11A/B/G
MAX441129
SPI I/F
RJ45
23
ISL6262
BCM5787MKFBG-A1
BCM5789KFBG-C1
BCM4401EKFBG-B0
INPUTS
26
DCBATOUT
35, 36
OUTPUTS
VCC_CORE_S0
0~1.3V
44A
BIOS
SST25LF080A
RJ11
MODEM
MDC Card
15,16,17,18
LPC BUS
34
ATI M54 DC/DC

FAN5234
49
PATA
SATA
USB
21
KBC
Renesas
USB
RE144B
3 PORT
21
LPC
30
INPUTS
OUTPUTS
DCBATOUT
VGA_CORE_S0
DEBUG
CONN.32
APL5331KAC
1D8V_S0
21
Finger
Print
HDD
20
20
CDROM
20
MINI USB
Blue-tooth
Touch
Pad 31
INT.
KB 31
43
1D2V_S0
<Variant Name>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLOCK DIAGRAM
Size
A3
Document Number
Date: Wednesday, June 21, 2006
Rev
LWG2
SA
Sheet
of
52
ICH7M Integrated Pull-up

and Pull-down Resistors
ICH7-M EDS 17837
C
1.5V1
EE_DIN, EE_DOUT, GNT[3:0], GPIO[25],

GNT[4]#/GPIO48, GNT[5]#/GPO17, PME#,
954305D 27Mhz/LCDCLK Spread

and Frequency Selection Table
SS3
Byte9
bit 7
0
SS2
bit6
SS1
bit5
SS0
bit4
-0.50 Down
page 3
Spread Amount%
Calistoga Strapping Signals and

EDS 17050 0.71
Configuration
page 7
Configuration
Pin Name
Strap Description
CFG[2:0]
FSB Frequency Select

001 = FSB533
011 = FSB667
others = Reserved
ICH7 internal 20K pull-ups
LAD[3:0]#/FHW[3:0]#, LAN_RXD[2:0]
-1.00 Down
LDRQ[0], LDRQ[1]/GPIO[41],
-1.50 Down
CFG[4:3]
Reserved
PWRBTN#, TP[3]
-2.00 Down
CFG5
DMI x2 Select
DD[7], DDREQ
-0.75 Down
CFG6
-1.25 Down
CFG7
-1.75 Down
-2.25 Down
4
0 = DMI x2
1 = DMI x4
(Default)
Reserved
ICH7 internal 11.5K pull-downs

0 = Reserved
1 =Mobile CPU(Default)
CPU Strap
ACZ_BIT_CLK, ACZ_RST#, ACZ_SDIN[2:0],
ICH7 internal 20K pull-downs
Reserved
ACZ_SDOUT, ACZ_SYNC, DPRSLPVR/GPIO16,
EE_CS,SPI_ARB, SPI_CLK, SPKR,
+-0.25 Center
+-0.5 Center
+-0.75 Center
+-1.0 Center
CFG8
CFG9
USB[7:0][P,N]
ICH7 internal 15K pull-downs
SATALED#
ICH7 internal 15K pull-up
CFG[11:10]
LAN_CLK
+-0.25 Center
+-0.5 Center
+-0.75 Center
+-1.0 Center
PCI Routing
DD[15:0], DIOW#, DIOR#, DREQ,

approximately 33 ohm
ICH7M Functional Strap Definitions

Signal
ACZ_SDOUT
page 16
Comment
Usage/When Sampled
XOR Chain Entrance/
PCIE Port Config bit1,
Rising Edge of PWROK
Allows entrance to XOR Chain testing when TP3

pulled low.When TP3 not pulled low at rising edge
of PWROK,sets bit1 of RPC.PC(Config Registers:
offset 224h)
ACZ_SYNC
PCIE bit0,
Rising Edge of PWROK.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
EE_CS
Reserved
This signal should not be pull high.
EE_DOUT
Reserved
This signal should not be pull low.
GNT2#
Reserved
GNT3#
Top-Block
Swap Override.
Sampled low:Top-Block Swap mode(inverts A16 for

all cycles targeting FWH BIOS space).
Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
GNT5#/
GPIO17#,
GNT4#/
GPIO48
Boot BIOS Destination

Selection.
Controllable via Boot BIOS Destination bit

(Config Registers:Offset 3410h:bit 11:10).
GNT5# is MSB, 01-SPI, 10-PCI, 11-LPC.
CFG[15:14]
Reserved
CFG16
FSB Dynamic ODT
0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled (Default)
CFG17
Global R-comp Disable

(All R-comps)
0 = All R-comp Disable

1 = Normal Operation (Default)
CFG18
VCC Select
0 = 1.05V (Default)
1 = 1.5V
CFG19
DMI Lane Reversal
0 = Normal operation (Default):lane

Numbered in order
1 =Reverse Lane,4->0,3->1 ect...
00 = Reserved
01 = XOR mode enabled
10 = All Z mode enabled
11 = Normal Operation
(Default)
Reserved
7412
22
MiniPCI
21
LAN
23
A -> H
REQ/GNT
0
1
CFG20
SDVO/PCIE
Concurrent
SDVOCRTL
_DATA
SDVO Present
0 = Only SDVO or PCIE x1 is

operational (Default)
1 =SDVO and PCIE x1 are operating
simultaneously via the PEG port
0 = No SDVO Card present
(Default)
1= SDVO Card present
NOTE: All strap signals are sampled with respect to the leading
edge of the Calistoga GMCH PWORK in signal.
History
2
DPRSLPVR
Reserved
This signal should not be pull high.
GPIO25
Reserved.
Rising Edge of RSMRST#.
INTVRMEN
Integrated VccSus1_05
VRM Enable/Disable.
Always sampled.
Reserved
Requires an external pull-up resistor.
XOR Chain Selection.

TBD, Chapter 8.
SATALED#
Reserved
Wistron Corporation
SPKR
No Reboot.
If sampled high, the system is strapped to the

"No Reboot" mode(ICH7 will disable the TCO Timer
system reboot feature). The status is readable
via the NO REBOOT bit.

LINKALERT#
REQ[4:1]#
CFG[13:12]
page 16
INT -> PIRQ

A->G, B->B,
C->F, D->G
A/C -> E
B/D -> E
DCS3#, IDEIRQ
Reserved
IORDY, DA[2:0], DCS1#,
IDSEL
0 = Reverse Lanes,15->0,14->1 ect..

1= Normal operation(Default):Lane
Numbered in order
XOR/ALL Z test
straps
ICH7 internal 100K pull-down
ICH7M IDE Integrated Series

Termination Resistors
DDACK#,
PCI Express Graphics

Lane Reversal
TP3
XOR Chain Entrance.

Enables integrated VccSus1_05 VRM when

sampled high
This signal should not be pull low unless using

XOR Chain testing.
<Variant Name>
Title
Reference
Size
A3
Document Number
Date: Saturday, June 10, 2006
Rev
LWG2
SA
Sheet
of
52
3D3V_S0
R155 1
2
0R0603-PAD
3D3V_CLKGEN_S0
3D3V_48MPWR_S0
R213 1
2
0R0603-PAD
3D3V_CLKPLL_S0
R158 1
2
0R0603-PAD
3D3V_S0
3D3V_S0
C257
C254
C230
C255
C303
C258
C508
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
C226
SC4D7U10V5ZY-3GP
C301
SC1U6D3V2ZY-GP
C229
SC1U6D3V2ZY-GP
C228
SCD1U16V2ZY-2GP
3D3V_S0
U24
R598
10KR2J-3-GP
30
51
25
32
SS_SEL
R173
R176
R179
R209
PCLK_KBC
PCLK_LAN
PCLK_PCM
PCLK_FWH
H/L: 100/96MHz
16 PM_STPPCI#
33R2J-2-GP
33R2J-2-GP
33R2J-2-GP
33R2J-2-GP
PCLKCLK0
PCLKCLK1_LAN
PCLKCLK2
PCLKCLK3
SS_SEL
ITP_EN
2 33R2J-2-GP
1
2
R174
10KR2J-3-GP
56
3
4
5
9
8
PCI0
PCI1
PCI2
PCI3
PCIF1/SEL100/96#
PCIF0/ITP_EN
55
PCI_STOP#
46
47
SCL
SDA
H/L : CPU_ITP/SRC7
DY
2
2
2
2
R211 1
16 CLK_ICHPCI
R597
10KR2J-3-GP
1
1
1
1
PCLK_FWH & PCLK_PCM

need equal length
11,18 SMBC_ICH
11,18 SMBD_ICH
14
15
GEN_XTAL_OUT_R
X2
R154
X-14D31818M-31GP16
82.30005.831
C225
1
GEN_XTAL_IN
SC27P50V2JN-2-GP
C256
1
CLK_ICH14
R181 1
GEN_XTAL_OUT
470R2J-2-GP
50
49
2 33R2J-2-GP GEN_REF
52
2
1GEN_IREF 39
475R2F-L1-GP
R157
3D3V_S0
10
XTAL_IN
XTAL_OUT
REF
IREF
VTT_PWRGD#/PD
-2 modify
2
R212
10KR2J-3-GP
35
CLK_EN#
DY
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
RN21
1
2
4 SRN33J-5-GP-U
3
CLK_PCIE_ICH 16
CLK_PCIE_ICH# 16
RN40
2
1
SRN33J-5-GP-U
GIGA
3
4
CLK_PCIE_LAN 22
CLK_PCIE_LAN# 22
RN25
2
1
SATA
3
4
SRN33J-5-GP-U
CLK_PCIE_SATA 15
CLK_PCIE_SATA# 15
1
2
MINIC
4 SRN33J-5-GP-U
3
1
2
VGA
4 SRN33J-5-GP-U
3
CLK_PCIE_PEG 42
CLK_PCIE_PEG# 42
19
20
22
23
24
25
26
27
31
30
33
32
CLK_MCH_3GPLL_1
CLK_MCH_3GPLL_1#
CLK_PCIE_ICH_1
CLK_PCIE_ICH_1#
CLK_PCIE_LAN_1
CLK_PCIE_LAN_1#
CLK_PCIE_SATA_1
CLK_PCIE_SATA_1#
CLK_PCIE_MINI1_1
CLK_PCIE_MINI1_1#
RN27
CPU2_ITP/SRC7
CPU2_ITP#/SRC7#
36
35
CLK_PCIE_PEG_1
CLK_PCIE_PEG_1#
RN28
CPU0
CPU0#
CPU1
CPU1#
44
43
41
40
CLK_CPU_BCLK_1
CLK_CPU_BCLK_1#
RN17
3
4
2 SRN33J-5-GP-U
1
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
RN19
3
4
2 SRN33J-5-GP-U
1
CPU_STOP#
FSC/TEST_SEL
FSB/TEST_MODE
USB48/FSA
54
53
16
12
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
PM_STPCPU# 16
VSS_PCI
VSS_PCI
VDD_SRC
VDD_SRC
34
21
51
45
38
13
29
VSS_REF
VSS_CPU
VSSA
VSS48
VSS_SRC
VDD_PCI
VDD_PCI
7
1
VDD_REF
VDD_CPU
VDDA
VDD48
VDD_SRC
48
42
37
11
28
IDTCV125PAG-GP
4 SRN33J-5-GP-U
3
SRC1
SRC1#
SRC2
SRC2#
SRC3
SRC3#
SRC4
SRC4#
SRC5
SRC5#
SRC6
SRC6#
2
6
1
2
LVDS
LVDS#
SC27P50V2JN-2-GP
DOT96
DOT96#
RN35
17
18
CLK_MCH_BCLK_1
CLK_MCH_BCLK_1#
CPU_SEL2
CPU_SEL1
CLK48
22R2J-2-GP 1 R601
2
22R2J-2-GP 1 R600
2
1 R602
2
3D3V_CLKGEN_S0 2K2R2J-2-GP
CLK_PCIE_MINI1 26
CLK_PCIE_MINI1# 26
Dummy when use UMA
CPU_SEL2 4,7
CPU_SEL1 4,7
CLK48_ICH 16
CLK48_CARDBUS
CPU_SEL0 4,7
25
3D3V_CLKPLL_S0
3D3V_48MPWR_S0
2
71.00125.A0W
EMI capacitor
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
SEL2
SEL1
SEL0
CPU
FSB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
266M
133M
200M
166M
333M
100M
400M
Reserved
X
533M
X
667M
X
X
X
X
RN34
CLK_PCIE_MINI1
1
CLK_PCIE_MINI1#
2 MINIC
SRN49D9F-GP
RN42
CLK_PCIE_LAN
2
CLK_PCIE_LAN#
1 GIGA
SRN49D9F-GP
RN32
CLK_PCIE_SATA
2
CLK_PCIE_SATA#
1 SATA
SRN49D9F-GP
RN20
CLK_PCIE_ICH
1
CLK_PCIE_ICH#
2
SRN49D9F-GP
4
3
CLK_ICH14
RN18
3
4
CLK_CPU_BCLK
1
CLK_CPU_BCLK#
2
SRN49D9F-GP
3
4
CLK_MCH_BCLK
1
CLK_MCH_BCLK#
2
SRN49D9F-GP
CLK_ICHPCI
4
3
CLK48_ICH
RN16
RN31
CLK_PCIE_PEG
1
CLK_PCIE_PEG#
2 VGA
SRN49D9F-GP
RN36
CLK_MCH_3GPLL
1
CLK_MCH_3GPLL#
2
SRN49D9F-GP
4
3
4
3
1
EC20
1
EC18
2 DY
SC22P50V2JN-4GP
2 DY
SC22P50V2JN-4GP
1
EC17
1
EC21
1
EC34
2 DY
SC22P50V2JN-4GP
2 DY
SC22P50V2JN-4GP
2 DY
SC22P50V2JN-4GP
<Variant Name>
4
3
Wistron Corporation
4
3
Title
Clock Generator IDT CVT125PAG

Size
A3
Document Number

A
Rev
LWG2
SA
Sheet
E
of
52
TP27 TPAD30
U72A
D5
C6
B4
A3
STPCLK#
LINT0
LINT1
SMI#
AA1
AA4
AB2
AA3
M4
N5
T2
V3
B2
C3
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
RSVD[10]
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TP37
TP31
TP36
TP35
TP26
TP25
TP34
TP32
TPAD30
TP19
TPAD30
TP14
B25
1
2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
PROCHOT#
THERMDA
THERMDC
D21
A24
A25
XDP/ITP SIGNALS
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
THERMTRIP#
RSVD[11]
H_TRDY# 6
H_HIT#
H_HITM#
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
TP41
TP44
TP46
TP40
TP43
TP47
TP39
TP30
TP33
TP29
TP42
TP18
H_THERMDA
6
6
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
H_THERMDC
BCLK[0]
BCLK[1]
A22
A21
RSVD[12]
T22
TP28 TPAD30
RSVD[13]
RSVD[14]
RSVD[15]
RSVD[16]
RSVD[17]
RSVD[18]
RSVD[19]
RSVD[20]
D2
F6
D3
C1
AF1
D22
C23
C24
TP20 TPAD30
TP24 TPAD30
R596 2
0R2J-2-GP
TPAD30
TPAD30
TPAD30
TPAD30
PM_THRMTRIP-I# 33
PM_THRMTRIP#
should connect to
ICH7 and Calistoga
without T-ing
( No stub)
1D05V_S0
R628
1KR2F-3-GP
Layout Note:
0.5" max length.
6
6
6
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
CPU_GTLREF0
R627
2KR2F-3-GP
BGA479-SKT6-GPU2
62.10079.001
CPU_PROCHOT# 35
DY
CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3
TP45
TP17
TP16
TP15
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
6 H_DSTBN#0
6 H_DSTBP#0
6 H_DINV#0
R595
56R2J-4-GP
1 R605
2
0R0402-PAD
C675
SC2200P50V2KX-2GP
1D05V_S0
H_THERMDA 19
H_THERMDC 19
PM_THRMTRIP-A# 7
C7
H_D#[63..0]
U72B
6
2nd source: 62.10053.401
C321
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
M24
N25
M26
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
AD26
R614 1KR2J-1-GP
DYTEST1
2
1
1
2TEST2
R615 51R2F-2-GP
3,7
3,7
3,7
E22
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
H23
G22
J26
CPU_SEL0
CPU_SEL1
CPU_SEL2
C26
GTLREF
TEST2
B22
B23
C21
BSEL[0]
BSEL[1]
BSEL[2]
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
W24
Y25
V23
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
AD23
AE24
AC20
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP[0]
COMP[1]
COMP[2]
COMP[3]
R26
U26
U1
V1
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
E5
B5
D24
D6
D7
AE6
MISC
TEST1
D25
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
DATA GRP 2
HIT#
HITM#
H_LOCK# 6
H_CPURST# 6
H_RS#[2..0]
H_RS#0
H_RS#1
H_RS#2
B1
F3
F4
G3
G2
H4
LOCK#
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
H_IERR#
H_INIT# 15
CONTROL
D20
B3
H_DINV#[3..0] 6
H_DSTBN#[3..0] 6
H_DSTBP#[3..0] 6
Place testpoint on
H_IERR# with a GND
0.1" away
DATA GRP 3
15 H_STPCLK#
15 H_INTR
15 H_NMI
15 H_SMI#
H_BREQ#0 6
SC1KP16V2KX-GP
2
1
A20M#
FERR#
IGNNE#
F1
A6
A5
C4
H_DEFER# 6
H_DRDY# 6
H_DBSY# 6
R613
56R2J-4-GP
DATA GRP 1
15 H_A20M#
15 H_FERR#
15 H_IGNNE#
6
6
6
1 2
6 H_ADSTB#1
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
ADSTB[1]#
H_ADS#
H_BNR#
H_BPRI#
H5
F21
E1
IERR#
INIT#
THERM
Y2
U5
R3
W6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
W2
Y1
V4
BR0#
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
ADDR GROUP 1
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
DEFER#
DRDY#
DBSY#
H1
E2
G5
DATA GRP 0
H_REQ#0 K3
H_REQ#1 H2
H_REQ#2 K2
H_REQ#3 J3
H_REQ#4 L5
ADS#
BNR#
BPRI#
H CLK
6 H_ADSTB#0
6 H_REQ#[4..0]
1D05V_S0
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
RESERVED
J4
L4
M3
K5
M1
N2
J1
N3
P5
P2
L1
P4
P1
R1
L2
ADDR GROUP 0
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
6 H_A#[31..3]
H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6
H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6
COMP0
COMP1
COMP2
COMP3
R6301
R6291
R2871
R2861
2
2
2
2
27D4R2F-L1-GP
54D9R2F-L1-GP
27D4R2F-L1-GP
54D9R2F-L1-GP
H_DPRSLP# 15,35
H_DPSLP# 15
H_DPWR# 6
H_PWRGD 15,33
H_CPUSLP# 6,15
PSI#
35
BGA479-SKT6-GPU2
XDP_TDI
R284 1
XDP_TMS
R282 1
XDP_TDO
R283 1
H_CPURST#
R606 1
Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .
<NO_STUFF>
1D05V_S0
2 150R2F-1-GP
2 39D2R3F-2-GP
DY
DY
2 54D9R2F-L1-GP
2 54D9R2F-L1-GP
3D3V_S0
XDP_DBRESET# R207 1
DY
2 150R2F-1-GP
XDP_TCK
R299 1
2 27D4R2F-L1-GP
XDP_TRST#
R301 1
2 680R3F-GP
<Variant Name>
Wistron Corporation
Title
All place within 2" to CPU
CPU (1 of 2)
Size
A3
Document Number

A
Rev
LWG2
SA
Sheet
E
of
52
VCC_CORE_S0
U72D
VCC_CORE_S0
A4
A8
A11
A14
A16
A19
A23
A26
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
U72C
AE7
VSS_SENSE 35
VCC_CORE_S0
DY
VCCSENSE and VSSSENSE lines

should be of equal length.
Layout Note:
R298
100R2F-L1-GP-U
Layout Note:
Provide a test point (with
no stub) to connect a
differential probe
between VCCSENSE and
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.
C700
C365
C341
C676
C680
C682
SC10U10V5ZY-1GPSC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C716
<NO_STUFF>
VCC_SENSE 35
VSSSENSE
BGA479-SKT6-GPU2
C364
C363
C348
C347
C342
C340
C711
C368
SCD1U10V2KX-4GPSCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
SCD1U10V2KX-4GPSCD1U10V2KX-4GPSCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
C674
H_VID0 35
SCD01U16V2KX-3GP
H_VID1 35
VCC_CORE_S0
H_VID2 35
H_VID3 35
H_VID4 35
H_VID5 35
R300
H_VID6 35
100R2F-L1-GP-U
H_VID[0..6] 35
AF7
1D05V_S0
1
2
HCB1608KF121T30-GP
68.00230.041
C673
SC4D7U6D3V3KX-GP
VCCSENSE
1D5V_S0
L22
AD6
AF5
AE5
AF4
AE3
AF2
AE2
1D5V_VCCA_S0
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
C369
SCD1U10V2KX-4GP
B26
1 R285
2
0R0402-PAD
VCCA
CPU_V6
V6
G21
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
Layout Note
1D05V_S0
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
AF3
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF24
BGA479-SKT6-GPU2
<NO_STUFF>
<Variant Name>

DY
DY
DY
DY
Title
CPU (2 of 2)
C715
C346
C344
C343
C701
C713
C702
C714
C703
C677
C370
C683
C712
C366
C678
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
Size
A3
Document Number

A
Wistron Corporation
2
VCC_CORE_S0
Rev
LWG2
SA
Sheet
E
of
52
H_XRCOMP
H_XSWING
R644
100R2F-L1-GP-U
1
2
C743
SCD1U16V2ZY-2GP
H_YRCOMP
R639
24D9R2F-L-GP
1D05V_S0
R642
54D9R2F-L1-GP
H_YSCOMP
1D05V_S0
3 CLK_MCH_BCLK
3 CLK_MCH_BCLK#
E1
E2
E4
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
Y1
U1
W1
H_YRCOMP
H_YSCOMP
H_YSWING
AG2
AG1
H_CLKIN
H_CLKIN#
1D05V_S0
R274
100R2F-L1-GP-U
H_ADS#
4
H_ADSTB#0 4
H_ADSTB#1 4
H_VREF
H_BNR# 4
H_BPRI# 4
H_BREQ#0 4
H_CPURST# 4
H_DBSY# 4
H_DEFER# 4
H_DPWR# 4
H_DRDY# 4
J7
W8
U3
AB10
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
K4
T7
Y5
AC4
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
K3
T6
AA5
AC5
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_HIT#
H_HITM#
H_LOCK#
D3
D4
B3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
D8
G8
B8
F8
A8
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#_0
H_RS#_1
H_RS#_2
B4
E6
D6
H_RS#0
H_RS#1
H_RS#2
H_SLPCPU#
H_TRDY#
E3
E7
R246
200R2F-L-GP
C362
SCD1U16V2ZY-2GP
H_DINV#[3..0]
H_DSTBN#[3..0]
H_DSTBP#[3..0]
H_HIT#
4
H_HITM# 4
H_LOCK# 4
H_REQ#[4..0]
H_RS#[2..0]
1 R646
2
0R0402-PAD
H_CPUSLP# 4,15
H_TRDY# 4
CALISTOGA
C741
SCD1U16V2ZY-2GP
R640
100R2F-L1-GP-U
E8
B9
C13
J13
C6
F6
C7
B7
A7
C3
J9
H8
K13
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_YSWING
R641
221R2F-2-GP
H_XRCOMP
H_XSCOMP
H_XSWING
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_VREF_0
H_BNR#
H_BPRI#
H_BREQ#0
H_CPURST#
H_DBSY#
H_DEFER#
H_DPWR#
H_DRDY#
H_VREF_1
R645
221R2F-2-GP
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
1D05V_S0
H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14
H_XSCOMP
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
R647
54D9R2F-L1-GP
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
1D05V_S0
F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
K11
G4
T10
W11
T3
U7
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
AB8
W2
AA4
AA7
AA2
AA6
AA10
Y8
AA1
AB4
AC9
AB11
AC11
AB3
AC2
AD1
AD9
AC1
AD7
AC6
AB5
AD10
AD4
AC8
HOST
H_A#[31..3]
U71A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
4 H_D#[63..0]
R643
24D9R2F-L-GP
Place them near to the chip ( < 0.5")
<Variant Name>
Wistron Corporation
Title
GMCH (1 of 5)
Size
A3
Document Number

A
Rev
LWG2
SA
Sheet
E
of
52
SM_CK#_0
SM_CK#_1
SM_CK#_2
SM_CK#_3
11,12
11,12
11,12
11,12
M_CKE0
M_CKE1
M_CKE2
M_CKE3
AU20
AT20
BA29
AY29
SM_CKE_0
SM_CKE_1
SM_CKE_2
SM_CKE_3
11,12
11,12
11,12
11,12
M_CS0#
M_CS1#
M_CS2#
M_CS3#
AW13
AW12
AY21
AW21
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
M_OCDCOMP0
M_OCDCOMP1
M_ODT0
M_ODT1
M_ODT2
M_ODT3
M_RCOMPN
M_RCOMPP
BA13
BA12
AY20
AU21
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
SM_VREF_0
SM_VREF_1
AF33
AG33
A27
A26
C40
D41
G_CLKIN#
G_CLKIN
D_REFCLKIN#
D_REFCLKIN
D_REFSSCLKIN#
D_REFSSCLKIN
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
AE35
AF39
AG35
AH39
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
AC35
AE39
AF35
AG39
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
AE37
AF41
AG37
AH41
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
AC37
AE41
AF37
AG41
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
16 DMI_RXN[3..0]
PM_BMBUSY#
PM_EXTTS#_0
PM_EXTTS#_1
PM_THRMTRIP#
PWROK
RSTIN#
SDVO_CTRLCLK
SDVO_CTRLDATA
LT_RESET#
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC
16 DMI_RXP[3..0]
MISC
16 DMI_TXP[3..0]
PM
16 DMI_TXN[3..0]
CLK
DMI
3 CLK_MCH_3GPLL#
3 CLK_MCH_3GPLL
C737
C667
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
SEL2
SEL1
SEL0
CPU
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
266M
133M
200M
166M
333M
100M
400M
Reserved
H28
H27
K28
TP13 TPAD30
TP12 TPAD30
MCH_ICH_SYNC#
D1
C41
C1
BA41
BA40
BA39
BA3
BA2
BA1
B41
B2
AY41
AY1
AW41
AW1
A40
A4
A39
A3
16
3D3V_S0
R2542
DUMMY-R2
R2422
DUMMY-R2
R2412
1
DUMMY-R2
R2492
1
DUMMY-R2
R2552
1
DUMMY-R2
R2472
1
DUMMY-R2
R2602
1
DUMMY-R2
R2532
1
DUMMY-R2
R2522
1
DUMMY-R2
R2592
1
DUMMY-R2
R2512
1
DUMMY-R2
1 R256
2
DY
2K2R2J-2-GP
R2772
1
DUMMY-R2
R2752
1
DUMMY-R2
R2482
1
DUMMY-R2
R2582
1
DUMMY-R2
R2502
1
DUMMY-R2
R2762
1
DUMMY-R2
RN43
1
2
4
3
SRN10KJ-5-GP
1D8V_S3
PM_EXTTS#0
PM_EXTTS#1
M_RCOMPN
R271
80D6R2F-L-GP
M_RCOMPP
R272
80D6R2F-L-GP
C37
B35
A37
LA_DATA#_0
LA_DATA#_1
LA_DATA#_2
B37
B34
A36
LA_DATA_0
LA_DATA_1
LA_DATA_2
G30
D30
F29
LB_DATA#_0
LB_DATA#_1
LB_DATA#_2
F30
D29
F28
LB_DATA_0
LB_DATA_1
LB_DATA_2
A16
C18
A19
TV_DACA_OUT
TV_DACB_OUT
TV_DACC_OUT
J20
B16
B18
B19
TV_IREF
TV_IRTNA
TV_IRTNB
TV_IRTNC
E23
D23
C22
B22
A21
B21
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
C26
C25
G23
J22
H23
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_IREF
CRT_VSYNC
1D05V_S0
RN97
SRN10KJ-5-GP
GMCH_DDCCLK
GMCH_DDCDATA
3D3V_S0
LA_CLK#
LA_CLK
LB_CLK#
LB_CLK
DY
G28
PM_BMBUSY# 16R237
1
2
F25 PM_EXTTS#0
VGATE_PWRGD 16,35,45
0R2J-2-GP
H26 PM_EXTTS#1
1 R239
2
G6
PM_THRMTRIP-A# 4
PWROK
16,19
0R0402-PAD
AH33
R238
1
2
AH34
PLT_RST1# 16,20,22,26,30,32,42
1D5V_S0
100R2J-2-GP
CALISTOGA
3D3V_S0
A33
A32
E27
E26
VGA
SM_RCOMP#
SM_RCOMP
AK1
AK41
CPU_SEL0 3,4
CPU_SEL1 3,4
CPU_SEL2 3,4
L_BKLTCTL
L_BKLTEN
L_CLKCTLA
L_CLKCTLB
L_DDC_CLK
L_DDC_DATA
L_IBG
L_VBG
L_VDDEN
L_VREFH
L_VREFL
TV
AV9
AT9
DDR_VREF_S3
SM_OCDCOMP_0
SM_OCDCOMP_1
K16
K18
J18
F18
E15
F15
E18
D19
D16
G16
E16
D15
G15
K15
C15
H16
G18
H15
J25
K27
J26
U71C
D32
J30
H30
H29
G26
G25
B38
C35
F32
C33
C32
LVDS
R244
R273
11,12
40D2R2F-GP 40D2R2F-GP
11,12
DY
DY
11,12
11,12
AL20
AF10
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
1D5V_PCIE_S0
CFG18
CFG19
GRAPHICS
AW35
AT1
AY7
AY40
PCI-EXPRESS
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3
4
3
11
11
11
11
MUXING
SM_CK_0
SM_CK_1
SM_CK_2
SM_CK_3
DDR
AY35
AR1
AW7
AW40
M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3
CFG
11
11
11
11
U71B
RSVD_0 H32
RSVD_1 T32
RSVD_2 R32
RSVD_3 F3
RSVD_4 F7
RSVD_5 AG11
RSVD_6 AF11
RSVD_7 H7
RSVD_8 J19
RSVD_9 K30
RSVD_10 J29
RSVD_11 A41
RSVD_12 A35
RSVD_13 A34
RSVD_14 D28
RSVD_15 D27
RSVD
1
2
EXP_A_COMPI
EXP_A_COMPO
D40
D38
EXP_A_RXN_0
EXP_A_RXN_1
EXP_A_RXN_2
EXP_A_RXN_3
EXP_A_RXN_4
EXP_A_RXN_5
EXP_A_RXN_6
EXP_A_RXN_7
EXP_A_RXN_8
EXP_A_RXN_9
EXP_A_RXN_10
EXP_A_RXN_11
EXP_A_RXN_12
EXP_A_RXN_13
EXP_A_RXN_14
EXP_A_RXN_15
F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
EXP_A_RXP_0
EXP_A_RXP_1
EXP_A_RXP_2
EXP_A_RXP_3
EXP_A_RXP_4
EXP_A_RXP_5
EXP_A_RXP_6
EXP_A_RXP_7
EXP_A_RXP_8
EXP_A_RXP_9
EXP_A_RXP_10
EXP_A_RXP_11
EXP_A_RXP_12
EXP_A_RXP_13
EXP_A_RXP_14
EXP_A_RXP_15
D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
EXP_A_TXN_0
EXP_A_TXN_1
EXP_A_TXN_2
EXP_A_TXN_3
EXP_A_TXN_4
EXP_A_TXN_5
EXP_A_TXN_6
EXP_A_TXN_7
EXP_A_TXN_8
EXP_A_TXN_9
EXP_A_TXN_10
EXP_A_TXN_11
EXP_A_TXN_12
EXP_A_TXN_13
EXP_A_TXN_14
EXP_A_TXN_15
F36 GTXN0
G40 GTXN1
H36 GTXN2
J40 GTXN3
L36 GTXN4
M40 GTXN5
N36 GTXN6
P40 GTXN7
R36 GTXN8
T40 GTXN9
V36 GTXN10
W40 GTXN11
Y36 GTXN12
AA40 GTXN13
AB36 GTXN14
AC40 GTXN15
EXP_A_TXP_0
EXP_A_TXP_1
EXP_A_TXP_2
EXP_A_TXP_3
EXP_A_TXP_4
EXP_A_TXP_5
EXP_A_TXP_6
EXP_A_TXP_7
EXP_A_TXP_8
EXP_A_TXP_9
EXP_A_TXP_10
EXP_A_TXP_11
EXP_A_TXP_12
EXP_A_TXP_13
EXP_A_TXP_14
EXP_A_TXP_15
D36 GTXP0
F40 GTXP1
G36 GTXP2
H40 GTXP3
J36 GTXP4
L40 GTXP5
M36 GTXP6
N40 GTXP7
P36 GTXP8
R40 GTXP9
T36 GTXP10
V40 GTXP11
W36 GTXP12
Y40 GTXP13
AA36 GTXP14
AB40 GTXP15
PEG_RXP[15..0] 42
42
PEG_TXN[15..0]
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
PEG_TXN0
SCD1U16V2KX-3GP
PEG_TXN1
SCD1U16V2KX-3GP
PEG_TXN2
SCD1U16V2KX-3GP
PEG_TXN3
SCD1U16V2KX-3GP
PEG_TXN4
SCD1U16V2KX-3GP
PEG_TXN5
SCD1U16V2KX-3GP
PEG_TXN6
SCD1U16V2KX-3GP
PEG_TXN7
SCD1U16V2KX-3GP
PEG_TXN8
SCD1U16V2KX-3GP
PEG_TXN9
SCD1U16V2KX-3GP
PEG_TXN10
SCD1U16V2KX-3GP
PEG_TXN11
SCD1U16V2KX-3GP
PEG_TXN12
SCD1U16V2KX-3GP
PEG_TXN13
SCD1U16V2KX-3GP
PEG_TXN14
SCD1U16V2KX-3GP
42 PEG_TXN15PEG_TXP[15..0]
SCD1U16V2KX-3GP
PEG_TXP0
SCD1U16V2KX-3GP
PEG_TXP1
SCD1U16V2KX-3GP
PEG_TXP2
SCD1U16V2KX-3GP
PEG_TXP3
SCD1U16V2KX-3GP
PEG_TXP4
SCD1U16V2KX-3GP
PEG_TXP5
SCD1U16V2KX-3GP
PEG_TXP6
SCD1U16V2KX-3GP
PEG_TXP7
SCD1U16V2KX-3GP
PEG_TXP8
SCD1U16V2KX-3GP
PEG_TXP9
SCD1U16V2KX-3GP
PEG_TXP10
SCD1U16V2KX-3GP
PEG_TXP11
SCD1U16V2KX-3GP
PEG_TXP12
SCD1U16V2KX-3GP
PEG_TXP13
SCD1U16V2KX-3GP
PEG_TXP14
SCD1U16V2KX-3GP
PEG_TXP15
SCD1U16V2KX-3GP
CALISTOGA
CFG20
CFG3
CFG4
When High 1K Ohm
CFG5
CFG6
CFG6:
CFG7
0=Moby Dick ,1=Calistoga (default)
CFG8
CFG9
CFG10
CFG11
When Low choice

lower than 3.5K
Ohm
<Variant Name>
1
CFG12
Wistron Corporation
CFG13

CFG14
When PM replace to GM
CFG15
Title
GMCH (2 of 5)
CFG16
Size
A3
CFG17
Document Number

A
1
C298
1
C297
1
C294
1
C293
1
C290
1
C289
1
C287
1
C284
1
C283
1
C280
1
C279
1
C248
1
C277
1
C245
1
C275
1
C273
1
C300
1
C299
1
C296
1
C295
1
C292
1
C291
1
C288
1
C286
1
C285
1
C282
1
C281
1
C249
1
C278
1
C247
1
C276
1
C274
R594
1
24D9R2F-L-GP
PEG_RXN[15..0] 42
Rev
LWG2
SA
Sheet
E
of
52
SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
AY13
AJ33
AM35
AL26
AN22
AM14
AL9
AR3
AH4
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
AK33
AT33
AN28
AM22
AN12
AN8
AP3
AG5
AK32
AU33
AN27
AM21
AM12
AL8
AN3
AH5
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
AY16
AU14
AW16
BA16
BA17
AU16
AV17
AU17
AW17
AT16
AU13
AT17
AV20
AV12
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
AW14
AK23
AK24
AY14
M_A_BS#0 11,12
M_A_BS#1 11,12
M_A_BS#2 11,12
M_A_CAS# 11,12
M_A_DM[7..0] 11
M_A_DQS[7..0] 11
M_A_DQS#[7..0] 11
M_A_A[13..0] 11,12
M_A_RAS# 11,12
SA_RCVENIN#
SA_RCVENOUT#
TP23 TPAD30
TP11 TPAD30
M_A_WE# 11,12
Place Test PAD Near to Chip

as could as possible
AU12
AV14
BA20
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
MEMORY
SA_BS_0
SA_BS_1
SA_BS_2
AK39
AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AJ9
AN10
AK13
AH11
AK10
AJ8
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ5
AJ3
SYSTEM
MEMORY
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
SYSTEM
AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AL5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AL2
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8
DDR
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
U71D
11 M_A_DQ[63..0]
U71E
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
DDR
11 M_B_DQ[63..0]
SB_BS_0
SB_BS_1
SB_BS_2
AT24
AV23
AY28
SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
AR24
AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
AM39
AT39
AU35
AR29
AR16
AR10
AR7
AN5
AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#
AU23
AK16
AK18
AR27
M_B_BS#0 11,12
M_B_BS#1 11,12
M_B_BS#2 11,12
M_B_CAS# 11,12
M_B_DM[7..0] 11
M_B_DQS[7..0] 11
M_B_DQS#[7..0] 11
M_B_A[13..0] 11,12
M_B_RAS# 11,12
SB_RCVENIN#
SB_RCVENOUT#
TP22 TPAD30
TP21 TPAD30
M_B_WE# 11,12
Place Test PAD Near to Chip

ascould as possible
CALISTOGA
CALISTOGA
<Variant Name>
Wistron Corporation
Title
GMCH (3 of 5)
Size
A3
Document Number

A
Rev
LWG2
SA
Sheet
E
of
52
U71H
F21
E21
G21
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
B26
C39
AF1
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
A38
B39
VCCA_LVDS
VSSA_LVDS
AF2
VCCA_MPLL
H20
G20
VCCA_TVBG
VSSA_TVBG
E19
F19
C20
D20
E20
F20
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
AH1
AH2
VCCD_HMPLL0
VCCD_HMPLL1
A28
B28
C28
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
D21
VCCD_TVDAC
A23
B23
B25
VCC_HV0
VCC_HV1
VCC_HV2
H19
VCCD_QTVDAC
1D5V_HPLL_S0
1D5V_S0
1D5V_MPLL_S0
1D5V_S0
1D5V_S0
L11
1D5V_HPLL_S0
1
2
HCB1608KF121T30-GP
68.00230.041
C400
2 R257
11D5V_TVDAC_S0
0R0603-PAD
C339
SCD1U10V2KX-4GP
C401
1D5V_S0
L30
2 R619
0R0603-PAD
1
1
3D3V_S0
1D5V_MPLL_S0
1
2
HCB1608KF121T30-GP
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
68.00230.041
C738
C739
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
C698
C697
SC10U10V5ZY-1GPSCD1U10V2KX-4GP
1D5V_S0
11D5V_QTVDAC_S0
C338
SCD1U10V2KX-4GP
2 R620
0R0603-PAD
1D5V_S0
1D5V_AUX
1
2
C334
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C330
SCD1U10V2KX-4GP
C314
SCD1U10V2KX-4GP
C336
1 R245
2
0R0805-PAD
AK31
AF31
AE31
AC31
AL30
AK30
AJ30
AH30
AG30
AF30
AE30
AD30
AC30
AG29
AF29
AE29
AD29
AC29
AG28
AF28
AE28
AH22
AJ21
AH21
AJ20
AH20
AH19
P19
P16
AH15
P15
AH14
AG14
AF14
AE14
Y14
AF13
AE13
AF12
AE12
AD12
POWER
VCCAUX0
VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
VCCAUX9
VCCAUX10
VCCAUX11
VCCAUX12
VCCAUX13
VCCAUX14
VCCAUX15
VCCAUX16
VCCAUX17
VCCAUX18
VCCAUX19
VCCAUX20
VCCAUX21
VCCAUX22
VCCAUX23
VCCAUX24
VCCAUX25
VCCAUX26
VCCAUX27
VCCAUX28
VCCAUX29
VCCAUX30
VCCAUX31
VCCAUX32
VCCAUX33
VCCAUX34
VCCAUX35
VCCAUX36
VCCAUX37
VCCAUX38
VCCAUX39
VCCAUX40
VCCP_GMCH_CAP3
VCCP_GMCH_CAP2
VCCP_GMCH_CAP1
C740
SCD47U10V3ZY-GP
Wistron Corporation
Title
GMCH (4 of 5)
Document Number

C
C744
SCD47U10V3ZY-GP
<Variant Name>
Size
A3
B
C710
SCD22U16V3ZY-GP
CALISTOGA
1
2
1D05V_S0
C332
C742
SC2D2U6D3V3MX-1-GP SC4D7U10V5ZY-3GP
2D5V_3GBG_S0
C361
SCD1U10V2KX-4GP
C315
SCD1U10V2KX-4GP
C671
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG
AC14
AB14
W14
V14
T14
R14
P14
N14
M14
L14
AD13
AC13
AB13
AA13
Y13
W13
V13
U13
T13
R13
N13
M13
L13
AB12
AA12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
L12
R11
P11
N11
M11
R10
P10
N10
M10
P9
N9
M9
R8
P8
N8
M8
P7
N7
M7
R6
P6
M6
A6
R5
P5
N5
M5
P4
N4
M4
R3
P3
N3
M3
R2
P2
M2
D2
AB1
R1
P1
N1
M1
SC4D7U6D3V3KX-GP
C668
VTT_0
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VTT_26
VTT_27
VTT_28
VTT_29
VTT_30
VTT_31
VTT_32
VTT_33
VTT_34
VTT_35
VTT_36
VTT_37
VTT_38
VTT_39
VTT_40
VTT_41
VTT_42
VTT_43
VTT_44
VTT_45
VTT_46
VTT_47
VTT_48
VTT_49
VTT_50
VTT_51
VTT_52
VTT_53
VTT_54
VTT_55
VTT_56
VTT_57
VTT_58
VTT_59
VTT_60
VTT_61
VTT_62
VTT_63
VTT_64
VTT_65
VTT_66
VTT_67
VTT_68
VTT_69
VTT_70
VTT_71
VTT_72
VTT_73
VTT_74
VTT_75
VTT_76
VCC_TXLVDS0
VCC_TXLVDS1
VCC_TXLVDS2
2
0R0603-PAD
C316
1
1
R240
C669
AJ41
AB41
Y41
V41
R41
N41
L41
AC33
G41
H41
1D05V_S0
VCCSYNC
C670
1D5V_3GPLL_S0
SC4D7U6D3V3KX-GP
2
1
1D5V_S0
SC4D7U6D3V3KX-GP
2
1
R592 1
2
0R0805-PAD
SCD1U10V2KX-4GP
2
1
1D5V_PCIE_S0
SC4D7U6D3V3KX-GP
2
1
1D5V_S0
C672
SCD1U10V2KX-4GP
2 R593
0R0603-PAD
C30
B30
A30
2D5V_S0
2D5V_3GBG_S0
H22
Rev
LWG2
SA
Sheet
E
of
52
1D05V_S0
AC41
AA41
W41
T41
VCC_NCTF0
P41
VCC_NCTF1
VSS_NCTF0 AE27
M41
VCC_NCTF2
VSS_NCTF1 AE26
J41
VCC_NCTF3
VSS_NCTF2 AE25
F41
VCC_NCTF4
VSS_NCTF3 AE24
AV40
VCC_NCTF5
VSS_NCTF4 AE23
AP40
VCC_NCTF6
VSS_NCTF5 AE22
AN40
VCC_NCTF7
VSS_NCTF6 AE21
AK40
VCC_NCTF8
VSS_NCTF7 AE20
AJ40
VCC_NCTF9
VSS_NCTF8 AE19
AH40
VCC_NCTF10
VSS_NCTF9 AE18
AG40
VCC_NCTF11
VSS_NCTF10 AC17
Y17
AF40
VCC_NCTF12
VSS_NCTF11
AE40
VCC_NCTF13
VSS_NCTF12 U17
B40
VCC_NCTF14
1D5V_AUX
AY39
VCC_NCTF15
AW39
VCC_NCTF16
AV39
VCC_NCTF17
AR39
VCC_NCTF18
AN39
VCC_NCTF19
VCCAUX_NCTF0 AG27
AJ39
VCC_NCTF20
VCCAUX_NCTF1 AF27
AC39
VCC_NCTF21
VCCAUX_NCTF2 AG26
AB39
VCC_NCTF22
VCCAUX_NCTF3 AF26
AG25
AA39
VCC_NCTF23
VCCAUX_NCTF4
Y39
VCC_NCTF24
VCCAUX_NCTF5 AF25
W39
VCC_NCTF25
VCCAUX_NCTF6 AG24
V39
VCC_NCTF26
VCCAUX_NCTF7 AF24
AG23
T39
VCC_NCTF27
VCCAUX_NCTF8
R39
VCC_NCTF28
VCCAUX_NCTF9 AF23
P39
VCC_NCTF29
VCCAUX_NCTF10 AG22
N39
VCC_NCTF30
VCCAUX_NCTF11 AF22
M39
VCC_NCTF31
VCCAUX_NCTF12 AG21
L39
VCC_NCTF32
VCCAUX_NCTF13 AF21
J39
VCC_NCTF33
VCCAUX_NCTF14 AG20
H39
VCC_NCTF34
VCCAUX_NCTF15 AF20
AG19
G39
VCC_NCTF35
VCCAUX_NCTF16
F39
VCC_NCTF36
VCCAUX_NCTF17 AF19
D39
VCC_NCTF37
VCCAUX_NCTF18 R19
AT38
VCC_NCTF38
VCCAUX_NCTF19 AG18
AF18
AM38
VCC_NCTF39
VCCAUX_NCTF20
AH38
VCC_NCTF40
VCCAUX_NCTF21 R18
AG38
VCC_NCTF41
VCCAUX_NCTF22 AG17
AF38
VCC_NCTF42
VCCAUX_NCTF23 AF17
AE17
AE38
VCC_NCTF43
VCCAUX_NCTF24
C38
VCC_NCTF44
VCCAUX_NCTF25 AD17
AK37
VCC_NCTF45
VCCAUX_NCTF26 AB17
AH37
VCC_NCTF46
VCCAUX_NCTF27 AA17
AB37
VCC_NCTF47
VCCAUX_NCTF28 W17
AA37
VCC_NCTF48
VCCAUX_NCTF29 V17
Y37
VCC_NCTF49
VCCAUX_NCTF30 T17
R17
W37
VCC_NCTF50
VCCAUX_NCTF31
V37
VCC_NCTF51
VCCAUX_NCTF32 AG16
T37
VCC_NCTF52
VCCAUX_NCTF33 AF16
R37
VCC_NCTF53
VCCAUX_NCTF34 AE16
P37
VCC_NCTF54
VCCAUX_NCTF35 AD16
N37
VCC_NCTF55
VCCAUX_NCTF36 AC16
M37
VCC_NCTF56
VCCAUX_NCTF37 AB16
L37
VCC_NCTF57
VCCAUX_NCTF38 AA16
Y16
J37
VCC_NCTF58
VCCAUX_NCTF39
H37
VCC_NCTF59
VCCAUX_NCTF40 W16
G37
VCC_NCTF60
VCCAUX_NCTF41 V16
F37
VCC_NCTF61
VCCAUX_NCTF42 U16
D37
VCC_NCTF62
VCCAUX_NCTF43 T16
AY36
VCC_NCTF63
VCCAUX_NCTF44 R16
AW36
VCC_NCTF64
VCCAUX_NCTF45 AG15
AN36
VCC_NCTF65
VCCAUX_NCTF46 AF15
AH36
VCC_NCTF66
VCCAUX_NCTF47 AE15
AG36
VCC_NCTF67
VCCAUX_NCTF48 AD15
AC15
AF36
VCC_NCTF68
VCCAUX_NCTF49
AE36
VCC_NCTF69
VCCAUX_NCTF50 AB15
AC36
VCC_NCTF70
VCCAUX_NCTF51 AA15
C36
VCC_NCTF71
VCCAUX_NCTF52 Y15
B36
VCC_NCTF72
VCCAUX_NCTF53 W15
BA35
VCCAUX_NCTF54 V15
AV35
VCCAUX_NCTF55 U15
AR35
VCCAUX_NCTF56 T15
AH35
VCCAUX_NCTF57 R15
AB35
AA35
CALISTOGA
Y35
W35
V35
T35
R35
P35
N35
C320
C337
C317
C319
C333
C335
C318
TC20
M35
ST220U2VBM-3GP
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
L35
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
J35
H35
G35
Place these Caps close VCC_0 ~ VCC_110
F35
D35
AN34
1D8V_S3
U71F
AD27
AC27
AB27
AA27
Y27
W27
V27
U27
T27
R27
AD26
AC26
AB26
AA26
Y26
W26
V26
U26
T26
R26
AD25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
R25
AD24
AC24
AB24
AA24
Y24
W24
V24
U24
T24
R24
AD23
V23
U23
T23
R23
AD22
V22
U22
T22
R22
AD21
V21
U21
T21
R21
AD20
V20
U20
T20
R20
AD19
V19
U19
T19
AD18
AC18
AB18
AA18
Y18
W18
V18
U18
T18
NCTF
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
CALISTOGA
C399
DY
C695
C709
C686
DY
U71J
AT23
AN23
AM23
AH23
AC23
W23
K23
J23
F23
C23
AA22
K22
G22
F22
E22
D22
A22
BA21
AV21
AR21
AN21
AL21
AB21
Y21
P21
K21
J21
H21
C21
AW20
AR20
AM20
AA20
K20
B20
A20
AN19
AC19
W19
K19
G19
C19
AH18
P18
H18
D18
A18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
J16
F16
C16
AN15
AM15
AK15
N15
M15
L15
B15
A15
BA14
AT14
AK14
AD14
AA14
U14
K14
H14
E14
AV13
AR13
AN13
AM13
AL13
AG13
P13
F13
D13
B13
AY12
AC12
K12
H12
E12
AD11
AA11
Y11
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS
J11
D11
B11
AV10
AP10
AL10
AJ10
AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1
CALISTOGA
C313

Title
GMCH (5 of 5)
Size
A3
Document Number

A
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
Wistron Corporation
SCD1U16V2ZY-2GP
2
1
C359
SCD1U16V2ZY-2GP
2
1
C331
SCD1U16V2ZY-2GP
2
1
C736
SCD1U16V2ZY-2GP
2
1
C360
SCD1U10V2KX-4GP
2
1
DY
SCD1U10V2KX-4GP
2
1
C708
SCD1U10V2KX-4GP
2
1
TC21
AK34
AG34
AF34
AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
<Variant Name>
CALISTOGA
SCD1U10V2KX-4GP
2
1
VCC
VCC_SM_0
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_SM_37
VCC_SM_38
VCC_SM_39
VCC_SM_40
VCC_SM_41
VCC_SM_42
VCC_SM_43
VCC_SM_44
VCC_SM_45
VCC_SM_46
VCC_SM_47
VCC_SM_48
VCC_SM_49
VCC_SM_50
VCC_SM_51
VCC_SM_52
VCC_SM_53
VCC_SM_54
VCC_SM_55
VCC_SM_56
VCC_SM_57
VCC_SM_58
VCC_SM_59
VCC_SM_60
VCC_SM_61
VCC_SM_62
VCC_SM_63
VCC_SM_64
VCC_SM_65
VCC_SM_66
VCC_SM_67
VCC_SM_68
VCC_SM_69
VCC_SM_70
VCC_SM_71
VCC_SM_72
VCC_SM_73
VCC_SM_74
VCC_SM_75
VCC_SM_76
VCC_SM_77
VCC_SM_78
VCC_SM_79
VCC_SM_80
VCC_SM_81
VCC_SM_82
VCC_SM_83
VCC_SM_84
VCC_SM_85
VCC_SM_86
VCC_SM_87
VCC_SM_88
VCC_SM_89
VCC_SM_90
VCC_SM_91
VCC_SM_92
VCC_SM_93
VCC_SM_94
VCC_SM_95
VCC_SM_96
VCC_SM_97
VCC_SM_98
VCC_SM_99
VCC_SM_100
VCC_SM_101
VCC_SM_102
VCC_SM_103
VCC_SM_104
VCC_SM_105
VCC_SM_106
VCC_SM_107
AU41
AT41
AM41
AU40
BA34
AY34
AW34
AV34
AU34
AT34
AR34
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1
SCD1U10V2KX-4GP
2
1
VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_92
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_107
VCC_108
VCC_109
VCC_110
SC10U10V5ZY-1GP
2
1
U71I
U71G
AA33
W33
P33
N33
L33
J33
AA32
Y32
W32
V32
P32
N32
M32
L32
J32
AA31
W31
V31
T31
R31
P31
N31
M31
AA30
Y30
W30
V30
U30
T30
R30
P30
N30
M30
L30
AA29
Y29
W29
V29
U29
R29
P29
M29
L29
AB28
AA28
Y28
V28
U28
T28
R28
P28
N28
M28
L28
P27
N27
M27
L27
P26
N26
L26
N25
M25
L25
P24
N24
M24
AB23
AA23
Y23
P23
N23
M23
L23
AC22
AB22
Y22
W22
P22
N22
M22
L22
AC21
AA21
W21
N21
M21
L21
AC20
AB20
Y20
W20
P20
N20
M20
L20
AB19
AA19
Y19
N19
M19
L19
N18
M18
L18
P17
N17
M17
N16
M16
L16
ST220U2VBM-3GP
2
1
1D05V_S0
Rev
SA
LWG2
Sheet
E
10
of
52
8 M_B_DQS#[7..0]
8 M_B_DQS[7..0]
13
31
51
70
131
148
169
188
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
114
119
ODT0
ODT1
1
2
C328
BC4
DY SCD1U16V2ZY-2GP
2
SC2D2U6D3V3MX-1-GP
2
1
7,12 M_ODT2
7,12 M_ODT3
DDR_VREF_S3
202
164
166
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
10
26
52
67
130
147
170
185
M_CLK_DDR2 7
M_CLK_DDR#2 7
M_B_DM[7..0] 8
SDA
SCL
195
197
VDDSPD
199
SA0
SA1
198
200
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
50
69
83
120
163
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
81
82
87
88
95
96
103
104
111
112
117
118
VREF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
GND
GND
201
DDR2-200P-5-GP-U
8,12 M_A_BS#2
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
8,12 M_A_BS#0
8,12 M_A_BS#1
107
106
BA0
BA1
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
11
29
49
68
129
146
167
186
/DQS0
/DQS1
/DQS2
/DQS3
/DQS4
/DQS5
/DQS6
/DQS7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
13
31
51
70
131
148
169
188
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
114
119
ODT0
ODT1
1
2
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
8 M_A_DQ[63..0]
SMBD_ICH 3,18
SMBC_ICH 3,18
3D3V_S0
1 R363
2
10KR2J-3-GP
BC6
SCD1U16V2ZY-2GP
Place near DM2

M_CLK_DDR3
DY
C326
SC10P50V2JN-4GP
M_CLK_DDR#3
M_CLK_DDR2
1D8V_S3
DY
C448
SC10P50V2JN-4GP
M_CLK_DDR#2
8 M_A_DQS#[7..0]
8 M_A_DQS[7..0]
7,12 M_ODT0
7,12 M_ODT1
DDR_VREF_S3
DDR_VREF_S3
C696
62.10017.771
High 5.2mm
2nd source:62.10017.661
DY
BC10
SCD1U16V2ZY-2GP
202
110
115
M_CS0# 7,12
M_CS1# 7,12
CKE0
CKE1
79
80
CK0
/CK0
30
32
CK1
/CK1
164
166
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
10
26
52
67
130
147
170
185
SDA
SCL
195
197
VDDSPD
199
SA0
SA1
198
200
NC#50
NC#69
NC#83
NC#120
NC#163/TEST
50
69
83
120
163
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
81
82
87
88
95
96
103
104
111
112
117
118
VREF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
162
165
168
171
172
177
178
183
184
187
190
193
196
GND
GND
201
M_CKE0 7,12
M_CKE1 7,12
M_CLK_DDR1 7
M_CLK_DDR#1 7
M_A_DM[7..0] 8
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_CLK_DDR0
DY
C329
SC10P50V2JN-4GP
M_CLK_DDR#0
M_CLK_DDR1
DY
SMBD_ICH
SMBC_ICH
C449
SC10P50V2JN-4GP
M_CLK_DDR#1
3D3V_S0
BC7
SCD1U16V2ZY-2GP
DDR2-200P-4-GP-U
1D8V_S3
<Variant Name>
Wistron Corporation
62.10017.761
Title
High 9.2mm
2nd source:62.10017.A61
DDR2 Socket
Size
Document Number
Custom
Place near DM1
M_CLK_DDR0 7
M_CLK_DDR#0 7
CK1
/CK1
/CS0
/CS1
M_CLK_DDR3 7
M_CLK_DDR#3 7
M_A_RAS# 8,12
M_A_WE# 8,12
M_A_CAS# 8,12
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
30
32
108
109
113
/DQS0
/DQS1
/DQS2
/DQS3
/DQS4
/DQS5
/DQS6
/DQS7
CK0
/CK0
M_CKE2 7,12
M_CKE3 7,12
/RAS
/WE
/CAS
11
29
49
68
129
146
167
186
79
80
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
CKE0
CKE1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
M_CS2# 7,12
M_CS3# 7,12
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
SC2D2U6D3V3MX-1-GP
2
1
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
110
115
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
8 M_B_DQ[63..0]
/CS0
/CS1
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
BA0
BA1
M_B_RAS# 8,12
M_B_WE# 8,12
M_B_CAS# 8,12
107
106
108
109
113
8,12 M_B_BS#0
8,12 M_B_BS#1
/RAS
/WE
/CAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2
8,12 M_B_BS#2
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
NORMAL TYPE
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
DM2
8,12 M_A_A[13..0]
DM1
8,12 M_B_A[13..0]
NORMAL TYPE
Rev
LWG2
SB
Sheet
E
11
of
52
PARALLEL TERMINATION
Decoupling Capacitor
Put decap near power(0.9V) and pull-up resistor
SRN56J-5-GP
RN60
8
7
6
5
DY
M_ODT2 7,11
M_CS2# 7,11
M_B_RAS# 8,11
1
1
M_B_A13
1
2
3
4
C418
C396
C415
C434
C436
C398
C397
C409
C408
C407
C437
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
M_B_A5
M_B_A3
M_B_A1
M_B_A10
DY
1
2
3
4
RN62
8
7
6
5
DY
M_ODT1 7,11
M_ODT3 7,11
2
R314 2 56R2J-4-GP
R312 2 56R2J-4-GP M_A_A9
R315 2 56R2J-4-GP M_B_A8
R313
56R2J-4-GP
C435
C419
C413
C387
C386
C411
C384
C412
C438
C385
C391
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
M_B_A[13..0] 8,11
M_A_A[13..0] 8,11
SRN56J-5-GP
M_B_A12
M_B_A9
M_CKE2 7,11
M_B_BS#2 8,11
1
2
3
4
1
1
1
1
Put decap near power(0.9V)

and pull-up resistor
DDR_VREF_S0
RN55
8
7
6
5
DDR_VREF_S0
DY
1D8V_S3
Place these Caps near DM1
SRN56J-5-GP
1
C395
SC2D2U6D3V3MX-1-GP
C394
SC2D2U6D3V3MX-1-GP
C735
SC2D2U6D3V3MX-1-GP
C734
SC2D2U6D3V3MX-1-GP
M_B_BS#1 8,11
M_B_A0
M_B_A2
M_B_A4
1
2
3
4
8
7
6
5
RN59
C417
SC2D2U6D3V3MX-1-GP
SRN56J-5-GP
DY
C389
C414
C388
C410
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
M_CKE3 7,11
SRN56J-5-GP
M_B_A6
M_B_A7
M_B_A11
1
2
3
4
RN54
8
7
6
5
DY
DY
RN61
8
7
6
5
1
2
3
4
M_B_BS#0 8,11
M_B_WE# 8,11
M_CS3# 7,11
M_B_CAS# 8,11
1D8V_S3
SRN56J-5-GP
Place these Caps near DM2
RN63
1
C759
SC2D2U6D3V3MX-1-GP
C390
SC2D2U6D3V3MX-1-GP
C392
SC2D2U6D3V3MX-1-GP
C733
SC2D2U6D3V3MX-1-GP
M_ODT0 7,11
M_CS0# 7,11
M_A_RAS# 8,11
M_A_A13
1
2
3
4
8
7
6
5
C761
SC2D2U6D3V3MX-1-GP
SRN56J-5-GP
2
RN65
DY
RN66
8
7
6
5
1
2
3
4
DY
1
2
C382
C383
C416
C393
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SRN56J-5-GP
M_A_BS#1 8,11
M_A_A0
M_A_A2
M_A_A4
1
2
3
4
8
7
6
5
DY
M_A_BS#0 8,11
M_A_WE# 8,11
M_A_CAS# 8,11
M_CS1# 7,11
SRN56J-5-GP
RN56
8
7
6
5
1
2
3
4
M_A_A12
M_A_A8
M_CKE0 7,11
M_A_BS#2 8,11
SRN56J-5-GP
RN64
8
7
6
5
1
2
3
4
M_A_A6
M_A_A7
M_A_A11
1
2
3
4
M_A_A5
M_A_A3
M_A_A1
M_A_A10
M_CKE1 7,11
<Variant Name>
SRN56J-5-GP
Wistron Corporation
RN67
8
7
6
5

Title
DDR2 Termination Resistor
SRN56J-5-GP
Size
A3
Document Number

A
Rev
LWG2
SA
Sheet
E
12
of
52
NUM_LED 30
5V_S0
3D3V_S0
SATA
R235
10KR2J-3-GP
D22
KMEDIA_LED#_1
1
2
LED-B-67-GP-U2
1
2
R805
300R2F-GP
EC566
SC1000P50V2JN-N1
MEDIA_LED#
CDROM_LED# 20
LED3
HDLED#
2
R233
BAW56PT-U
83.00056.E11
1
0R2J-2-GP
SATA_LED# 15
SATA
46
5V_S5
Q41
2 GND
LED4
K PWRLED#_1
1
2
LED-B-67-GP-U2
1
2 PWRLED#_2
R806
300R2F-GP
EC567
SC1000P50V2JN-N1
OUT 3
R2
R1
1 IN
PWRLED 30,31
ATI_TXAOUT2- 45
ATI_TXAOUT2+ 45
ATI_TXAOUT1- 45
ATI_TXAOUT1+ 45
C12
SCD1U16V2ZY-2GP
C19
DY
SC10U10V5ZY-1GP
2
1
SC1KP16V2KX-GP
EDID_CLK 43 LCDVDD_S0
EDID_DAT 43
ATI_TXACLK- 45
ATI_TXACLK+ 45
EVEN CHANNEL
ATI_TXAOUT0- 45
ATI_TXAOUT0+ 45
ATI_TXBOUT0- 45
ATI_TXBOUT0+ 45
ATI_TXBOUT1- 45
ATI_TXBOUT1+ 45
ODD CHANNEL
ATI_TXBOUT2- 45
ATI_TXBOUT2+ 45
ATI_TXBCLK- 45
ATI_TXBCLK+ 45
BRIGHTNESS
1
2
R4751 0R2J-2-GP
2
R474 0R2J-2-GP
USB_PN5 16
USB_PP5 16
LCDGPIO 30
C554
CHDTC124EU-1GP
EC31
DCBATOUT
Layout 60 mil
IPEX-CON40-2-GP
20.F0763.040
Power:
Blue : power on
Blue Blinking : suspend
EC6 EC5
SCD1U10V2KX-4GP
SC1KP16V2KX-GP
1
2
1 IN
CHDTC124EU-1GP
1 R169
2 SCD1U10V2KX-4GP
EC4
0R2J-2-GP
VCC_CCD 3VCCD
1
2
SC1KP16V2KX-GP
2
1
2
1
R2
R1
EC3
1
42
2 GND
OUT 3
3D3V_S0
44
CAP_LED 30
Q13
NC
MH2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
45
CHDTC124EU-1GP
LED1
5VCCD
1 IN
R236
4K7R2J-2-GP
R2
R1
KNUM_LED#_11
2 NUM_LED#_2
R804
300R2F-GP
LED-B-67-GP-U2
EC565
SC1000P50V2JN-N1
NC
MH1
C20
SC1U10V3KX-3GP
41 1N4148W-7-F-GP
43
SC1KP16V2KX-GP
2
1
OUT 3
KCAP_LED#_1 1
2CAP_LED#_2
R803
300R2F-GP
LED-B-67-GP-U2
EC564
SC1000P50V2JN-N1
NC
A
C8
AAT4280IGU-3-T1GP
SCD1U50V3KX-GP
74.04280.B9P
SC1U10V3KX-3GP
NC
A
2 GND
D41
LCD1 5V_S0
6
5
4
SCD1U25V3KX-GP
2
1
C9
Q12
LED2
IN
GND
IN
45 ATI_LCDVDD_ON
OUT
GND
ON/OFF#
1
2
3
Layout 40 mil
5V_S0
LCD/INVERTER/CCD CONN
3D3V_S0
Layout 40 mil
U2
SC1U50V5ZY-1-GP
2
1
LCDVDD_S0
BRIGHTNESS 30
BLON_OUT 30
EC32
R9
100KR2J-1-GP
C553
TOP VIEW
40
Q55
LCD
2 GND
OUT 3
WLAN_TEST_LED 30
1
2
1
2
2
1
2
DY
R842
10KR2J-3-GP
DY
R841
CAP_LED
R2
NUM_LED
R1
1 IN
DC_BATFULL 30
PWRLED
CHDTC124EU-1GP
DC_BATFULL
2 GND
150R2J-L1-GP-U
EC571
DY
R840
10KR2J-3-GP
EC570
SC1000P50V2JN-N1
OUT 3
DY
R839
10KR2J-3-GP
2 GND
1 DC_BATFULL#_2
100R2J-2-GP
Q20
DY
R838
10KR2J-3-GP
LED6
BLUETOOTH_LED 30
Q24
DC_BATFULL#_1
2
R444
1 IN
10KR2J-3-GP
R2
R1
84.00124.F1K
CHDTC124EU-1GP
EC569
3D3V_S5
3D3V_S0
Wireless/Bluetooth
Blue: WLAN
Amber: Bluetooth
Blue+Amber : WLAN + Bluetooth
1 BT_LED# OUT 3
150R2J-L1-GP-U
SC1000P50V2JN-N1
SC1000P50V2JN-N1
1 LED-BO-5-GP-U 3
1 IN
CHDTC124EU-1GP
Q26
BT_LED#_1
2
R430
EC568
5V_S5
R2
R1
LED5
WLAN_LED# 26
2 GND
WLAN_LED#_1
1 LED-BO-5-GP-U 3
1
100R2J-2-GP
2
R807
5V_S0
1CHRGER_LED#_2
R445
OUT 3
Blue: DC-in and charge full

Amber: Charging Battery
No Color: Batt. mode
Amber Shine: Batt. empty
R2
R1
1 IN
CHRGER_LED
<Variant Name>
CHRGER_LED
30
CHDTC124EU-1GP
Wistron Corporation
SC1000P50V2JN-N1

Front panel
LED
Title
left side
Power
Right side
Battery
Wireless
Num
Caps
HDD
LCD / LAUNCH / LEDs

Size
Custom
Document Number
Rev
LWG2
SA
Sheet
13
of
52
CRT I/F & CONNECTOR
Ferrite bead impedance: 47 ohm@100MHz
Layout Note:
Place these resistors
close to the CRT-out
connector
SB change
5V_S0
L17
CRT_R
5V_CRT_S0
43 ATI_RED
D2
CH751H-40PT
BLM18BB470SN1-GP
L18
CRT_G
43 ATI_GREEN
-1 for CRT SIV Fail
CRT1
17
1
2
1
2
RN3
SRN10KJ-5-GP
C546
SC6D8P50V2DN-GP
Layout Note:
* Must be a ground return path between this ground and the ground on
the VGA connector.
Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT
CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.
C544
SC6D8P50V2DN-GP
DY
1
BLM18BB470SN1-GP
C542
SC6D8P50V2DN-GP
6
1
11
DAT_DDC1_5
12
JVGA_HS
13
JVGA_VS
14
CLK_DDC1_5
CRT_R
7
2
8
3
9
4
10
5
15
CRT_G
CRT_B
VIDEO-15-42-GP-U
20.20378.015
C6
SC18P50V2JN-1-GP
C4
SC100P50V2JN-3GP
16
C7
SC100P50V2JN-3GP
Hsync & Vsync level shift
DY
CRT_B
1
2
C545
SC3P50V2CN-1-GP
DY
SC3P50V2CN-1-GP
R456
R457
R458
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP
C543
C541
SC3P50V2CN-1-GP
43 ATI_BLUE
C2
SCD01U16V2KX-3GP
4
3
BLM18BB470SN1-GP
L19
C5
SC18P50V2JN-1-GP
-1 for CRT SIV Fail
5V_S0
43
1 R451
2
47R2J-2-GP
ATI_HSY
HSYNC_4
3D3V_S0
4
3
U59A
14
DDC_CLK & DATA level shift

C539
SCD1U16V2ZY-2GP
RN4
SRN2K2J-1-GP
JVGA_HS
1 R449
2
47R2J-2-GP
ATI_VSY
VSYNC_4
1
2
For System CRT

JVGA_VS
TSAHCT125PW-GP
DAT_DDC1_5
43 ATI_DDCDAT
Q3
2N7002-7F-GP
43 ATI_DDCCLK
43
14
TSAHCT125PW-GP
U59B
CLK_DDC1_5
Q4
2N7002-7F-GP
TV
C689
SC150P-GP
1
L25
TV
R616
150R2F-1-GP
TV
1
BAV99PT-GP-U
MINDIN7-11-U2-GP
22.10021.D81
LUMA_1
D25
TV C693
SC270P50V2JN-2GP
Reverse type
2
<Variant Name>
CRT_G 3
TV
D24
COMP_1
TV
SC270P50V2JN-2GP
BAV99PT-GP-U
Wistron Corporation
BAV99PT-GP-U
D34
COMP_1 3
TV C692
D33
CRMA_1 3
BAV99PT-GP-U
2 C691
C688
SC150P-GP
CRT_R 3
BAV99PT-GP-U
TV SC33P50V3JN-GP
1
2
IND-1D2UH-5-GP
D32
LUMA_1 3
TV
8
5V_S0

Title
CRT_B 3
CRT/TV Connector
Size
A3
1
BAV99PT-GP-U
Document Number
Rev
LWG2
TV
43 ATI_TV_COMP
5V_S0
D23
TV
TV
1
2
IND-1D2UH-5-GP
3
6
7
5
2
4
TV
R617
150R2F-1-GP
SC270P50V2JN-2GP
2 C690
SC33P50V3JN-GP
TV
43 ATI_TV_LUMA
TV C706
TV
C704
SC150P-GP
1
L24
TVOUT1
CRMA_1
TV
R621
150R2F-1-GP
1
2
IND-1D2UH-5-GP
TV
43 ATI_TV_CRMA
2 C705
TV SC33P50V3JN-GP
1
L26
TV OUT CONN
SA
Sheet
E
14
of
52
1D05V_S0
Y5
W4
INTRUDER#
INTVRMEN
W1
Y1
Y2
W3
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
C178
SC1U10V3ZY-6GP
DY
2nd source: 20.D0198.103
28
AC97_BTCLK 2
R124 1
22R2J-2-GP
AC97_BTCLK
21 ACZ_BTCLK_MDC
21,28 ACZ_SYNC
1
R545
1
R553
28 ACZ_RST_ALC#
21 ACZ_RST_MDC#
2
2
R126 1
2
22R2J-2-GP
1
R547
ACZ_BIT_CLK
ACZ_SYNC_R
2
39R2J-L-GP
ACZ_RST#_R
39R2J-L-GP
39R2J-L-GP
21,28 ACZ_SDATAOUT
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
U1
R6
ACZ_BIT_CLK
ACZ_SYNC
R5
ACZ_RST#
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
AF7
AE7
AG6
AH6
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
AF1
AE1
SATA_CLKN
SATA_CLKP
3 CLK_PCIE_SATA#
3 CLK_PCIE_SATA
1
2
1
U5
V4
T5
AF3
AE3
AG2
AH2
1
R569
Place within 500 mils

of ICH7ball
LAN_RSTSYNC
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
Change to 24.9 1% ohm

when use SATA HD
INTVRMEN
LAN_CLK
T2
T3
T1
TPAD30 TP5
ACZ_SDATAOUT_R
1
2
T4
39R2J-L-GP
R544
AF18
13 SATA_LED#
R543
300KR2J-GP
P.H. for internal VCCSUS1_05
V3
U7
V6
V7
20
20
20
20
20
20
A20GATE
A20M#
AE22
AH28
CPUSLP#
AG27
H_CPUSLP#_2
TP1/DPRSTP#
TP2/DPSLP#
AF24
AH25
H_DPRSLP#_2
TP111TPAD30
2
3D3V_S0
10KR2J-3-GP
Open R168 for Dothan A step

Shunt for Dothan B step
& all Yonah
LPC_LFRAME# 30,32
1D05V_S0
K_A20GATE 30
H_A20M# 4
1 R170
2DY
0R2J-2-GP
1 R168
2
H_DPSLP# 0R0402-PAD
4
FERR#
AG26
GPIO49/CPUPWRGD
AG24
H_PWRGD 4,33
IGNNE#
INIT3_3V#
INIT#
INTR
AG22
AG21
AF22
AF25
H_IGNNE# 4
FWH_INIT# 32
H_INIT# 4
H_INTR 4
RCIN#
AG23
H_RCIN#
NMI
SMI#
AH24
AF23
H_NMI 4
H_SMI# 4
STPCLK#
AH22
H_STPCLK# 4
THERMTRIP#
AF26
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15
IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
DA0
DA1
DA2
AH17
AE17
AF17
IDE_PDA0 20
IDE_PDA1 20
IDE_PDA2 20
DCS1#
DCS3#
AE16
AD16
IDE_PDCS1# 20
IDE_PDCS3# 20
ACZ_SDOUT
R565
56R2J-4-GP
H_CPUSLP# 4,6
H_DPRSLP# 4,35
H_FERR# 4
1D05V_S0
H_PWRGD
1 R563
2
200R2F-L-GP
DY
1D05V_S0
-1 Modify
30
R568
56R2J-4-GP
H_THERMTRIP_R
SATALED#
SATARBIAS AH10
2
AG10
24D9R2F-L-GP
IDE_PDIOR#
IDE_PDIOW#
IDE_PDDACK#
INT_IRQ14
IDE_PDIORDY
IDE_PDDREQ
LFRAME#
AC3 LPC_LDRQ0#
1
AA5
R559
AB3
LDRQ0#
LDRQ1#/GPIO23
U3
28 ACZ_SDATAIN0
21 ACZ_SDATAIN1
20 SATA_RXN0
20 SATA_RXP0
20 SATA_TXN0
20 SATA_TXP0
RTC_AUX_S5
RTCRST#
AA3
INTRUDER#
INTVRMEN
C133
SCD1U16V2ZY-2GP
RTC_RST#
30,32
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
2
20KR2J-L2-GP
2
1MR2J-1-GP
AA6
AB5
AC4
Y6
1
R540
1
R541
LAD0
LAD1
LAD2
LAD3
CH751H-40PT
ACES-CON3-GP
20.F0714.003
3
2BAT_D
2
RTXC1
RTCX2
RTC
LPC
2
3
RCT_X1 AB1
RCT_X2AB2
D20
BAT
1
LPC_LAD[0..3]
U20A
C236 SC4D7P50V3DN-1GP
LAN
CPU
1KR2J-1-GP
R123
RTC1
C135
SC1U10V3ZY-6GP
RTC circuitry
AC-97/AZALIA
CH751H-40PT
H_DPSLP#
DY
R164
10MR2J-L-GP
D19
R567
56R2J-4-GP
X1
X-32D768KHZ-41GP
82.30001.731
RTC_AUX_S5
SATARBIASN
SATARBIASP
AF15
AH15
AF16
AH16
AG16
AE15
DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ
SATA
3D3V_AUX_S5
C234 SC4D7P50V3DN-1GP
IDE
Layout Note: R568 needs to placed

within 2" of ICH7, R568 must be placed
within 2" of R169 w/o stub.
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
ICH7-M-GP
71.ICH7M.00U
R549
0R2J-2-GP
INTVRMEN
Enable
DY
Disable
0
<Variant Name>
Wistron Corporation
Placement Note:
Diatance between the ICH-7 M and cap on the "P" signal
should be identical distance between the ICH-7 M and cap
on the "N" signal for same pair.

Title
ICH7-M (1 of 4)
Size
A3
Document Number
Rev
LWG2
Date: Wednesday, June 21, 2006

A
SA
Sheet
E
15
of
52
3D3V_S0
U20C
RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]
TPAD30
TP68
TPAD30
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
28 ACZ_SPKR
30 PM_SUS_STAT#
2 R516
1
C26
PLT_RST1# 7,20,22,26,30,32,42
0R0402-PAD
A9
CLK_ICHPCI 3
1
2
B19 ICH_PME#_1
ICH_PME# 51
R512 0R0402-PAD
RSVD[6]
RSVD[7]
RSVD[8]
RSVD[9]
MCH_SYNC#
SPKR
SUS_STAT#
SYS_RST#
AB18
PCI_IRDY# 25,51
PCI_PAR 24,51
2 47R2J-2-GP
PCIRST1# 25,27,51
PCI_DEVSEL# 25,51
PCI_PERR# 25,51
A21
21 USB_EN2#_SB
B21
PSW_CLR# E23
21 USB_EN3#_SB
31 PSW_CLR#
25,30,51 PM_CLKRUN#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#
B23
AC20
AF21
3 PM_STPPCI#
3 PM_STPCPU#
PLTRST#
PCICLK
PME#
MISC
A19
A27
A22
SMB_ALERT#
24,51
24,51
24,51
24,51
A7
E10
B18 R511 1
A12
C9
E11 PCI_LOCK#
B10
F15
F14
F16
G8
F7
F8
G7
DBRESET#
7 PM_BMBUSY#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
GPIO2/PIRQE#
GPIO3/PIRQF#
GPIO4/PIRQG#
GPIO5/PIRQH#
RI#
25,51
25,51
25,51
25,51
INT_PIRQF# 25
INT_PIRQG# 25
INT_PIRQH# 51
30
GPIO26
GPIO27
GPIO28
GPIO33/AZ_DOCK_EN#
GPIO34/AZ_DOCK_RST#
AD22
AC21
AC18
ECSMI# E21
SPI_WP#
ECSCI#
MCH_ICH_SYNC#
26 PCIE_RXN2
26 PCIE_RXP2
H26
H25
SCD1U16V2KX-3GP
2
1 C574 G28
SCD1U16V2KX-3GP
2
1 C575 G27
PERn2
PERp2
PETn2
PETp2
K26
K25
J28
J27
PERn3
PERp3
PETn3
PETp3
3D3V_S0
1
2
3
4
5
10
9
8
7
6
M26
M25
L28
L27
PERn4
PERp4
PETn4
PETp4
3D3V_S0
INT_PIRQD#
INT_PIRQG#
INT_PIRQF#
INT_PIRQC#
3D3V_S0
1
2
3
4
5
SRN8K2J-2-GP
ACZ_SPKR
ECSCI#
DY
EXT_FWH#
3D3V_S5
1
2
3
4
5
10
9
8
7
6
3D3V_S5
USB_OC#4
C773
DUMMY-C2
C807
DUMMY-C2
C811
DUMMY-C2
USB_OC#5
USB_OC#7
USB_OC#4
USB_OC#6
SB adds for OC#
SRN10KJ-L3-GP
10
9
8
7
6
PM_CLKRUN#
USB_OC#2
USB_OC#1
USB_OC#3
USB_OC#0
USB_OC#2
3D3V_S5
PCIE_WAKE#
PSW_CLR#
SMB_ALERT#
PM_RI#
SRN10KJ-L3-GP
RP9
PCI_REQ#3
INT_SERIRQ
PCI_REQ#4
PCI_REQ#0
SRN8K2J-2-GP
RP4
10
9
8
7
6
MCH_ICH_SYNC#
PCI_REQ#1
PCI_REQ#2
PCI_REQ#5
ICH7_GPI12
1
PM_BATLOW#_R 2
DBRESET#
3
SMB_LINK_ALERT# 4
5
3D3V_S5
SRN8K2J-2-GP
RP6
3D3V_S0
INT_PIRQB#
INT_PIRQH#
INT_PIRQE#
INT_PIRQA#
3D3V_S5
3D3V_S0
32
SPI_CLK
RN90
1
2
8K2R2J-3-GP
R625
2
1
R513
1KR2J-1-GP
1 R560
2
10KR2J-3-GP
R561
1
2
10KR2J-3-GP
PWROK 7,19
PM_BATLOW#_R
PWRBTN#
PWRBTN#_ICH
LAN_RST#
C19
2 R564
1 100R2J-2-GP PM_DPRSLPVR 35
2
DY1100KR2J-1-GP
R566
D16
BAS16-1-GP
1
SB_PWRBTN# 30
1
2
3
R510
2
10KR2J-3-GP
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO35
GPIO38
GPIO39
Y4
E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20
SB_RSMRST# 30
ECSWI# 30
R546
100KR2J-1-GP
ICH7_GPI12
R47
2
0R2J-2-GP
MDC_KILL# 21
USB_EN1#_SB 21
PERn1
PERp1
PETn1
PETp1
3D3V_S0
RP7
3D3V_S0
AA4
AC22 PM_DPRSLPVR_R
C23
GPIO
F26
F25
SCD1U16V2KX-3GP
2
1 C602 E28
SCD1U16V2KX-3GP
2
1 C601 E27
USB_OC#0
NEW
PCI_SERR#
PCI_LOCK#
PCI_PERR#
PCI_DEVSEL#
PM_SUS_CLK 18
PM_SLP_S3# 18,30,33,38,40,49
PM_SLP_S5# 30,38,40
C21
VRMPWRGD
GPIO6
GPIO7
GPIO8
CLK_ICH14 3SRN10KJ-6-GP
CLK48_ICH 3
TP0/BATLOW#
WAKE#
SERIRQ
THRM#
ICH7 Pullups
10
9
8
7
6
GPIO16/DPRSLPVR
RSMRST#
PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1
22
22
22
22
LAN
26 PCIE_TXP2
RP5
B24
D23
F22
8
7
6
5
U20D
AE9
AG8
AH8
F21
AH20
MiniC26 PCIE_TXN2
1
2
3
4
5
C20
1
2
3
4
ICH7-M-GP
ICH7-M-GP
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#
PWROK
GPIO18/STPPCI#
GPIO20/STPCPU#
AC19
U2
7,35,45 VGATE_PWRGD
AC1
B2
GPIO11/SMBALERT#
GPIO32/CLKRUN#
PCIE_WAKE# F20
AH21
AF20
32
GPIO0/BM_BUSY#
AG18
22,30 PCIE_WAKE#
25,30 INT_SERIRQ
19
THRM#
CLK14
CLK48
SATA0_R2
SATA0_R0
SATA0_R3
SATA0_R1
TPAD30
TP2
A28
SATA0_R0
SATA0_R1
SATA0_R2
SATA0_R3
TP69
PM_RI#
AF19
AH18
AH19
AE19
ECSWI#
ECSMI#
3
4
SMLINK0
SMLINK1
SRN100KJ-6-GP
RN88
3
2
4
1
1 R125
2
47R2J-2-GP
TPAD30 TP4
21 USB_OC#2
21 USB_OC#4
SRN10KJ-5-GP
PERn5
PERp5
PETn5
PETp5
T25
T24
R28
R27
PERn6
PERp6
PETn6
PETp6
R2
P6
P1
SPI_CLK
SPI_CS#
SPI_ARB
SPI_MOSI
SPI_MISO
P5
P2
SPI_MOSI
SPI_MISO
D3
C4
D5
D4
E5
C3
A2
B3
V26
V25
U28
U27
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
7
7
7
7
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
Y26
Y25
W28
W27
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
7
7
7
7
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
AB26
AB25
AA28
AA27
DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2
7
7
7
7
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
AD25
AD24
AC28
AC27
DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3
7
7
7
7
DMI_CLKN
DMI_CLKP
AE28
AE27
CLK_PCIE_ICH# 3
CLK_PCIE_ICH 3
DMI_ZCOMP
DMI_IRCOMP
SPI_CLK_1
SPI_CS#
SPI_ARB
USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
21 USB_OC#0
2
1
P26
P25
N28
N27
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
OC0#
OC1#
OC2#
OC3#
OC4#
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
C25
D25
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3
USBRBIAS#
USBRBIAS
D2
D1
Layout Note:
PCIE AC coupling caps
need to be within 250 mils of the driver.
7 DMI_TXN[3..0]
7 DMI_TXP[3..0]
7 DMI_RXN[3..0]
7 DMI_RXP[3..0]
1D5V_S0
AE5
AD5
AG4
AH4
AD9
TPAD30
PCI_REQ#2 51
PCI_GNT#2 51
GPIO21/SATA0GP
GPIO19/SATA1GP
GPIO36/SATA2GP
GPIO37/SATA3GP
Place within 500 mils of ICH

R535
24D9R2F-L-GP
PIRQA#
PIRQB#
PIRQC#
PIRQD#
TP112
SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1
SATA
GPIO
B15
C12
D12
C15
PCI_REQ#1
PCI_GNT#1
PCI_REQ#2
PCI_GNT#2
PCI_REQ#3
PCI_GNT#3
PCI_REQ#4
PCI_GNT#4
PCI_REQ#5
PCI_GNT#5
C22
B22
SMB_LINK_ALERT# A26
SMLINK0
B25
SMLINK1
A25
18,22,26 SMB_CLK
18,22,26 SMB_DATA
PCI_REQ#0 25
PCI_GNT#0 25
Clocks
C/BE0#
C/BE1#
C/BE2#
C/BE3#
PCI_REQ#0
SMB
D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8
Interrupt I/F
A3
B4
C5
B5
REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
REQ4#/GPIO22
GNT4#/GPIO48
GPIO1/REQ5#
GPIO17/GNT5#
Direct Media Interface
INT_PIRQB#
PCI
USB
25
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PCI-Express
E18
C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6
SYS
GPIO
Power MGT
U20B
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
RN24
SPI
24,25,51 PCI_AD[0..31]
DMI_IRCOMP_R
USB_PN0 21
USB_PP0 21
USB_PN1 21
USB_PP1 21
USB_PN2 21
USB_PP2 21
USB_PN3 20
USB_PP3 20
USB_PN4 21
USB_PP4 21
USB_PN5 13
USB_PP5 13
USB_PN6 26
USB_PP6 26
USB
Pair
TP117TPAD30
TP116TPAD30
USB_RBIAS_PN
1
R80
2
22D6R2F-L1-GP
ICH7-M-GP
SC Modify
Device
USB1
BT
USB3
FP
USB2
CCD
MINIC1
NC
3D3V_S5
EXT_FWH#
1 R557
DY
PWROK
2
10KR2J-3-GP
LPC
PCI
SPI
T=22ms
GNT5# GNT4#
32
SPI_CS#
32
32
SPI_MOSI
SPI_MISO
RSMRST#_TO_KBC 30
DY
Default:H
PCI_GNT#4
2
1KR2J-1-GP
R588
C659
100KR2J-1-GPSC4D7U10V5ZY-3GP
1
R542
3
4
2
10KR2J-3-GP
RN91
2
1
Wistron Corporation
Title
ICH7-M (2 of 4)
Size
A3
Boot from various source

A
<Variant Name>
SRN10KJ-5-GP
R42
3D3V_S5
4K7R2J-2-GP
2N7002-7F-GP
D40
BAT54PT-GP
PCI_GNT#5
SPI
Q43
R587
2
10KR2J-3-GP
1 R532
DY
1
EXT_FWH# 32
SPI_WP#
2
R562 1KR2J-1-GP
Document Number

B
Rev
LWG2
SA
Sheet
E
16
of
52
1D5V_ICH_S0
C587
DY
SCD1U10V2KX-4GP
C591
SCD1U10V2KX-4GP
SCD01U16V2KX-3GP
NO_STUFF
C592
1D5V_S0
1
TPAD28 TP7
E3
VccSus3_3[19]
C1
VccUSBPLL
AA2
Y7
Vcc1_5_A[19]
Vcc1_5_A[20]
AB17
AC17
Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]
T7
F17
G17
Vcc1_5_A[24]
Vcc1_5_A[25]
AB8
AC8
VccSus1_05[1]
VccSus1_05[2]
VccSus1_05[3]
VccSus1_05/VccLAN1_05[1]
VccSus1_05/VccLAN1_05[2]Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]
ICH7-M-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1
2
1
RTC_AUX_S5
C589
SCD1U10V2KX-4GP
DY
NO_STUFF
C588
C608
C639
C590
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1D5V_S0
<Variant Name>
1
Wistron Corporation
1D5V_S0

A1
H6
H7
J6
J7
Title
ICH7-M (3 of 4)
Size
A3
Document Number

A
DY
3D3V_S5
1 R531
2
0R0603-PAD
3D3V_S0
C598
SCD1U10V2KX-4GP
C54
SC10U10V5ZY-1GP
3D3V_ICH_S5
Layout Note:
IDE decoupling
3D3V_S5
C136
SCD1U10V2KX-4GP
R548 1
2
0R0603-PAD
V3D3A_VCCPSUS
NO_STUFF
Layout Note:
Place near AB3
C55
SC10U10V5ZY-1GP
DY
K7
C28
G20
C570
SCD1U10V2KX-4GP
VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]
K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7
C571
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
A24
C24
D19
D22
G19
C593
SCD1U10V2KX-4GP
C640
2
1
P7
VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]
C596
SCD1U10V2KX-4GP
VccSus3_3[1]
3D3V_S0
VccRTC
W5
Layout Note:
PCI decoupling
3D3V_S0
A5
B13
B16
B7
C10
D15
F9
G11
G12
G16
C620
SC10U6D3V5MX-3GP
SCD1U10V2KX-4GP
2
1
DY
3D3V_ICH_S5
Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]
C595
C609
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C644
C641
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C594
2
1
1
2
NO_STUFF
NO_STUFF
C642
C638
AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19
3D3V_S0
Vcc1_5_A[10]
Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]
C643
SCD1U10V2KX-4GP
Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]
Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]
1D05V_S0
AB10
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9
3D3V_S0
C636
SCD1U10V2KX-4GP
AE23
AE26
AH26
Vcc3_3[2]
SCD1U10V2KX-4GP
C605
SCD1U10V2KX-4GP
VccSATAPLL
AH11
C606
DY
C607
SCD1U10V2KX-4GP
3D3V_S5
AD2
1D5V_S0
SCD1U10V2KX-4GP
C612
1D5V_ICH_S0
ATX
Vcc1_5_A[1]
Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]
ARX
VccDMIPLL
AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5
1D5V_S0
1
2
R558 0R0603-PAD
Vcc3_3[1]
DY
R7
V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]
C616
3D3V_S5
B27
AG28
C647
C637
C649
1D5V_S0
SC10U10V5ZY-1GP SCD01U16V2KX-3GP
1
2
IND-1D2UH-5-GP
3D3V_S0
C597
SCD1U10V2KX-4GP
L21
1D5V_GPLL_ICH_S0
1D5V_S0
3D3V_S0
VccSus3_3/VccSusHDA
USB
2
2
C57
SCD1U16V2ZY-2GP
U6
R41
100R2J-2-GP
V5REF_S5
D15
CH751H-40PT
Vcc3_3/VccHDA
5V_S5
3D3V_S5
V5
V1
W2
W7
VCCA3GP
Layout Note:
Place near ICH7
C34
SCD1U16V2ZY-2GP
C611
V5REF_S0
R21
100R2J-2-GP
D7
CH751H-40PT
Vcc1_5_B[1]
Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]
1D05V_S0
C646
C610
C613
C617
C615
C699
SCD1U10V2KX-4GPSCD1U10V2KX-4GPSCD1U10V2KX-4GPSCD1U10V2KX-4GP
SC10U6D3V5MX-3GP
SCD1U10V2KX-4GP
5V_S0
3D3V_S0
AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23
V5REF_Sus
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
*Within a given well, 5VREF needs to be up before the

corresponding 3.3V rail
F6
Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]
Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
VCC PAUX Vcc1_05[20]
CORE
1
2
C619
C599
C618
C645
C627
C600
SCD1U10V2KX-4GP SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C61
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC10U10V5ZY-1GP
C60
SC10U6D3V5MX-3GP
1D5V_ICH7
2
0R0603-PAD
L20
V5REF[2]
IDE
V5REF_S5
V5REF[1]
AD17
PCI
1D5V_S0
USB CORE
G10
U20F
V5REF_S0
Layout Note:
Place near pin AA19
Rev
LWG2
SA
Sheet
E
17
of
52
U20E
P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27
3D3V_S5
32K suspend clock output

U11
1
2
3
16,30,33,38,40,49 PM_SLP_S3#
16 PM_SUS_CLK
OE
A
GND
VCC
32KHZ
1
R44
2
G792_32K 19
100R2J-2-GP
NC7SZ126P5X-GP
73.7S126.AAH
R43
240KR3-GP
63.24434.15L
SMBUS
5V_S0
3D3V_S0
4
3
3D3V_S5
RN9
SRN4K7J-8-GP
1
2
RN10
SRN4K7J-8-GP
Q37
S
D
16,22,26 SMB_DATA
SMBC_ICH 3,11
16,22,26 SMB_CLK
2N7002-7F-GP
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
4
3
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
1
2
A4
A23
B1
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D10
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F4
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G18
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J1
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M17
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P24
P27
SMBD_ICH 3,11
SB Mirror
Q36
2N7002-7F-GP
Q13 & Q14 connect SMLINK and

SMBUS in S) for SMBus 2.0
compliance
<Variant Name>
Wistron Corporation
ICH7-M-GP
Title
ICH7-M (4 of 4)
Size
A3
Document Number

A
Rev
LWG2
SA
Sheet
E
18
of
52
5V_S0
TP118
TP119
TPAD34 TPAD34
FAN1_VCC
R156
10KR2J-3-GP
FAN1_VCC
D21
FAN1_FG1
3
2
C119
SC2200P50V2KX-2GP
C227
SC1KP16V2KX-GP
*Layout* 15 mil
4
ACES-CON3-GP
20.F0714.003
BAS16-1-GP
FAN1
C173
SC4D7U6D3V3KX-GP
SCD1U16V2ZY-2GP
C120
*Layout* 15 mil
2nd source: 20.D0198.103
5V_S0
U18
ALERT#
THERM#
THERM_SET
RESET#
DGND
DGND
5
17
SGND1
SGND2
SGND3
8
10
12
G792_DXP2
G792_DXP3
V_DEGREE
R138
49K9R2F-L-GP
G792SFUF-GP
V_DEGREE
=(((Degree-72)*0.02)+0.34)*VCC
G792_DXN2
G792_DXN3
74.00792.A79
G68
C176
G792_DXN3 43
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
System Sensor, Put between CPU and NB.

System,VGA
M52/54: T[op]/105, Tj/125 degree.
H_THERMDA 4
Place near chip as close

as possible
30,33 PURE_HW_SHUTDOWN#
GAP-CLOSEGAP-CLOSE
DXP1:108 Degree (CPU)

DXP2:H/W Setting 100(System)
DXP3:105 Degree (VGA)
C126
G69
3D3V_AUX_S5
R119
100KR2J-1-GP
Q46
PMBS3904-1-GP
1
C687
SC470P50V3JN-2GP
G792_DXP3 43
ALERT#
Setting T8 as
100 Degree
R118 2
DY 0R2J-2-GP
THRM#
2
16
Change to 0R2-0 when using UMA

3
15
13
3
2
G792_32K 18
SMBD_KBC 30
SMBC_KBC 30
DXP1
DXP2
DXP3
1
4
14
16
18
19
C123
C125
C124
SC4D7U10V5ZY-3GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
FAN1
FG1
CLK
SDA
SCL
NC#19
7
9
11
1
R117
10KR2J-3-GP
1
R141
4K99R2F-L-GP
VCC
DVCC
C174
SC1U10V3ZY-6GP
6
20
5V_G792_S0
1
2
10R3J-3-GP
*Layout* 30 mil
R140
3D3V_S0
5V_S0
C175
SC2200P50V2KX-2GP
H_THERMDC 4
7,16 PWROK
For CPU Sensor
1 R139
2 G792_RESET#
4K7R2F-GP
R137
10KR2F-2-GP
Digital Output Data Bits

TEMP.
111
1110
011
+25.5
001
1001
100
+0.5
+0.125
-0.125
0
0
0
1
000
000
000
111
0001
0000
0000
1111
110
100
5V_AUX_S5
001
111
111
1110
111
-25.5
110
0110
100
-55.25
100
1000
110
-65.000
011
1111
000
1 R281
2 CPU_THSET
25K5R2F-GP
PURE_HW_SHUTDOWN#
1
2
3
SET
GND
OUT#
U34
-1.125
Thermal Get Setting
R280
10R2J-2-GP
HW thermal shut down tempature setting 95 degree

(18D2 KOhm), 85 degree (25.699 KOhm).
Put the back of CPU .
1
+1.75
Dummy when G792 enhanced T85V_AUX_S5

function
VCC
HYST
-1M modify
G709T1UF-GP
74.00709.A7F
Rset (K)=0.0012T*T-0.9308T+96.147
C367
SCD01U16V2KX-3GP
T6
T7
Sencor 0
CPU DTS
98
100
Sencor 1
G792-1 CPU
98
100
Sencor 2
G792-2 System
78
83
Sencor 3
G792-3 VGA
110
115
R278
0R0402-PAD
<Variant Name>
111
+126.375
CPU_TH_HYST
Wistron Corporation
EXT
1111
DY

R279
0R2J-2-GP
Title
Thermal/Fan Controllor G792
LSB
111
MSB
Sign
+127.875
Size
Custom
Document Number
Rev
SA
LWG2
Sheet
19
of
52
SATA Connector
7A
8A
9A
V5
V5
V5
13A
14A
15A
V12
V12
V12
18
16
14
12
10
8
6
4
3
5
7
9
11
13
15
17
DD15
DD14
DD13
DD12
DD11
DD10
DD9
DD8
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
35
33
36
37
38
DA0
DA1
DA2
CS0#
CS1#
B+
B-
S6
S5
AA+
S3
S2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NP1
NP2
CDROM1
44
32
11A
SATA
1
SC4700P50V2KX-1GP
1
SC4700P50V2KX-1GP
SATA
1
SATA
SC4700P50V2KX-1GP
1
SC4700P50V2KX-1GP
2
2C481
C482
2
2C480
C479
15
15
15
15
15
15
15
15
15
15
SATA_RXP0 15
SATA_RXN0 15
SATA_TXN0 15
SATA_TXP0 15
SATA
40
30
26
24
22
43
19
45
46
2
S1
S4
S7
4A
5A
6A
10A
12A
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
IDE_PDDREQ
IDE_PDIOR#
15 IDE_PDDACK#
5V_S0
15
15
IDE_PDA2
IDE_PDCS3#
C131
SC10U10V5ZY-1GP
C130
SCD1U16V2ZY-2GP
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
3D3V_S0
HDDDRV#_5
15
15
15
15
15
15
15
15
IDE_PDIOW#
15
IDE_PDA1 15
IDE_PDA0 15
IDE_PDCS1# 15
CDROM_LED# 13
CSEL
RN23
SRN8K2J-3-GP
IDE_PDIORDY 15
INT_IRQ14 15
5V_S0
-1 Modify
SATA
SPD-CONN50-4R-19GPU
20.80346.050
Close to Connector
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0
R374
0R2J-2-GP
49
NP1
NP2
RESERVED#44
RESERVED#32
RESERVED#11A
CDROM Connector
4
3
V33
V33
V33
20
28
34
1
39
31
27
25
23
21
29
1
2
1A
2A
3A
KEY
CSEL
PDIAG#
RESET#
DASP#
INTRQ
IORDY
DIOR#
DIOW#
DMARQ
DMACK#
TP50
TPAD30
+5V_MOTOR
+5V_LOGIC
CON44+15P+S7-GP
CDROM
20.F0794.066
PATA : 20.F0793.044
50
3D3V_S0 5V_S0
4
3
3V to 5V level shift for HDD
1
2
RN74
SRN10KJ-5-GP
Finger Print
7,16,22,26,30,32,42
3D3V_S0
3D3V_S5
1
R837
1
DY R833
0R3-0-U-GP
FP_PWR
0R3-0-U-GP
16
16
USB_PP3
USB_PN3
PLT_RST1#
HDDDRV#_5
Q25
2N7002-7F-GP
FP1
EC: N060446
4
3
2
1
C439
SC10U10V5ZY-1GP
1
2
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
K
A
C440
42
41
TP55
TPAD30
5V_S0
D27
EC26
SSM22LLPT-GP
HDD1
5V_S0
SC2D2U10V3KX-GP
C908
PWR TRACE 100mil
5
ACES-CON4-3-GP
20.K0220.004
<Variant Name>
Wistron Corporation
Title
Size
A3
SATA HDD / ODD /FINGER PRINT

Document Number
Rev
LWG2
SA
Sheet
20
of
52
for USB GPIO control SB & KBC function change

R25
5V_USB5_S5
5V_S5
USB_EN1#
USB_EN1#
GND
IN
IN
EN#/EN
8
7
6
5
OUT
OUT
OUT
FLG
USB_EN1#_SB 16
USB_EN2#
USB_EN2#_SB 16
USB_EN3#
0R2J-2-GP
R38
1
2
USB_EN3#_SB 16
USB_OC#0 16
G528P1UF-GP
C911
R843
100KR2J-1-GP
5V_USB2_S5
USB_EN1#
R39
USB_EN2#
R46
USB_EN3#
R40
DUMMY-R2
USB_EN1#_KBC 30
DUMMY-R2
USB_EN2#_KBC 30
DUMMY-R2
USB_EN3#_KBC 30
0R2J-2-GP
only SB use
only KBC use

5V_USB5_S5
USB1
7
5
5V_USB1_S5
U89
60 mil
8
7
6
5
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1
2
C810
L28
DY
16 USB_PN0
16 USB_PP0
4
FILTER-79-GP
69.10084.071
1
2
USB_1USB_1+
C812
2
3
4
6
8
SKT-USB-105-GP-U
22.10218.J11
1
2
R632 0R2J-2-GP
1
2
R631 0R2J-2-GP
-1 Modify
R844
100KR2J-1-GP
C915
SC47U6D3V0MX-1GP
C912
C913
C914
SC47U6D3V0MX-1GP
74.00546.A7D
USB_OC#4 16
USB GPIO Control on SB version G546A2P1UF-GP
R850
100KR2J-1-GP
USB_OC#2 16
SCD1U10V2KX-4GP
USB_EN3#
USB_EN2#
GND
OC1#
IN
OUT1
EN1/EN1# OUT2
EN2/EN2# OC2#
SC1KP16V2KX-GP
1
2
3
4
5V_USB5_S5
5V_S5
0R2J-2-GP
R26
1
2
SCD1U10V2KX-4GP
1
2
3
4
U88
5V_USB2_S5
L33
BLUETOOTH MODULE CONNECTOR
5V_USB2_S5
BLUETOOTH_EN 30
AAT4250IGV-T1-GP
C827
74.04250.A3F
4
FILTER-79-GP
69.10084.071
2
0R2J-2-GP
2
0R2J-2-GP
C828 1
2 SCD1U16V2ZY-2GP
C808
ACES-CON4-1-GP
20.D0197.104
2nd source: 20.F0760.004
MDC 1.5 CONN
SKT-USB-105-GP-U
22.10218.J11
1
2
R651 0R2J-2-GP
1
2
R652 0R2J-2-GP
USB3
7
5
139R2J-L-GP2 AC_DIN1A_R
1
2
R748
DUMMY-R2
3
5
7
9
11
MH2
16
4
6
8
10
12
17
18
EC563
AMP-CONN12A-GP
C562
3 SC22P50V2JN-4GP
R69
BAT54A-1-AS
2
10KR2J-3-GP
20.F0582.012
2nd source: 20.F0604.012
16 USB_PP2
4
FILTER-79-GP
69.10084.071
USB_3USB_3+
2
3
4
TC16
ST100U6D3VDM-5
80.10715.591
6
8
SKT-USB-105-GP-U
22.10218.J11
1
2
R685 0R2J-2-GP
1
2
R684 0R2J-2-GP
USB PORT
C564
SC1U10V3KX-3GP
ACZ_BTCLK_MDC 15
D44
<Variant Name>
R494
DY
16 USB_PN2
R495
100KR2J-1-GP
Wistron Corporation
15,28 ACZ_SYNC
15 ACZ_SDATAIN1
15 ACZ_RST_MDC#
15
14
2
13
MH1
1
SC22P50V2JN-4GP
15,28 ACZ_SDATAOUT
MDC_KILL#
2
3
4
6
8
3D3V_LAN_S5
MDC1
16
USB_5USB_5+
C809
3D3V_BT_S0
C910
L38
C909
60 mil
USB_PN1 16
USB_PP1 16
1
R4281
R429
4
FILTER-79-GP
69.10084.071
5V_USB1_S5
SC1KP16V2KX-GP
4
3
2
16 USB_PP4
5V_USB1_S5
SCD1U10V2KX-4GP
BT1
DY
L47
TC23
4
SCD1U10V2KX-4GP
CardR
Place near BT1
SCD1U10V2KX-4GP
OUT
IN
GND
NC#3 ON/OFF#
ST100U6D3VDM-5
1
2
3
SC1KP16V2KX-GP
U80
3D3V_BT_S0
3D3V_S0
7
5
DY
16 USB_PN4
60 mil
USB2
Title
USB and MDC I/F
3D3V_LAN_S5
Size
A3
Document Number
Rev
LWG2
SA
Sheet
21
of
52
P10
N10
16 PCIE_TXP1
16 PCIE_TXN1
C857 SC4D7U10V5ZY-3GP
R755
4K7R2F-GP 5789
PCIE_SDSVDD
R756 1
2
4K7R2F-GP
1 L46
2
0R0603-PAD
AVDDL_G
C859 SC4D7U10V5ZY-3GP
C860
SCD47U10V3ZY-GP
GIGA
2
DY
1
0R2J-2-GP
1
0R2J-2-GP
16,18,26 SMB_CLK
16,18,26 SMB_DATA
G14 GPHY_PLLVDD
Q53
B
5787
REGCTL25
L13
REGCTL25
REGCTL12
J13
REGCTL12
SC4D7U10V5ZY-3GP
2
1
C
MMJT9435T1G-GPU
C864
C862
5787
PERST#
WAKE#
AVDD
AVDD
H2
J2
H3
VMAINPRESNT
LOW_PWR
PWR_IND_LED#
ATTN_IND_LED#
CLKREQ#
REFCLK_SE
M1
K1
L1
SRN49D9F-GP
3 MDI3+
4 MDI32
1
3 MDI2+
4 MDI22
1
1
SCD1U16V2ZY-2GP
2
MDI0+
MDI0-
23
23
TRD1P
TRD1N
C13
C14
MDI1+
MDI1-
23
23
TRD2P
TRD2N
D13
D14
MDI2+
MDI2-
23
23
TRD3P
TRD3N
E13
E14
MDI3+
MDI3-
23
23
CS#
SSCLK
SI
SO
C12
E11
E12
F11
GPIO0
GPIO1
GPIO2
ENERGY_DET
G12
H13
G13
C4
SPEED1000LED#
SPD100LED#
TRAFFICLED#
LINKLED#
A12
B11
B10
A11
TRST#
TMS
TDI
TCK
TDO
D12
C11
H12
D7
D6
RDAC
NC#K14
NC#L8
NC#L9
UART_MODE
SERIAL_DI
SERIAL_DO
EEDATA
EECLK
TEST#
GPHY_TVCOI
LAN_X1_G
GIGA GIGA
"GIGA"
"5789"
"5787"
GIGA
P12
X8
R765 1LAN_X0_G
N12
GIGA200R2J-L1-GP
5787
CS# 1
2
R757 4K7R2J-2-GP
SO
TPAD28 TP78
DY
R760
1
210KR2J-3-GP
LAN_EE_WP
1 R761
2
10KR2J-3-GP
5789
1G_LED# 23
100M_LED# 23,51
LAN_ACT_LED# 23,51
10M_LED# 23,51
1
2
R796 4K7R2F-GP
GIGA
L10 LAN_EEDATA
K11 LAN_EECLK
1
2
L7
R763 4K7R2F-GP
5787
1
2
R764 4K7R2F-GP
5789
XTALO
GIGA
BCM5787MKFBG-GP
C871
D8
XTALI
XTAL-25MHZ-70GP
82.30020.581
C870
C867
GIGA
SC33P50V2JN-3GP
2
GIGA
C866
SCD1U10V2KX-4GP
2
1
C869
SC27P50V2JN-2-GP
1D2V_LAN_S5
BCM5787MKFBG-GP
71.05787.00U
SRN49D9F-GP
B13
B14
SMB_CLK
SMB_DATA
3D3V_LAN_S5
K14
L8
L9
TRD0P
TRD0N
GIGA
SCD1U10V2KX-4GP
2
1
GIGA
5789
A13 AVDD_A13
F14 AVDD_F14
E
C868
5789
C847
VAUX_PRESENT
ATTN_BTN#
DY
Q54
MMJT9435T1G-GPU
SC10U10V5ZY-1GP
2
1
C
C2
A6
C865
SCD1U10V2KX-4GP
GIGA
GIGA
REFCLK+
REFCLK-
GIGA
SC4D7U10V5ZY-3GP
2
1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J6
J7
J8
J9
K2
2
1
M5
5787
2 R7665787
10R2J-2-GP
M7
2 R7675787
10R2J-2-GP
M10
R768
0R2J-2-GP
N1
2
1
N5
5787
2 R7695787
10R2J-2-GP
N7
R770
0R2J-2-GP
N9
2
1
N11 LAN_N11
5787
2 R7725787
10R2J-2-GP
P5
R771
2
10R2J-2-GP
P7
5787
R773
0R2J-2-GP
P9
2
1
P11
5787
R774
0R2J-2-GP
H14 XTALVDD_G
PCIE_TXDN
2LAN_SMB_CLK D10
R749 2LAN_SMB_DATAD9
R758
R759 2
A10
578711K24R2F-GP
3D3V_LAN_S5GIGA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
XTALVDD
P6
CLK_SEL F4
2D5V_LAN_S5
GIGAGIGA
A14 BIASVDD_G
PCIE_SDSVDD
M6
C863
C861
PCIE_SDSVDD
M8
SCD1U10V2KX-4GP
SC10U10V5ZY-1GP
2
1
2
1
PCIE_PLLVDD
SC4D7U10V5ZY-3GP
3D3V_LAN_S5
PCIE_PLLVDD
BIASVDD
N8
P8
R752GIGA
2
1VAUX_PRESENT
J12
1 5787 2 1KR2J-1-GP A2
R753
4K7R2J-2-GP
3D3V_LAN_S0 1
5789 24K7R2J-2-GP
R754
1KR2J-1-GP
1
L3
DY 2R775
2
1LOW_PWR
L6
R762 0R0402-PAD
3D3V_LAN_S0
C858
SCD47U10V3ZY-GP
GIGA
2
GPHY_PLLVDD
PCIE_PLLVDD
DY
C848
3D3V_LAN_S5
1
2
C850
1 L43
2
0R0603-PAD
GIGA
7,16,20,26,30,32,42 PLT_RST1#
16,30 PCIE_WAKE#
C856
C855
GIGA
CLK_PCIE_LAN
CLK_PCIE_LAN#
3 CLK_PCIE_LAN
3 CLK_PCIE_LAN#
DY
SCD1U16V2KX-3GP
2
SCD1U16V2KX-3GP
2
16 PCIE_RXP1
16 PCIE_RXN1
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1
2
1
1 L45
2GPHY_PLLVDD
0R0603-PAD
F12
F13
DY
AVDDL
AVDDL
1 L42
2 AVDDL_G
0R0603-PAD
C854
5789
PCIE_RXDP
PCIE_RXDN
GIGA
1C849N6GIGA
PCIE_TXDP
C853
GIGA
<Variant Name>
-2 modify
Wistron Corporation
-- stuff when 5789 or 5787M.

-- stuff when 5789.
-- stuff when 5787.
Title
BCM5787M / BCM5789
Size
A3
Document Number
Rev
LWG2

5
SCD1U16V2ZY-2GP
2
2
1
GIGA
B8
E5
E6
E7
E8
E9
E10
F5
F10
G4
J4
J5
J10
K4
K5
K6
K7
K8
C844
U83A
Place PLLVDD/AVDDL
1D2V_LAN_S5 CKT as close to chip as
possible
SCD47U10V3ZY-GP
SCD47U10V3ZY-GP
A8
D5
P13
D11
G11
K12
SCD1U10V2KX-4GP
2
1
GIGA GIGA
BCM5789
BCM5787M
VDDC1.2
VDDC1.2
VDDC1.2
VDDC1.2
VDDC1.2
VDDC1.2
VDDC1.2
VDDC1.2
VDDC1.2
VDDC1.2
VDDC1.2
VDDC1.2
VDDC1.2
VDDC1.2
VDDC1.2
VDDC1.2
VDDC1.2
VDDC1.2
RN106
5789
SCD1U10V2KX-4GP
1D2V_LAN_S5
RN105
C846
SCD1U10V2KX-4GP
GIGA
RN104
5789
GIGA
SCD1U10V2KX-4GP
1 L44
2AVDD_F14
0R0603-PAD
C851
SRN49D9F-GP
RN103
5789
SCD1U16V2ZY-2GP
2
AT24C256N-10SU-GP
1
2
3
4
2
1
A0
A1
NC#3
GND
5789
GIGA
VCC
WP
SCL
SDA
3 MDI1+
4 MDI1-
1
2
GIGA
8
7
6
5
LAN_EE_WP
LAN_EECLK
LAN_EEDATA
BIASVDD_G
C843
5789
2
1
SCD1U10V2KX-4GP
2
1
1 L40
2
0R0603-PAD
C872
SCD1U10V2KX-4GP
U84
1 L41
2AVDD_A13
0R0603-PAD
C845 GIGA
B4
B7
B12
E2
F6
F7
F8
F9
G5
G6
G7
G8
G9
G10
H5
H6
H7
H8
H9
H10
SCD1U10V2KX-4GP
2
1
GIGA
SCD1U10V2KX-4GP
2
1
GIGA
GIGA
VDDP_G
VDDIO
VDDID
VDDID
U83B
5789
1R776
2
0R3-0-U-GP
SCD1U10V2KX-4GP
2
1
C839
R746
1KR2J-1-GP
SCD1U10V2KX-4GP
C852
R747
0R0402-PAD
VDDP
VDDP
VDDP
1 R751
2
0R0603-PAD
A1 DC
A3 DC
A4 DC
C838
A5 DC
VDDIO_PCI_G
A7 DC
A9 DC
B1 DC
B2 DC
B3 DC
GIGA
B5 DC
B6 DC
B9 DC
C1 DC
C3 DC
C5 DC
C6 DC
C7 DC
C8 DC
C9 DC
C10 DC
D1 DC
D2 DC
D3 DC
D4 DC
E1 DC
E3 DC
E4 DC
F1 DC
F2 DC
F3 DC
G1 DC
G2 DC
G3 DC
H1 DC
H4 DC
H11 DC
J1 DC
J3 DC
J11 DC
1D2V_LAN_S5
J14 DC
K3 DC
K9 DC
K10 DC
K13 DC
L2 DC
L4 DC
L5 DC
L11 DC
L12 DC
3D3V_LAN_S5
L14 DC
M2 DC
M3 DC
M4 DC
M9 DC
M11 DC
M12 DC
M13 DC
2D5V_LAN_S5
M14 DC
N2 DC
N3 DC
N4 DC
N13 DC
N14 DC
P1 DC
P2 DC
P3
C837
C836
C835 P4 DC
DC
P14 DC
SCD1U10V2KX-4GP
2
1
SCD1U10V2KX-4GP
2
1
GIGA
3D3V_LAN_S0
3D3V_LAN_S5
3D3V_S5
R750
0R3-0-U-GP
5789
2D5V_LAN_S5
3D3V_S0
C840
5789
R745
1KR2J-1-GP
GIGA
SCD1U10V2KX-4GP
GIGA
C834
1
2
1
2
GIGA
C799
SCD1U10V2KX-4GP
GIGA
C830
SCD1U10V2KX-4GP
1
2
C802
SCD1U10V2KX-4GP
GIGA
SCD1U10V2KX-4GP
1
2
1
2
GIGA
C801
GIGA
5789
R744
1KR2J-1-GP
SCD1U16V2ZY-2GP
2
GIGA
C800
SCD1U10V2KX-4GP
GIGA
SCD1U10V2KX-4GP
C797
C798
SCD1U10V2KX-4GP
1D2V_LAN_S5
SCD1U10V2KX-4GP
1
2
C841
1 L39
2XTALVDD_G
0R0603-PAD
C842 GIGA
3 MDI0+
4 MDI0-
3D3V_LAN_S5
2D5V_LAN_S5
3D3V_LAN_S5
CLOSE TO GPHY PINS
SRN49D9F-GP
SA
Sheet
1
22
of
52
Voltage
Rail
4401E
5789
5787
VDDIO_PCI
3D3V_LAN_S5
VDDC
1D8V_LAN_S5
1D2V_LAN_S5
VDDIO
3D3V_LAN_S5
3D3V_LAN_S5
VESD
3D3V_LAN_S5
VDDP
Don't Care
Don't Care
3D3V_S0
LAN Connector
Don't Care
3D3V_S0
2D5V_S5
RJ1
3D3V_2D5V_S5
3D3V_S5
2D5V_S5
1D8V_1D2V_S5 1D8V_LAN_S5
CONN_PWR_2
1D2V_S5
22,51 LAN_ACT_LED#
RJ45_2
RJ45_3
RJ45_4
RJ45_5
RJ45_6
RJ45_7
RJ45_8
D36
MCT4
MCT3
MCT2
MCT1
22,51 10M_LED#
22,51 100M_LED#
22
RJ45_1
CONN_PWR_1
LAN_LED#
8
7
6
5
RN6
SRN75J-1-GP
1G_LED#
LED COLOR
9
B1
NP1
B2
RJ45_1
B2:YELLOW
RJ45_2
RJ45_3
RJ45_4
RJ45_5
RJ45_6
RJ45_7
RJ45_8
A1
A2
A3
RJ11_1
RJ11_2
NP2
10
A1:Amber
A3:GREEN
RJ45-107-GP-U
22.10245.J01
1
2
3
4
CH731UPT-GP
LAN Link: Green(A3), behavior is the

same for 10/100/1000 bits
EC2
3D3V_LAN_S5
R471
0R2J-2-GP
1
2
RJ45-1
TD- --> TX-
RJ45-2
RD+ --> RX+
RJ45-3
RD- --> RX-
RJ45-6
RX+
RXRXCT
TXCT
TX+
TX-
12
11
10
9
8
7
1
2
RJ45_7
RJ45_8
MCT4
MCT3
RJ45_4
RJ45_5
TIP
2
HFB1608VF-102-GP
RING
2
HFB1608VF-102-GP
1
L5
1
L4
ACES-CON2-GP-U
20.F0714.002
2nd source: 20.D0196.102

2
XFORM-208-GP
68.68161.30A
GIGA
51
51
51
51
1
2
C552
22
22
MDI1+
MDI1-
22
22
C551
MDI0+
MDI0-
MDI1+
MDI1MDI0+
MDI0-
1
2
3
4
5
6
RD+
RDRDCT
TDCT
TD+
TD-
RX+
RXRXCT
TXCT
TX+
TX-
RJ45_3
RJ45_6
MCT2
MCT1
RJ45_1
RJ45_2
12
11
10
9
8
7
LAN_LED#
LAN_ACT_LED#
XFORM-208-GP
MDI0+_M
MDI0-_M
MDI1+_M
MDI1-_M
2 R486
4401E
2 R491
4401E
2 R492
4401E
2 R501
4401E
0R2J-2-GP
1
0R2J-2-GP
1
0R2J-2-GP
1
0R2J-2-GP
1
CONN_PWR_1
2
470R2J-2-GP
3D3V_LAN_S5
3D3V_LAN_S5
CONN_PWR_2
1 R473 470R2J-2-GP
2
R10
<Variant Name>
ERC1
SRC100P50V-2-GP
77.61012.02L
Wistron Corporation
1
2
3
4
TD+ --> TX+
MDI2+
MDI2-
RD+
RDRDCT
TDCT
TD+
TD-
8
7
6
5
RJ45 PIN
1
1
2
10/100 LAN Transformer
C17
SCD1U10V2KX-4GP
22
22
XF1
SCD1U10V2KX-4GP
DOC_TIP,DOC_RING,TIP,RING:
W/S : 10/100 @ Surface layers
10/20 @ Inner layers
C16
1
2
3
4
5
6
MDI3+
MDI3-
SCD1U10V2KX-4GP
1.route on bottom as differential pairs.

2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.
3.No vias, No 90 degree bends.
4.pairs must be equal lengths.
5.6mil trace width,12mil separation.
6.36mil between pairs and any other trace.
7.Must not cross ground moat,except
RJ-45 moat.
TRING1
XF2
22
22
SCD1U10V2KX-4GP
For Modem Cable from MDC
4401E
TCT1
RJ11 signal must leave the other signal

or power plane 100mil.
2
SC1KP2KV8KX-LGP
LAN Data: Yellow(B2), when LAN is

transfering data.
R478
0R2J-2-GP
GIGA
2D5V_LAN_S5
LAN_TERMINAL

Title
LAN Connector
Size
A3
Document Number
Rev
LWG2
Date: Monday, June 12, 2006

A
SA
Sheet
E
23
of
52
C766 should close Pin-P15

and Pin-R17.
SD_WP
26
SM_R#
25,27
25,27
Should be places as close to

PCI7412 as possible
C764
C765
SC1KP16V2KX-GP
2
1
C769
SCD1U10V2KX-4GP
3D3V_S0
CBB_A13 27
Bypass/Decupoling Capacitors
H14
CPAR/A13
* All 1394 signals must be routed on top side only

* Differential pairs of each ports should have equal trace length
* Stubs must be keep as short as possible
CBB_D3 27
CBB_D4 27
CBB_D11 27
CBB_D5 27
CBB_D12 27
CBB_D6 27
CBB_D13 27
CBB_D7 27
CBB_D15 27
CBB_A10 27
CBB_CE2# 27
CBB_OE# 27
CBB_A11 27
CBB_IORD# 27
CBB_A9 27
CBB_IOWR# 27
CBB_A17 27
CBB_A24 27
CBB_A7 27
CBB_A25 27
CBB_A6 27
CBB_A5 27
CBB_A4 27
CBB_A3 27
CBB_A2 27
CBB_A1 27
CBB_A0 27
CBB_D0 27
CBB_D8 27
CBB_D1 27
CBB_D9 27
CBB_D10 27
SCD1U10V2KX-4GP
P19
N18
N17
M15
N19
M18
M17
L19
L18
L15
K18
K17
K15
J18
J15
J17
H19
F15
E17
D19
A16
E14
B15
B14
A14
C13
B13
C11
E11
F11
A10
C10
SC1KP16V2KX-GP
2
1
CAD0/D3
CAD1/D4
CAD2/D11
CAD3/D5
CAD4/D12
CAD5/D6
CAD6/D13
CAD7/D7
CAD8/D15
CAD9/A10
CAD10/CE2#
CAD11/OE#
CAD12/A11
CAD13/IORD#
CAD14/A9
CAD15/IOWR#
CAD16/A17
CAD17/A24
CAD18/A7
CAD19/A25
CAD20/A6
CAD21/A5
CAD22/A4
CAD23/A3
CAD24/A2
CAD25/A1
CAD26/A0
CAD27/D0
CAD28/D8
CAD29/D1
CAD30/D9
CAD31/D10
CC/BE3#/REG#
CC/BE2#/A12
CC/BE1#/A8
CC/BE0#/CE1#
E13
E18
H18
L17
SD_WP/SM_CE#
SD_CMD/SM_ALE
SD_CLK/SM_RE#
MC_PWR_CTRL_1/SM_R/B#
MC_PWR_CTRL_0
SD_CD#
CBB_D[0..15]
CBB_A[0..25]
C778
3D3V_S0
SC1KP16V2KX-GP
2
1
A15
W8
P1
P10
P8
P6
L14
L6
J14
J6
F14
F12
F9
F6
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCCB
AVDD_33
AVDD_33
AVDD_33
SD_DAT3/SM_D7
SD_DAT2/SM_D6
SD_DAT1/SM_D5
SD_DAT0/SM_D4
VSSPLL
U38A
C770
PCI7412ZHK-GP
CBB_CE1# 27
CBB_A8 27
CBB_A12 27
CBB_REG# 27
SD_CD# 26
3D3V_S0
4
3
26
E7
C5
A4
F8
MC_PWR_CTRL1_0 C8
E9
1394_AGND
R17
U14
U13
R14
71.07412.B0U
E6
B5
A5
C6
PAR
VCCP
VCCP
J19
U15
P14
P13
1
U19
P15
VDDPLL_33
VDDPLL_15
K19
K1
1
1
U7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PCI_PAR
SCD1U16V2ZY-2GP
TI PCI7412
AGND
AGND
AGND
16,51
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
P9
P7
N6
M14
K14
K6
H6
G14
F13
F10
F7
R11
P11
U11
V11
W11
R10
U10
V10
R9
U9
V9
W9
V8
U8
R8
W7
W4
T2
T1
R3
P5
R2
R1
P3
N3
N2
N1
M5
M6
M3
M2
M1
VR_PORT
VR_PORT
K2
VR_EN#
C/BE3#
C/BE2#
C/BE1#
C/BE0#
16,25,51 PCI_AD[0..31]
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
C776
C766
SCD1U16V2ZY-2GP
C442 C423
1 OF 2
3D3V_S0
VCCCB
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
P2
U5
V7
W10
16,51
16,51
16,51
16,51
VCC_ASKT_S0
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
2
1394_AGND 3D3V_PLL_S0
4
CardR
<Variant Name>
C762
C767
C
Q48
CHT2222APT-GP
SC1U6D3V2KX-GP
1
2
C768
MC_PWR_CTRL 26
SC1KP16V2KX-GP
2
1
3D3V_PLL_S0
1 R648
2
0R0603-PAD
3D3V_S0
CardR
SC1U6D3V2KX-GP
RN101
SRN10KJ-5-GP
Wistron Corporation
Title
TI PCI7412 (1 of 2)
Size
A3
Document Number

A
Rev
LWG2
SA
Sheet
E
24
of
52
TP81
TPAD28
TP48
TPAD28
1
1
1
E5
W12
V12
U12
MS_D[1..3] 26
1394_R1
T19
2 1394_R0T18
R322
R12
1
6K34R2F-GP
1394_XI
X5
X-24D576MHZ-46GP
82.30023.351
1394
C422
SC12P50V2JN-3GP
R18
R19
-2 modify
1394
1394_XO
2
1
C441
SC15P50V2JN-2-GP
R1
R0
CPS
XO
XI
1394
B10
C4
D1
E1
E2
E3
F2
F3
F5
G6
H17
M19
1394
CBB_A16 27
3
A3
B4
B8
CLK_48
A_USB_EN#
CBLOCK#/A19
TEST0
RSVD#G5
J5
H3
G3
G2
L5
P17
J3
J2
J1
H1
H2
H5
G1
R655
2
10KR2J-3-GP
1 R343
1 R653
3D3V_PLL_S0
RN68
INTD#
3
4
PM_CLKRUN# 16,30,51
3D3V_S0
2
1
INT_SERIRQ
INT_PIRQF#
INT_PIRQB#
INT_PIRQG#
SRN4K7J-8-GP
INTC#
INTB#
INTA#
F1
E10
H15
P12
G5
PCI_SPKR 28
47KR2J-2-GP
2 4K7R2J-2-GP
CLK48_CARDBUS
16,30
16
16
16
INTA#
INTB#
INTC#
INTD#
CARBUS 1 (INT_PIRQG#)
1394 (INT_PIRQB#)
Flash Media (INT_PIRQF#)
SD Host (INT_PIRQG#) share
MFUNC4: use bit 19-16 Register define.
CBB_A19 27
MC_PWR_CTRL-1
TP80 TPAD30
GRST#
PCLK
PRST#
1394_TPA0P
1394_TPA0N
2
33R2J-2-GP
CBB_WP 27
CBB_RESET 27
K5
L1
K3
26
26
MFUNC6
MFUNC5
MFUNC4
MFUNC3
MFUNC2
MFUNC1
MFUNC0
CCD1#/CD1#
CCD2#/CD2#
1394_AGND
SUSPEND#
SPKROUT
SDA
SCL
RI_OUT#/PME#
PHY_TEST_MA
CVS1/VS1#
CVS2/VS2#
1394_TPB0P
1394_TPB0N
TPBIAS1
TPBIAS0
TPB1P
TPB1N
TPB0P
TPB0N
TPA1P
TPA1N
TPA0P
TPA0N
1 R337
F18
A11
C15
3D3V_S0
IDSEL:AD22
INTA-->:INT_PIRQG#
INTB-->:INT_PIRQB#
INTC-->:INT_PIRQF#
INTD-->:INT_PIRQG#
GNT:PCI_GNT#0
REQ:PCI_REQ#0
N15
B11
W17
R13
V15
W15
V13
W13
V16
W16
V14
W14
1394
XD_CD#/SM_PHYS_WP#
SM_CLE
SM_CD#
A13
B16
26
26
1394_TPBIAS1
2
SCD1U16V2ZY-2GP
MS_DATA3/SD_DAT3/SM_D3
MS_SDIO/DATA0/SD_DAT0/SM_D0
MS_CLK/SD_CLK/SM_EL_WP#
MS_CD#
MS_BS/SD_CMD/SM_WE#
CAUDIO/BVD2/SPKR#
CDEVSEL#/A21
CFRAME#/A23
CGNT#/WE#
CINT#/READY/IREQ#
CIRDY#/A15
CPERR#/A14
CREQ#/INPACK#
CSERR#/WAIT#
CSTOP#/A20
CSTSCHG/BVD1/STSCHG#/RI#
CTRDY#/A22
1
C763
26 1394_TPBIAS0
CCLK/A16
CCLKRUN#/WP/IOIS16#
CRST#/RESET
B12
F19
E19
G17
E12
F17
G19
C14
C12
G18
A12
G15
26
B6
A6
C7
B7
A7
A8
E8
MS_D3
MS_D2
MS_D1
MSCSDIO
MS_CLK
MS_CD#
MSCBS
U38B
PCI7412ZHK-GP
TI PCI7412
LATCH/VD3/VPPD0
CLOCK/VD1/VCCD0#
DATA/VD2/VPPD1
26
26
TRDY#
STOP#
SERR#
REQ#
PERR#
IRDY#
IDSEL
GNT#
FRAME#
DEVSEL#
C9
A9
B9
26
26
26
26
W5
V6
W6
L3
R7
V5
R654
7412_IDSEL
2
N5
100R2F-L1-GP-U
L2
R6
U6
RSVD#B10/D2
RSVD#C4/VD0/VCCD1#
RSVD#D1
RSVD#E1
RSVD#E2
RSVD#E3
RSVD#F2
RSVD#F3
RSVD#F5
RSVD#G6
RSVD#H17/A18
RSVD#M19/D14
16,51 PCI_TRDY#
16,51 PCI_STOP#
16,51 PCI_SERR#
16
PCI_REQ#0
16,51 PCI_PERR#
16,51 PCI_IRDY#
16,24,51 PCI_AD22
16
PCI_GNT#0
16,51 PCI_FRAME#
16,51 PCI_DEVSEL#
NC#E5
2 OF 2
2
GAP-CLOSE
1394_AGND
PC2
PC1
PC0
G89
TP49
TPAD28
TP79
TPAD28
PCIRST1# 16,27,51
PCLK_PCM 3
3D3V_S0
27
CBB_CD2# 27
CBB_CD1# 27
CBB_VS2# 27
CBB_VS1# 27
CBB_A22 27
CBB_BVD1# 27
CBB_A20 27
CBB_WAIT# 27
CBB_INPACK# 27
CBB_A14 27
CBB_A15 27
CBB_RDY 27
CBB_D2
1 R344
2
43KR2J-GP
27
27
27
27
27
27
27
27
27
CBB_A18
CBB_D14
CB_LATCH
CB_CLOCK
CB_DATA
CBB_BVD2#
CBB_A21
CBB_A23
CBB_WE#
<Variant Name>
Wistron Corporation
Title
TI PCI7412 (2 of 2)
Size
A3
Document Number

A
Rev
LWG2
SA
Sheet
E
25
of
52
3D3V_S5
Mini Card Connector

3D3V_S0
1394 Connector
1D5V_S0
MINIC2
DY
TP61
13
WLAN_LED#
TP60 TPAD28
1 LED_WPAN#
WLAN_LED#
1 LED_WWAN#
42
44
46
LED_WWAN#
LED_WLAN#
LED_WPAN#
25 1394_TPB0N
TPAD30
PLT_RST1# 7,16,20,22,30,32,42
1394
4
9
15
18
21
26
27
29
34
35
40
50
53
54
1394
TPA0+
TPA0TPB0+
4
3
2
TPB0-
1
5
L13
SKT-1394-4P-12GP
69.10084.071
1394
R304
56R2J-4-GP R306
56R2J-4-GP
1394
62.10027.451
1394
25 1394_TPBIAS0
C402
SC1U10V3ZY-6GP
1394
Close to TI7412(Device)
C403
R305
5K1R2-GP
1394
1394
3D3V_CR_S0
62.10043.231
3D3V_S0
1D5V_S0
MS_D[1..3] 25
3D3V_S5
NP1
NP2
SKT-MINI52P-3-GP
1394
FILTER-79-GP
1
R302
R303
56R2J-4-GP 56R2J-4-GP
CN1
TP62
1
7
22
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
3
SMB_CLK 16,18,22
SMB_DATA 16,18,22
DY
WAKE#
CLKREQ#
PERST#
1
4
SMB_CLK
SMB_DATA
25 1394_TPA0N
25 1394_TPB0P
NP1
NP2
TPAD28
2
30 R8001
2
32 R8011 0R2J-2-GP
USB_PN6 16
USB_PP6 16
DY
0R2J-2-GP
1394
25 1394_TPA0P
R476
10KR2J-3-GP
USB_DUSB_D+
36
38
69.10084.071
L12 FILTER-79-GP
PCIE_TXN2 16
PCIE_TXP2 16
RF_ON/OFF#
30
31
33
C790
UIM
RESERVED#3
RESERVED#5
RESERVED#8
RESERVED#10
RESERVED#12
RESERVED#14
RESERVED#16
RESERVED#17
RESERVED#19
RESERVED#20
RESERVED#37
RESERVED#39
RESERVED#41
RESERVED#43
RESERVED#45
RESERVED#47
RESERVED#49
RESERVED#51
PETN0
PETP0
SB mirror
3
5
8
10
12
14
16
17
19
20
37
39
41
43
45
47
49
51
+3.3VAUX
PCIE_RXN2 16
PCIE_RXP2 16
SC220P50V3JN-GP
24
23
25
+3.3V
PERN0
PERP0
52
CLK_PCIE_MINI1 3
CLK_PCIE_MINI1# 3
+1.5V
+1.5V
13
11
3.3V
REFCLK+
REFCLK-
2
28
48
MINIC
1.5V
C788
C791
MS_D1
MSCSDIO
MS_D1
MS_D2
MS_D3
MSCBS
MS_CLK
24
24
SD_CD#
SD_WP
25
25
SD_WP
SD_VCC
SD_7
SD_8
SD_9
SD_1
SD_DAT0
SD_DAT1
SD_DAT2
SD_DAT3
SD_2
SD_5
SD_CD1
SD_WP1
MS_6
MS_2
MS_CD#
MSCBS
MS_VCC
MS_VCC
SD_4
MS_SDIO
MS_SCLK
NP1
NP2
NP3
NP4
MS_RESERVED
MS_RESERVED
SD_CMD
SD_CLK
SD_CD/DETECT
SD_WP/PROTECT
MS_INS
MS_BS
MS_4
MS_8
MS_5
MS_7
SD_VSS
SD_VSS
SD_3
SD_6
MS_VSS
MS_VSS
MS_10
MS_1
GND
GND
MSCSDIO 25
MS_CLK 25
NP1
NP2
NP3
NP4
DY DY
R88
R834
2
22KR2J-GP
CARD1
MS_9
MS_3
R146
CardR
2
22KR2J-GP
CardR CardR
C56
SCD1U16V2ZY-2GP
1
100KR2J-1-GP
1
2
100KR2J-1-GP
SC1U10V3ZY-6GP SCD1U16V2ZY-2GP
R741DY
SCD1U16V2ZY-2GP
1
2
1
2
Place near MINIC2
C572
SCD1U16V2ZY-2GP
1
2
C59
SC1U6D3V2KX-GP
1
2
C573
SCD1U16V2ZY-2GP
SC1U6D3V2KX-GP
DY
C58
MS_D2
MS_D3
SM_R# 24
MS_CLK
SD_WP 24
MSCBS
SD_CD2
SD_WP2
SKT-3IN1-GP
20.I0039.001
Bottom VIEW
1
36
Reader
POWER SWITCH
3D3V_CR_S0
3D3V_S0
OUT
IN
GND
NC#3 ON/OFF#
<Variant Name>
Wistron Corporation
MC_PWR_CTRL 24
AAT4250IGV-T1-GP
CardR
2
DY
74.04250.A3F

Title
C789
SC1U10V3ZY-6GP
CardR
MINI CARD / 1394

Size
A3
Document Number

A
C787
SCD1U16V2ZY-2GP
U75
1
2
3
Rev
LWG2
SA
Sheet
E
26
of
52
Cardbus I/F
D
CBB_A10
CBB_CE2#
CBB_OE#
CBB_VS1#
CBB_A11
CBB_IORD#
CBB_A9
PCMCIA
PCMCIA
C466
SCD1U16V2ZY-2GP
SC1KP16V2KX-GP
2
1
SC4D7U10V5ZY-3GP
C468
C464
CBB_IOWR#
C
PCMCIA
CBB_A8
CBB_A17
CBB_A13
CBB_A18
CBB_A14
CBB_A19
CBB_WE#
CBB_A20
CBB_RDY
CBB_A21
SC4D7U10V5ZY-3GP
CBB_A16
CBB_A22
CBB_A15
CBB_A23
CBB_A12
CBB_A24
CBB_A7
CBB_A25
CBB_A6
C465
PCMCIA
C467
SCD1U16V2ZY-2GP
VPP_ASKT_S0
PCMCIA
CBB_VS2#
CBB_A16
CBB_A5
CBB_RESET
CBB_A4
CBB_WAIT#
CBB_A3
CBB_INPACK#
CBB_A2
CBB_REG#
CBB_A1
Place close to pin 19.
CBB_BVD2#
C469
DUMMY-C2
CBB_A0
CBB_BVD1#
CBB_D0
CBB_D8
CBB_D1
CBB_D9
CBB_D2
CBB_D10
CBB_WP
CBB_CD2#
Clock AC termination
33MHz clock for 32-bit
Cardbus card I/F
25
25
25
25
25
25
C512
SC4D7U10V5ZY-3GP
CB_DATA
CB_CLOCK
CB_LATCH
PCIRST1#
2
R384 10KR2J-3-GP
PCMCIA
C494
DY
1
3
4
5
12
21
DATA
CLOCK
LATCH
RESET#
SHDN#
AVCC
AVCC
AVPP
9
10
C510
1
SCD1U16V2ZY-2GP
13
3.3V
C493
PCMCIA
TPAD28
TP56
TP57
TPAD28
1
2
OC#
15
5V
5V
NC#24
NC#23
NC#22
NC#19
NC#18
NC#17
NC#16
NC#14
NC#6
24
23
22
19
18
17
16
14
6
7
20
12V
12V
11
25
GND
GND
PCMCIA
5V_S0
PCMCIA
PC1
VCC_ASKT_S0
U55
25
25
25
16,25,51
5V_S0
3D3V_S0
CBB_D15
VCC_ASKT_S0
25
25
SC1U10V3ZY-6GP
2
CBB_CE1#
CBB_CE1# 24
CBB_CE2# 24
CBB_BVD1#
CBB_BVD2#
CBB_CD1#
CBB_CD2#
CBB_VS1#
CBB_VS2#
Power switch
25
25
CBB_CD1#
CBB_D4
CBB_D11
CBB_D5
CBB_D12
CBB_D6
CBB_D13
CBB_D7
CBB_D14
35
2
36
3
37
4
38
5
39
6
40
7
41
8
42
9
43
10
44
11
45
12
46
13
47
14
48
15
49
16
50
17
51
18
52
19
53
20
54
21
55
22
56
23
57
24
58
25
59
26
60
27
61
28
62
29
63
30
64
31
65
32
66
33
67
34
68
CBB_D3
VPP_ASKT_S0
PCMCIA
CBB_IORD# 24
CBB_IOWR# 24
CBB_OE# 24
CBB_WE# 25
CBB_REG# 24
CBB_RDY
CBB_WP
CBB_RESET 25
CBB_WAIT#
CBB_INPACK#
C511
SCD1U16V2ZY-2GP
R404
100KR2J-1-GP
PCMCIA
69
24,25
24,25
CBB_D[0..15]
CBB_A[0..25]
PCMCIA1
SCD1U16V2ZY-2GP
2
NP1
PCMCIA Socket
TPS2220APWPRG-GP
74.02220.A7G
CARDBUS-SKT43-GP
21.H0057.011
NP2
70
CARDBUS68P-15-GP
62.10024.671
<Variant Name>
DY
C492
SCD01U16V2KX-3GP
Wistron Corporation
Title
Size
A3
PCMCIA
Document Number

5
Rev
LWG2
SA
Sheet
1
27
of
52
ACZ_SPKR
C478
ACZ_SPKR1
2
SCD47U10V3ZY-GP
1 R370
2
47KR2J-2-GP
C499
1
AUDIO_BEEP
2AUDIP_PC_BEEP
C476
KBC_BEEP
KBC_BEEP1
2
SCD47U10V3ZY-GP
1 R369
2
47KR2J-2-GP
1
R686
1KR2J-1-GP
C805
SC100P50V3JN-2GP
C803
30
SC1U10V3KX-3GP
C804
16
"VAUX" Pull high to enable standby mode
C497
SCD1U10V2KX-4GP
1 R371
2
47KR2J-2-GP
1
PCI_SPKR1
2
SCD47U10V3ZY-GP
SCD1U10V2KX-4GP
2
1
C477
SCD1U10V2KX-4GP
2
1
PCI_SPKR
5VA_S0
3D3V_S0
25
AC97_BTCLK
ACZ_RST_ALC# 15
ACZ_SYNC 15,21
AC97_BTCLK 15
2
1
R695
10KR2J-3-GP
1
R808
1
R809
2
2
20KR2F-L-GP
5K1R2F-2-GP
MICIN_JD#
29
LINEOUT_JD# 29
SENSE_B
SENSE_A
34
13
44
43
LFE-OUT
CEN-OUT
DVDD1
DVDD2
AVDD1
AVDD2
PCBEEP
RESET#
SYNC
BIT-CLK
VAUX
1
9
25
38
12
11
10
6
33
SENSE_A
U77
C817
SCD1U10V2KX-4GP
LINE1-L
LINE1-R
LINE2-L
LINE2-R
29
31
LINE1-VREFO
LINE2-VREFO
21
22
16
17
MIC1-L
MIC1-R
MIC2-L
MIC2-R
32
28
30
MIC1-VREFO-R
MIC1-VREFO-L
MIC2-VREFO
43/44
CEN/LEFT
45
46
SURR-OUT-L
SURR-OUT-R
39
41
FRONT-OUT-L
FRONT-OUT-R
35
36
AUD_LOL 29
AUD_LOR 29
H_LOL 29
H_LOR 29
71.00883.A0G
10KR2J-3-GP
5VA_S0
*Layout*
20 mil
SURR-VREFO-L/R
C475
45/46
SIDESURR
SIDESURR-L is MIC2-VREFO-R, SIDESURR-R is LINE2-VREFO-R
23/24
LINE1
Jack 2
Line input, line output
21/22
MIC1
Jack 3
Mic input, line output
14/15
LINE2
16/17
MIC2
Int. Mic
Mic input
SC1U10V3KX-3GP
SHDN# SET
GND
IN
OUT
G923-330T1UF-GP
R368
28K7R3F-GP
C473
SC22P50V2JN-4GP
5VA_SETPIN
U53
R389 2
10KR2F-2-GP
<Variant Name>
C796
74.00923.A3F
SC1U10V3KX-3GP
Wistron Corporation
C474
SC2D2U6D3V3MX-1-GP
Title
Size
A3
Azalia codec ALC883

Document Number

A
4
1
SIDESURR-OUT-L
SIDESURR-OUT-R
MUTEIN 29
2
20KR2F-L-GP
SURR
5V_S0
AMP output, line input
39/41
48
47
ACZ_SDATAOUT 15,21
ACZ_SDATAIN0 15
AC97_DATIN
1 R391
2
39R2J-L-GP
CD-L
CD-R
CD-GND
1
R813
Re-tasking
AMP,Jack1
Location
FRONT
SPDIFO
SPDIFI/EAPD
POWER GENERATE
Symbol
35/36
5
8
18
20
19
GPIO0
GPIO1
2
3
40
37
27
1
2
DY
SC10U10V5ZY-1GP
SCD47U50V5ZY
1
R812
C821
Configuation:
(3 External Jacks, 1 internal Mic, 1 stereo output Speaker Amp.
Pin
SDATA-OUT
SDATA-IN
C816
1) When GPIO0 is assered, AMP should be muted.

2) SPDIFO should be turned off when not used.
VREF
AVSS1
AVSS2
DVSS1
DVSS2
26
42
4
7
ALC883-1-GP
JDREF
PIN37_VREFO
ALC 883
SC4D7U10V5ZY-3GP
1
C884
SC4D7U10V5ZY-3GP
MIC1_L
1
2 C806
MIC1_R
1
2
SC1U10V3ZY-6GP 1
INT_MICP_L
2C831
C883 1
SC1U10V3ZY-6GP
INT_MICP_R
2
C882
SC1U10V3ZY-6GP
MIC1V_R
1
2
R8101
MIC1V_L
2 2K2R2J-2-GP
R6961
2K2R2J-2-GP MIC2_V_INT
2
R811
2K2R2J-2-GP
C885
C814
SC1U10V3ZY-6GP
MIC_IN_L
MIC_IN_R
INT_MICP
SC4D7U10V5ZY-3GP
29
29
31
23
24
14
15
Rev
LWG2
SA
Sheet
E
28
of
52
AUDIO OP AMPLIFIER
5V_S0
I/P signal level

need +5V level
5V_OP_S0
R814
1
2
0R0603-PAD
1
13
13
15
INL
INR
5
ERC4
4
1
2
3
4
SRC100P50V-2-GP
SPKR_L+1
1
R707
R706
1KR2J-1-GP
MH2
MH1
4
5
3
6
2
1
R703 2
HP_OUT_R_1
22R2J-2-GP
HP_OUT_L_1
2
22R2J-2-GP
C826
R702
1KR2J-1-GP
C823
EC573
SC1KP16V2KX-GP
EC572
SPKR_R+1
LOUT1
LINEOUT_JD#
<Variant Name>
PHONE-JK195
22.10133.931
Wistron Corporation
Title
Audio AMP G1421B / Jack
Size
A3
Document Number

A
SGND
PGND
GND
PHONE-JK191
22.10133.901
SC1KP16V2KX-GP
SC100P50V3JN-2GP
R836
C903
28
Line-Out
MIC_L
10R3J-3-GP
SC100P50V3JN-2GP
MIC_R
C820
22KR2J-GP
22KR2J-GP
R835
MIC1
MH2
MH1
4
5
3
6
2
1
10R3J-3-GP
2nd source: 20.F0760.004
MICIN_JD#
MIC_IN_L
28
1
R827
1
R697
28
MIC_IN_R
2
3
4
SPKR1
ACES-CON4-1-GP
20.D0197.104
MIC-In
28
SPKR_RSPKR_L+
SPKR_L-
SC2D2U16V5ZY-2GP
C902
SC22P50V2JN-4GP
C901
SPKR_R+
SC680P50V2KX-2GP
2
1
1
2
SC1U10V3ZY-6GP
C900
8
7
6
5
SC680P50V2KX-2GP
2
1
OUT
G923-330T1UF-1GP
IN
1
2
R826 0R3-0-U-GP
GND
17
2
21
SVSS
DY
R825
2
1
SC1U10V3ZY-6GP
SHDN# SET
MAX4411ETP-1-GP
3D3V_S0_AU
DY
C899
2
0R2J-2-GP
SC1U10V3ZY-6GP
4
6
8
12
16
20
C898
R848
R847
LINE_R1_2
10KR2J-3-GP
PVSS
LINE_L1_2
10KR2J-3-GP
Internal SPKR
3D3V_S0
OUTL
OUTR
NC
NC
NC
NC
NC
NC
5V_S0
U87
30 AMP_SHUTDOWN
9
11
14
18
SHDNR#
SHDNL#
10
19
SVDD
PVDD
C1P
C1N
1
R824
10KR2J-3-GP
1
3
C897
SC47P50V2JN-3GP
C896
SC47P50V2JN-3GP
2
1
H_LOR
H_LOL
28
0R2J-2-GP
28
AMP_C1P
2
SC1U10V3KX-3GP
1KR2J-1-GP
G1432_MUTE
DY
C892
AMP_C1N
1
C893
SC1U10V3ZY-6GP
C895
1
2 LINE_L1 1
R845
1
2 LINE_R1 1
R846
C894
SC1U10V3ZY-6GP
G1432Q5U-GP
C891
1DY
11
2
16
1KR2J-1-GP
C890
SC1U10V3ZY-6GP
U86
R823
MUTEIN
2100KR2J-1-GP
1 R818
SPKR_L+1
SPKR_R+1
AUD_LOR 28
MUTE
RBYPBASS
NC#6
NC#8
NC#23
SC1U10V3ZY-6GP
C888
SOUND_R2 2
1
12KR2J-L-GP
R822
SOUND_R_OP1
2
1
10KR2J-3-GP
LBYPASS
SOUND_R_OP1 1
R821
SPKR_R+
SPKR_R-
SC2D2U16V5ZY-2GP
IN1#/IN2
RIN1
RIN2
ROUT+
ROUT-
18
17
19
12
SC2D2U16V5ZY-2GP
6
8
23
LIN1
LIN2
LOUT+
LOUT-
28
D43
CH3906PT-GP
R817 1
B
100KR2J-1-GP
C889
SC1U10V3ZY-6GP
2 1KR2J-1-GP
3D3V_S0_AU
1
2
24
7
GND/HS
GND/HS
GND/HS
GND/HS
DY
SOUND_L_OP1
12KR2J-L-GP
SPKR_L+
SPKR_L-
9
10
21
22
SOUND_L2 1
R819
SOUND_L_OP1
1 R820
2
10KR2J-3-GP
SHUTDOWN
VOL
LVDD
RVDD
C887
SC1U10V3ZY-6GP
1
2
AUD_LOL
R816 1
3D3V_S0_AU
SHDNL_R
U85
28
R815
10KR2J-3-GP
TP109
TPAD28
20
4
15
SC10U10V5ZY-1GP
DY
SCD1U16V2ZY-2GP
AMP_SHUTDOWN 30
C886
GND
GND
C527
14
25
C528
SC10U10V5ZY-1GP
C503
SCD1U16V2ZY-2GP
Rev
LWG2
SA
Sheet
E
29
of
52
For S/W Debug

Pin No.
R472
100KR2J-1-GP
DY
1 R3
2
0R2J-2-GP
39 CHG_4D35V#
21 USB_EN1#_KBC
KBC_BB_EN#
21 USB_EN2#_KBC
21 USB_EN3#_KBC
15,32 LPC_LAD[0..3]
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
15,32 LPC_LFRAME#
PLT_RST1#
7,16,20,22,26,32,42 PLT_RST1#
PCLK_KBC
16,25 INT_SERIRQ
1 2
PCLK_KBC_RC
13 BRIGHTNESS
C707
SC10P50V2JN-4GP
26
RF_ON/OFF#
13
45
DY
29 AMP_SHUTDOWN
28
KBC_BEEP
R626
DY
100R2J-2-GP
BLON_OUT
BLON_IN
R637
2M2R3-GP
DY
KROW1
KROW2
KROW3
KROW4
KROW5
KROW6
KROW7
KROW8
KBC_BEEP
KBC_SDA
RF_ON/OFF#
BRIGHTNESS
BLON_OUT
BLON_IN
KBC_BB_EN#
KBC_3D3V_AUX
Q45
CH3906PT-GP
PURE_HW_SHUTDOWN#
19,33
C660
SC10U10V5ZY-1GP
SRN10KJ-6-GP
121
122
123
124
125
126
127
128
P30/LAD0
P31/LAD1
P32/LAD2
P33/LAD3
P34/LFRAME#
P35/LRESET#
P36/LCLK
P37/SERIRQ
136
137
138
2
3
4
5
6
P40/TMCI0
P41/TMO0
P42/TMRI0/SDA1
P43/TMCI1
P44/TMO1
P45/TMRI1
P46
P47
140
141
143
144
RE144B
P60/FTCI/KIN0#/TMIX
P61/FTOA/KIN1#
P62/FTIA/KIN2#/TMIY
P63/FTIB/KIN3#
P64/FTIC/KIN4#
P65/FTID/KIN5#
P66/FTOB/KIN6#/IRQ6#
P67/TMOX/KIN7#/IRQ7#
P70
P71
P72
P73
P74
P75
P76
P77
Place near KBC

(Near H11,Top side).
71.00144.B0G
1
2
1
120
119
118
117
116
115
114
113
MD0
MD1
X1
X2
XTAL
EXTAL
10
9
8
142
12
PB0/WUE0#/LSMI
PB1/WUE1#/LSCI
PB2/WUE2#
PB3/WUE3#
PB4/WUE4#
PB5/WUE5#
PB6/WUE6#
PB7/WUE7#
41
40
39
38
37
35
34
33
-2 modify
LCDGPIO 13
NOVO 31
TCLK
31
TDATA
31
5V_S0
RN45
1
2
3
4
8
7
6
EC25
5
SCD1U16V2ZY-2GP
SRN10KJ-6-GP
P20
P21
P22
P23
P24
P25
P26
P27
C380
SC22P50V2JN-4GP
R270 1
X3
1
C358
XTAL-10MHZ-3GP
82.30054.041
SC22P50V2JN-4GP
DY
2
103
102
101
100
99
98
97
96
78
79
80
81
82
83
84
85
1
2
3
4
ECSCI#_KBC
EC_PWRBTN#
PCIE_WAKE#
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
94
93
92
91
90
89
88
87
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
66
65
64
63
62
61
60
59
KCOL9
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
32
31
30
29
28
27
26
25
EC_PWRBTN# 31
PM_SLP_S5# 16,38,40
BATA_IN# 39,41
PCIE_WAKE# 16,22
C694
AD_OFF
RN48
8
7
6
5
050510:For
Battery switch
fail issue
SC100P50V2JN-3GP
ECSCI#_KBC
1
D37
3 BAT54PT-GP
ECSCI# 16
2
1
D38
ECSWI#_KBC 3 BAT54PT-GP
ECSWI# 16
KBC_MATRIX0
KBC_MATRIX1
KBC_MATRIX0 31
KBC_MATRIX1 31
NAPA_U_V
KBC_3D3V_AUX
RN47
BATA_SCL
BATA_SDA
1
2
4
3
SRN10KJ-5-GP
KCOL[1..16] 31
KROW[1..8] 31
VSS
VSS
VSS
VSS
VSS
VSS
S5_EN
R586
10KR2J-3-GP
CardR
100R2J-2-GP 2
PA0/KIN8#
PA1/KIN9#
PA2/KIN10#/PS2AC
PA3/KIN11#/PS2AD
PA4/KIN12#/PS2BC
PA5/KIN13#/PS2BD
PA6/KIN14#/PS2CC
PA7/KIN15#/PS2CD
NMI
S5_EN
41 AD_OFF
P10/PW0
P11/PW1
P12/PW2
P13/PW3
P14/PW4
P15/PW5
P16/PW6
P17/PW7
7
42
67
95
111
139
33
SB_PWRBTN#
112
110
109
108
107
106
105
104
11
3D3V_AUX_S5
16 SB_PWRBTN#
31 WIRELESS_BTN#
CHG_I_PWM
CHG_V_PWM
3D3V_S5_SENSE
P90/IRQ2#
P91/IRQ1#
P92/IRQ0#
P93
P94
P95
P96/EXCL
P97/SDA0
1
D42
BAT54PT-GP 3 SB_RSMRST#_KBC
1 R618
2
0R0402-PAD
24
23
22
21
20
19
18
17
39 CHG_I_PWM
39 CHG_V_PWM
16 RSMRST#_TO_KBC
RES#
RESO#
STBY#
VCC
VCC
VCC
VCC
2
R802
2K2R2J-2-GP
58
57
56
55
54
53
52
51
U73
PG0
PG1
PG2
PG3
PG4/EXSDAA
PG5/EXSCLA
PG6/EXSDAB
PG7/EXSCLB
C324
C312
SCD1U16V2ZY-2GP SC10U10V5ZY-1GP
3D3V_S5
H8_RESET#
MODE0
KBC_NMI
H8_STBY#
MODE1
KBC_XTAL
KBC_EXTAL
C723
SCD1U16V2ZY-2GP
C732
SCD1U16V2ZY-2GP
C357
SCD01U16V2KX-3GP
DY
R268
10KR2J-3-GP
PWRLED 13,31
CHRGER_LED 13
DC_BATFULL 13
1
C724
SC4D7U10V5ZY-3GP
KBC_3D3V_AUX
R261 1
2
0R0805-PAD
KBC_3D3V_AUX
-1 Modify
KBC_5V_AUX
R584 1
2
0R0805-PAD
P80/PME#
P81/GA20
P82/CLKRUN#
P83/LPCPD#
P84/IRQ3#/TXD1
P85/IRQ4#/RXD1
P86/IRQ5#/SCK1/SCL1
5V_AUX_S5
16 SB_RSMRST#
NAPA_U_V
NUM_LED 13
CAP_LED 13
10
3D3V_AUX_S5
10KR2J-3-GP
129
130
131
132
133
134
135
GND
1394/CardReader Detect Pin

H:non 1394/CardReader
L:has 1394/CardReader
non CardR R267
50
49
48
47
46
45
44
43
PM_SLP_S3#
H8_RXD1
PF0/TMIA
PF1/TMIB
PF2/TMOA
PF3/TMOB
PF4/EXTMIX
PF5/EXTMIY
PF6/EXTMOX
PF7/TMOY
H8_TXD1
P50/EXTXD1
P51/EXRXD1
P52/EXSCK1/SCL0
LID_CLOSE#
16
15
14
KBC_AC_IN#
36
13
MODE0
3D3V_AUX_S5
PLANARID0 31
PLANARID1 31
PLANARID2 31
BLUETOOTH_EN 21
VCCB
VCL
H8_RESET#
68
69
70
71
72
73
74
75
TP101
TP102
TP103
TP104
TP75
TP106
TP74
TP108
MODE1
86
77
76
1
1 3D3V_AUX_KBC
Pin No.
KBC_3D3V_AUX
KBC_AC_IN#
RE144B-GP
1 R585
10KR2J-3-GP
RN46
5V_S0
KBC_MATRIX0
KBC_MATRIX1
3D3V_S0
1
2
4
3
SRN10KJ-5-GP
KBC_3D3V_AUX
3D3V_S0
KBC_NMI
RN96
SRN10KJ-5-GP
RN94
SRN10KJ-5-GP
41
Q39
S
SMBC_KBC 19
BLUETOOTH_LED 13
WLAN_TEST_LED 13
H_RCIN# 15
PM_SLP_S3# 16,18,33,38,40,49
LID_CLOSE# 31
ECSWI#_KBC
LID_CLOSE#
H8_TXD1
H8_RXD1
KBC_SCL
1
KBC_AC_IN#
2N7002-7F-GP
KBC_SDA
Q44
S

AC_IN# 39
Title
KBC_RE144B
BAT54PT-GP
Size
A3
Document Number
Rev
SA
LWG2

B
10KR2J-3-GP
Wistron Corporation
3
2N7002-7F-GP
A
-1 Modify
D39
2
SMBD_KBC 19
1 R599
<Variant Name>
BATA_SCL
15
K_A20GATE
16,25,51 PM_CLKRUN#
16 PM_SUS_STAT#
2
1
1
2
KBC_SCL
K_A20GATE
3
4
4
3
BATA_SDA 41
Sheet
E
30
of
52
Internal KeyBoard Connector

30 KROW[1..8]
COVER SWITCH
30 KCOL[1..16]
3D3V_AUX_S5
SW1
PSW_CLR#
30
30
KBC_MATRIX0
KBC_MATRIX1
PSW_CLR#
1
2
3
4
16
R460
100KR2J-1-GP
SW-DIP-4-2-U2-GP
R459
LID_CLOSE# 30
100R2F-L1-GP-U
PUSH-SW81-GP
C547
SC1KP16V2KX-GP
Keyboard matrix ( from vendor )
62.40014.141
US
Eur
Jap
Ohter
2nd source: 62.40010.151

1
MATRIXID1#
LAUNCH BD CONN
PSW_CLR#
Low Active
1 - 5 ON
NC
2 - 6 ON
KBC_MATRIX1
3 - 7 ON
KBC_MATRIX2
4 - 8 ON
KCOL10
KROW6
KROW7
KCOL11
KCOL12
KROW8
KCOL13
KCOL14
KCOL15
KCOL16
25
K/B
1
C906
4
3
1
2
C905
RN44
30
30
TDATA
TCLK
1
2
SRN33J-5-GP-U
4
3
EC327
RN100
SRN10KJ-5-GP
SCD1U10V2KX-4GP
1
2
EC35
5V_S0
WIRELESS_BTN# 30
NOVO 30
EC_PWRBTN# 30
C904
EC16
TOUCH PAD
5V_S0
SCD1U16V2ZY-2GP
SCD1U10V2KX-4GP
2
2 470R2J-2-GP
2 470R2J-2-GP
470R2J-2-GP
SCD1U16V2ZY-2GP
TPAD1
14
12
11
10
9
8
7
6
5
4
3
2
TP_DATA
TP_CLK
TP_LEFT
TP_RIGHT
CN2
1
13
5
1
6
3D3V_AUX_S5
ACES-CON12-GP
20.K0174.012
ERC3
SRC100P50V-2-GP
77.61012.02L
12
T/P
1
2
3
4
ACES-CON4-3-GP
8
7
6
5
TP_LEFT
TP_RIGHT
2
3
4
DY
R264
100KR2J-1-GP
DY
R263
100KR2J-1-GP
T/P
R623
100KR2J-1-GP
<Variant Name>
Wistron Corporation
2
R624
100KR2J-1-GP
R622
100KR2J-1-GP

Title
KEYBOARD/TOUCHPAD
PLANARID2
PLANARID1
PLANARID0
PLANARID2
PLANARID1
PLANARID0
30
30
30
Planar
ID(2,1,0)
SA: 0,0,0
SB: 0,0,1
SC,-1/-1m: 0,1,0
-2: 0,1,1
DY
R265
100KR2J-1-GP
20.K0220.004
KROW5
INT_MICP 28
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
2nd source: 20.K0198.025
PWRLED 13,30
1
R831 1
R832 1
R120
KROW4
20.K0197.025
12
WIRELESS_BTN#_CN
NOVO_CN
PWRBTN#
KCOL1
KCOL2
KCOL3
ACES-CON25-GP
SCD1U16V2ZY-2GP
ACES-CON12-GP
20.K0174.012
Launch
LAUNCH1
14
12
11
10
9
8
7
6
5
4
3
2
1
13
10KR2J-3-GP
R830
10KR2J-3-GP
R828 R829
10KR2J-3-GP
5V_S0
3D3V_S0
3D3V_AUX_S5
MATRIXID0#
KROW1
KROW2
KROW3
SCD1U10V2KX-4GP
26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
27
NC#26
C01
C02
C03
R01
R02
R03
C04
R04
R05
R06
R07
R08
R09
C05
R10
C06
C07
R11
R12
C08
R13
R14
R15
R16
NC#25
NC#27
CVR1
KB1
ON
5
6
7
8
Size
A3
Document Number
Rev
LWG2
SA
Sheet
31
of
52
GOLDEN FINGER FOR DEBUG BOARD
5V_S0
5V_S0
U46
7,16,20,22,26,30,42
PLT_RST1#
LPC_LFRAME#
PLT_RST1#
15,30 LPC_LFRAME#
PCLK_FWH
3 PCLK_FWH
FWH_INIT#
15 FWH_INIT#
15,30 LPC_LAD[0..3]
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0
EXT_FWH#
16 EXT_FWH#
3D3V_S0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
PLT_RST1#
LPC_LFRAME#
PCLK_FWH
FWH_INIT#
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0
EXT_FWH#
3D3V_S0
-1 Modify
FOX-GF30
ZZ.GF030.XXX
SPI FLASH ROM

8M Bits
3D3V_S0
3
Boot Device must have ID[3:0] = 0000

Has internal pull-down resistors
All may be left floated
FPET7 Elec. P3-46
R403
10KR2J-3-GP
16
SPI_WP#
16
16
SPI_CS#
SPI_MISO
U54
SPI_CS#
SPI_MISO
SPI_WP#
1
2
3
4
CE#
SO
WP#
VSS
SPI
VDD
HOLD#
SCK
SI
3D3V_S5
8
7
6
5
SPI_HOLD#
SPI_CLK
SPI_MOSI
1 R402
2
10KR2J-3-GP
3D3V_S5
SPI_CLK 16
SPI_MOSI 16
SST25LF080A-1GP
72.25080.E01
SOIC 200 Socket P/N:

Wieson: 62.10076.001
SPI ROM:
SST25LF080A: 72.25080.E01
SST25VF080B : 72.25080.G01
ST M25P80: 72.25P80.001
TOP VIEW
(B1)
(B2)
....
A15
A14
....
A2
(B14)
A1
(B15)
(BOTTOM VIEW)
<Variant Name>
Wistron Corporation
Title
BIOS : SPI
Size
A3
Document Number
Rev
LWG2

A
SA
Sheet
E
32
of
52
1D05V_S0
-1M Modify
4.7K / 0.22U ?
Aux Power
R719
56R2J-4-GP
3D3V_AUX_S5
PM_THRMTRIP-I# 4
R525
100KR2J-1-GP
4,15
DY
DY
1
D17
BAT54PT-GP 3
C33
SC1U50V5ZY-1-GP
PURE_HW_SHUTDOWN#
19,30
2
S5_EN_21 R70
2
10KR2J-3-GP
74.02951.F31
S5_EN
*Layout*
15 mil
LP2951CDR2G-GP
8
7
6
2
R45
0R0402-PAD
OUTPUT
INPUT
SENSE
FEEDBACK
SHUTDOWN
VO TAP
GND
ERROR# OUTPUT
AUX_SD
DY
1
2
3
4
C623
SC1U10V2KX-GP
Q8
CHT2222APT-GP
U4
C36
C35
SCD1U16V2ZY-2GP
SC10U10V6ZY-U
H_PWRGD
SHUTDOWN_S5 1 R496
2S5_EN_3
1KR2J-1-GP
DCBATOUT
2 C37
SCD1U16V2ZY-2GP
CHT2222APT-GP
Q51
30
DY
100mA
5V_AUX_S5
1 R720
2
10KR2J-3-GP
C71
SCD1U10V2KX-4GP
T(soft)=1.736ms
TPS51120_EN1_5 37
TPS51120_EN1_5
SET
OUT
G913CF-GP
R23
22KR2J-GP
BC3
SC1U10V3ZY-6GP
R358
1MR2J-1-GP
R2
Vout = 1.25*(1+ R1/R2)
T(soft)=1.736ms
TPS51120_EN2_3D3
TPS51120_EN2_3D3 37
BC1
SC1U10V3ZY-6GP
74.00913.A3F
1 2
2
SHDN#
GND
IN
1
2
3
SHUTDOWN_S5
R24
36K5R3F-2-GP
BC2
R1
SC22P50V3JN-GP
I max = 120 mA
U5
5V_AUX_S5
C472
SC4700P50V2KX-1GP
Q17
2N7002-7F-GP
3D3V_AUX_S5
Q16
2N7002-7F-GP
C457
SC4700P50V2KX-1GP
Run Power
1
Q18
TP0610K-T1-GP
Q52
3 OUT PM_SLP_S3#_Z12V G
R2
IN
3D3V_S5
1
2
3
4
CHDTC124EU-1GP
84.00124.F1K
U52
S
S
S
G
D
D
D
D
8
7
6
5
2N7002-7F-GP
R1
D29
MMGZ5242BPT-GP 3D3V_S0
PM_SLP_S3#_Z12V
DY
Q56
<Variant Name>
2N7002-7F-GP
AO4422-1-GP
1D8V_S0
Wistron Corporation
1D8V_S3
PM_SLP_S3#
R359
200KR3J-GP
GND 2
16,18,30,38,40,49
DY
R849
100R5J-3-GP
Q19
R366
100KR2J-1-GP
SCD1U25V3KX-GP
2
C272
R742
47KR2J-2-GP
1
330KR2F-L-GP
3D3V_S0
8
7
6
5
AO4422-1-GP
84.04422.B37
84.00610.C31
2
R367
D
D
D
D
RUN_PWR_CTLR
SCD1U25V3KX-GP
1
2
3
4
R360
Z_12V
2
10KR2J-3-GP
U51
S
S
S
G
DY C323
DCBATOUT
5V_S5
5V_S0
1
2
3
4
U27
S
S
S
G
D
D
D
D
IRF7805ZPBF-GP
84.07805.A37
8
7
6
5

Title
RUN and AUX POWER

Size
A3
Document Number
Rev
LWG2
SA
Sheet
33
of
52
TPS51124
1D8V/1D05V
CPU_CORE
Intersil ISL6262
Input Power
5V_S5
4
VID Setting
H_VID0
PGOOD(OD / 3.3V)
VID1(I / 1.05V)
H_VID2
VID2(I / 1.05V)
H_VID3
CLK_EN#(O)
6262_PWRGOOD
1D8V (O)
DCBATOUT_TPS51124
VIN
CLK_EN#
1D05V(O)
VID3(I / 1.05V)
H_VID4
VID5(I / 1.05V)
H_VID6
TPS51124_EN1
Output Power
VID6(I / 1.05V)
VCC_CORE_PWR(O)
Input Signal
PSI#
PM_DPRSLPVR
H_DPRSTP#
1D05V_S0 (7A)
EN1
TPS51124_EN2
VCC_CORE_S0(Imax=48A)
PSI# (I / 3.3V)
CPUCORE_ON
1D8V_S0 (7A)
Input Signal
VID4(I / 1.05V)
H_VID5
Output Power
VCC
Output Signal
VID0(I / 1.05V)
H_VID1
EN2
Output Signal
CPUCORE_ON
PGD_IN (I / 3.3V)
DPRSLPVR (I / 3.3V)
PGOOD1
CPUCORE_ON
PGOOD2
DPRSTP# (I / 3.3V)
Voltage Sense
VCC_SENSE
VSEN(I / Vcore)
VSS_SENSE
Charger Max8725
RTN(I / Vcore)
Input Signal
Input Power
DCBATOUT_6262
CHGON#/OFF
VCC(I)
BT_TH
5V_S0
VCC(I)
3D3V_S0
Output Signal
ICTL
BATT
PKPRES
ACOK
Input Power
VCC(I)
AD+
BT+SENSE
AC_IN
Output Power
ACIN
BT+
VOUT (O)
DCBATOUT
VOUT (O)
TPS51120
5V/3D3V
Input Signal
TPS51120_EN1_5
TPS51120_EN2_3D3
Output Signal
PGOOD1(OD / 5V)
CPUCORE_ON
PGOOD2(OD / 5V)
CPUCORE_ON
EN1
Output Power
EN2
5V(O)
Input Power
3D3V(O)
Adapter
5V_DC_S5 (6A)
3D3V_DC_S5 (5A)
AD_OFF
DCBATOUT_TPS51120
Input Signal
(I)
Input Power
VIN
AD_JK
5V_AUX_S5
VCC(I)
Output Signal
AD_IN
(O)
<Variant Name>
Output Power
AD+
VCC(O)
Wistron Corporation
VCC(I)
Title
Power Block Diagram

Size
A3
Document Number

A
Rev
SA
LWG2
Sheet
E
34
of
52
G81
DCBATOUT_6262
5V_S0
SA change to close gap
R777
0R2J-2-GP
R188
10R3J-3-GP
R222
10R2J-2-GP
R193
1K91R3F-GP
2
0R0402-PAD
VGATE_PWRGD 7,16,45
DCBATOUT
35
36 6262_BOOT1
1 R226
2
0R0603-PAD
H_VID5
H_VID6
37,38,40,45 CPUCORE_ON
16 PM_DPRSLPVR
4,15 H_DPRSLP#
3
CLK_EN#
2
2
2
2
2
2
2
R161
1
1
R160
2
PVCC
31
27
VID0
6262_VID1
38
VID1
UGATE2
6262_VID2
39
VID2
BOOT2
6262_VID3
40
VID3
6262_VID4
41
VID4
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
6262_VID5
42
VID5
6262_VID6
43
VID6
6262_CORE_ON
44
VR_ON
6262_DPRSLP
45
DPRSLPVR
6262_DPRSTP#
46
DPRSTP#
6262_CLKEN#
47
CLK_EN#
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
LGATE2
30
ISEN2
13
6262_FB212
1
R190
SC390P50V3JN-GP
6262_OCSET
VSUM
19
6262_VSUM
FB2
2
4K42R3F-GP
ISL6262CRZ-T-GPU
6262_VSUM 1
DY
R220
1R3F-GP
36
6262_ISENN2
36
OCP>=55A
1
2
R163 11K5R3F-GP
6262_AGND
C260
R219
11KR2F-L-GP
R185
NTC-10K-9-GP
-1
18 6262_VO
Place close to phase 1 chocke
1
DFB
17
DROOP
VSEN
C259
R182
2K61R3F-GP
U25
6262_DFB
C304
SCD22U10V2KX-1GP
1 R187
2K55R3F-GP
G75
Load Line
1
2
C261 SC180P-GP
6262_VO
2
<Variant Name>
GAP-CLOSE-PWR
6262_AGND
Wistron Corporation
6262_AGND

Title
CPU Vcore Power_1

Document Number

4
6262_ISENP2
R607 10KR3F-L-GP
R224
0R2J-2-GP
2
SC1KP50V3KX-GP
Size
A3
5
3K65R3F-GP
R610
36
6262_AGND
C265
SCD01U50V3KX-4GP
6262_VSEN
6262_DROOP
2
1
2
When test without cpu,

R183 & R184 change to 0 ohms
If VCC_SENSE and VSS_SENSE pins have pulled
resistors to VCC_CORE_S0
==> Remove R183/R184
R186
1KR2F-3-GP
6262_RTN
C263
SCD01U16V2KX-3GP
2
16
74.06262.073
C262
PH
VW
14
EC: N060535
1 R183
2
0R0402-PAD
5 VCC_SENSE
COMP
RTN
6262_VW 9
2
SC47P50V3JN-GP
1 R184
2
0R0402-PAD
5 VSS_SENSE
FB
15
PL
OCSET
C233
VDIFF
VO
1
C267
6262_AGND
6262_COMP10
Switching Frequency=300KHz
36
C308
SCD22U25V3ZY-GP
6262_PHASE2 36
6262_LGATE2
25
2 C232
SCD033U16V3KX-GP
SCD01U16V2KX-3GP
C231
11
6262_ISENN1
1R3F-GP
DY
6262_FB
2
1
61K9R2F-GP
36
29
2KR2-GP
1
R162
6262_ISENP1
36
C305
DY
R223
SCD22U10V3KX-2GP
NC
6262_VDIFF
1
2
C266 SC470P50V2KX-3GP
23 6262_ISEN2
R189
SCD22U10V3KX-2GP
C306
5V_S0
C309 SC4D7U6D3V3KX-GP
6262_UGATE2
2
26 6262_BOOT2 1 R225
0R0603-PAD
28
PGND2
R221 R608 10KR3F-L-GP

0R2J-2-GP
PHASE2
1K82R3F-GP
2
1K4R3F-1-GP
1 R778
2
0R3-0-U-GP1 R797
2
0R0603-PAD
1
2
GAP-CLOSE-PWR
R609
3K65R3F-GP
2
H_VID4
DY
SOFT
37
0R2J-2-GP
GAP-CLOSE-PWR
G23
2
H_VID3
1 2
H_VID[0..6]
5V_S5
6262_VID0
0R2J-2-GP
GAP-CLOSE-PWR
G24
2
H_VID2
5
24 6262_ISEN1
H_VID1
NTC
6262_VSUM 1
1
R227
1
R228
1
R231
1
R232
1
R229
1
R230
1
R197
1
R198
1
R196
1
R194
1
R195
36
ISEN1
6262_SOFT7
2
SCD015U25V3KX-GP
6262_LGATE1
33
RBIAS
VR_TT#
GAP-CLOSE-PWR
G25
2
DCBATOUT_6262
Place close to phase 1 chocke

If NTC=330Kohm, R10=8.66K
H_VID0
C268
1
32
PGND1
PGD_IN
470K /0402 size
6262_AGND
LGATE1
PSI#
6262_NTC
36
SCD047U50V3KX-GP
2
1
1 R611
NTC-470K-1-GP
6262_PHASE1
2 4K02R3F-GP
C269
1
2
SCD01U16V2KX-3GP
34
PHASE1
R612 1
6262_AGND
C310
SCD22U25V3ZY-GP
6262_RBIAS 4
4 CPU_PROCHOT#
36
6262_PGD_IN3
0R2J-2-GP
1
2
R191
147KR2F-GP
GAP-CLOSE-PWR
G26
2
6262_PSI#
0R2J-2-GP
GAP-CLOSE-PWR
G78
2
BOOT1
SCD22U10V3KX-2GP
6262_AGND
1
R199
1
R192
PSI#
CPUCORE_ON
GAP-CLOSE-PWR
G79
2
1
PGOOD
3V3
UGATE1
6262_UGATE1
6262_AGND
GND_T
GAP-CLOSE-PWR
G80
2
GND
49
VIN
VCC
21
2
1
R200
SC1U10V3KX-3GP
48
22
C307
C264
SCD01U25V2KX-3GP
20
2
1
6262_AGND
DY
PGOOD
Power good open-drain output.
Will be pulled up externally by
a 680. resistor to VCCP or 1.9k. to 3.3V.
5V_S5
3D3V_S0
Rev
SA
LWG2
Sheet
1
35
of
52
DCBATOUT_6262
1
2
C373
D
D
D
D
SC10U25V6KX-1GP
C322
SC10U25V6KX-1GP
C685
1
5
6
7
8
U30
SI7686DP-T1-GP
EC: N060382
SC10U25V6KX-1GP
EC321
SCD1U25V3ZY-1GP
S
S
S
G
4
3
2
1
Panasonic ETQP4LR36WFC
10*11.5*4mm
0.34uH / 24A
DCR=1.1mohm
2
1
S
S
S
G
6262_PHASE2
35
6262_LGATE2
1
2
DY
Panasonic ETQP4LR36WFC
10*11.5*4mm
0.34uH / 24A
DCR=1.1mohm
L27
2
IND-D36UH-9-GP
TC8
2
G83
GAP-CLOSE-PWR
4
3
2
1
4
3
2
1
G82
GAP-CLOSE-PWR
S
S
S
G
5
6
7
8
5
6
7
8
D
D
D
D
S
S
S
G
U35
FDS6676AS-GP
SE330U2VDM-6-GP
D
D
D
D
U32
FDS6676AS-GP
SE330U2VDM-6-GP
TC5
Id=46A
Qg=15~21nC, Rdson=6.9~8.6mohm
KEMET
330uF / 3V / V size
ESR=9mohm / Iripple=3.7A
35
35
C372
SCD1U25V3ZY-1GP
SC10U25V6KX-1GP
1
2
C717
4
3
2
1
C311
SC10U25V6KX-1GP
C718
SC10U25V6KX-1GP
1
2
5
6
7
8
D
D
D
D
6262_UGATE2
35
6262_ISENP1
DY
EC: N060382
35
6262_ISENN1
C684
SCD1U25V3ZY-1GP
4
3
2
1
4
3
2
1
DCBATOUT_6262
U33
SI7686DP-T1-GP
5
6
7
8
5
6
7
8
Id=30A
Qg=8~11nC, Rdson=14.4~18mohm
C
G77
GAP-CLOSE-PWR
TC7
SE330U2VDM-6-GP
S
S
S
G
G76
GAP-CLOSE-PWR
TC6
SE330U2VDM-6-GP
D
D
D
D
S
S
S
G
U29
FDS6676AS-GP
TC9
SE330U2VDM-6-GP
D
D
D
D
U28
FDS6676AS-GP
SE330U2VDM-6-GP
TC4
IND-D36UH-9-GP
6262_LGATE1
35
L23
6262_PHASE1
6262_UGATE1
35
35
Iomax=44A
OCP>=88A
VCC_CORE_S0
35
6262_ISENP2
35
6262_ISENN2
<Variant Name>
Wistron Corporation
Title
CPU Vcore Power_2

Size
A3
Document Number

5
Rev
SA
LWG2
Sheet
1
36
of
52
G48
1
2
51120_VREF2
2
0R0402-PAD
Iomax=11A
Qg=9.8nC,
Rdson=19.6~24mohm
COMP
N/A
N/A
TONSEL
380k/CH1
590k/CH2
290k/CH1
440k/CH2
220k/CH1
330k/CH2
D-Cap
MODE
180k/CH1
280k/CH2
ADJ.
EN1,EN2 Switcher OFF
not use
Swithchr ON
Switcher ON
EN3,EN5
not use
LDO ON
not use
C782
SC390P50V3JN-GP
R674
22KR2J-GP
DY
DY
1 2
N/A
VFB2
ADJ.
not use
VFB1
51120_COMP2
N/A
5V
Fixed Output
3.3V
Fixed Output
LDO OFF
C777
SC33P50V2JN-3GP
DY
51120_VFB2
GAP-CLOSE-PWR
G44
2
GAP-CLOSE-PWR
G45
2
GAP-CLOSE-PWR
G46
2
GAP-CLOSE-PWR
G47
2
3D3V_S5
GAP-CLOSE-PWR
NEC 220uF ,V size

ESR=25mohm
Iripple=2.2A
R661
13K3R2F-L1-GP
G104
51120_AGND
Vout=1V*(R1+R2)/R2
2
GAP-CLOSE-PWR
DY
C781
SC1KP50V3KX-GP
51120_AGND
For TPS51120,
Vout=5V
1. If you use
2. If you use
3. If you use
Vout=3.3V
1. If you use
2. If you use
3. If you use
a 6.8uH inductor, the minimum ESR is 70m ohm.

<Variant Name>
Wistron Corporation
Title
5V_UP_S5/3D3V_S5/5V_S5
Size
A3
VREG3 on
B
1
R662
TC12
30K9R3F-GP ST220U6D3VDM-15GP
DY
Document Number
51120_AGND
A
GAP-CLOSE-PWR
G43
2
DY
C785
SC1KP50V3KX-GP
51120_AGND
1
GAP-CLOSE-PWR
G42
2
DY
DY
DY
CURRENT
MODE
3D3V_PWR
3D3V Iomax=6A
OCP>12A
PWM
EC471
SCD1U25V3ZY-1GP
ENG
1
2
IND-3D3UH-43-GP
R675
22KR2J-GP
1 2
PWM
C786
SC390P50V3JN-GP
U48
AO4406-1-GP
V5FILT
C793
51120_TONSEL 1
R341
C795
L36
51120_DRVH2
51120_LL2
51120_DRVL2
SKIPSEL
2
1
Iomax=11A
Qg=9.8nC,
Rdson=20~25mohm
74.51120.073
AUTOSKIP
AUTOSKIP
/FAULTS
OFF
FLOAT
1
2
2
U47
AO4422-1-GP
51120_DRVH1
51120_DRVH2
27
14
3D3V_PWR
DRVH1
DRVH2
2
GAP-CLOSE-PWR
G41
2
DCBATOUT_51120
35,38,40,45
51120_COMP1
VREF2
25
16
CPUCORE_ON
DRVL1
DRVL2
51120_PGOOD1 1 R342
2
51120_PGOOD2 1
0R0402-PAD
2
R339
0R0402-PAD
51120_DRVL1
51120_DRVL2
30
11
51120_AGND
GND
GAP-CLOSE-PWR
G53
2
PGOOD1
PGOOD2
51120_LL2
51120_LL1
R340
0R0402-PAD
SC
COMP2
COMP1
15
26
OCP
51120_CS2
GAP-CLOSE-PWR
G39
2
GAP-CLOSE-PWR
R338
100KR2J-1-GP
LL2
LL1
S
S
S
G
15KR3F-GP
1
2
R353 20KR3F-GP
51120_AGND
51120_CS1
NEC 220uF ,V size

ESR=25mohm
Iripple=2.2A
G40
TC13
ST220U6D3VDM-15GP
51120_AGND
1 R355
GAP-CLOSE-PWR
G38
2
D
D
D
D
5V_S5
51120_V5FILT
1
CS1
CS2
23
18
24
17
5
33
TPS51120RHBR-GPU1
51120_AGND
GAP-CLOSE-PWR
G37
2
DY
S
S
S
G
SC1KP50V3KX-GP
C779
5V_PWR
R668
7K5R3F-GP
5
6
7
8
VREF2
51120_DRVL1
4
3
2
1
5V Iomax=6A
OCP>12A
5
6
7
8
51120_VREF2
GAP-CLOSE-PWR
G36
2
U45
SKIPSEL
TONSEL
VO1
VO2
4
3
2
1
1
2
7
2
20
22
V5FILT
VIN
28
13
1
8
DY
51120_VFB1
SC10U35V0ZY-GP
5V_PWR
3D3V_PWR
R667
30KR2F-GP
DY
SC10U35V0ZY-GP
VFB2
VFB1
C780
SC33P50V2JN-3GP
D
D
D
D
6
3
3D3V_S0
EN1
EN2
EN3
EN5
51120_SKIPSEL 32
31
29
12
10
9
VBST1
VBST2
VREG3
VREG5
19
21
C783
51120_VFB2
51120_VFB1
51120_V5FILT
GAP-CLOSE-PWR
G35
2
IND-3D3UH-43-GP
51120_COMP2 1R663
2
0R0603-PAD
51120_COMP1 1R666
2
0R0603-PAD
2
20R0402-PAD
0R0402-PAD
C455
SCD1U50V3ZY-GP
51120_VREG3
PGND1
PGND2
GND
GND
1
1 R664
R665
51120_V5FILT
2
51120_EN1
51120_EN2
1TPAD28
1TPAD28
1
2
1 R352 0R0402-PAD
2
R356 0R0402-PAD
TP52
TP53
33 TPS51120_EN1_5
33 TPS51120_EN2_3D3
SC10U10V5KX-2GP
SC10U10V5KX-2GP
51120_VBST1_11 R357
2 51120_VBST1
0R0603-PAD
SCD1U50V3ZY-GP
51120_VREG5
S
S
S
G
C456
51120_LL1 1
2
D
D
D
D
Iomax=11A
Qg=9.8nC,
Rdson=19.6~24mohm
EC470
SCD1U25V3ZY-1GP
GS 10*10*4 4D7uH
5V_PWR
DCR=25mohm, Isat=6A
U50
AO4406-1-GP
C453
51120_AGND DCBATOUT_51120
51120_LL2 1
2 51120_VBST2_11 R351
2 51120_VBST2
0R0603-PAD
SCD1U50V3ZY-GP
C784
L37
51120_DRVH1
51120_LL1
5
6
7
8
C454
SC1U10V3KX-3GP
C794
5
6
7
8
4
3
2
1
R354
51120_VREG5 1
2
5D1R3F-GP
GAP-CLOSE-PWR
C792
2
GAP-CLOSE-PWR
G34
2
GAP-CLOSE-PWR
G52
2
Iomax=11A
Qg=9.8nC,
Rdson=20~25mohm
51120_V5FILT
GAP-CLOSE-PWR
G51
2
U49
AO4422-1-GP
SC10U35V0ZY-GP
GAP-CLOSE-PWR
G50
2
SC10U35V0ZY-GP
G33
S
S
S
G
DCBATOUT
DCBATOUT_51120
D
D
D
D
DCBATOUT_51120
2
GAP-CLOSE-PWR
G49
2
4
3
2
1
Rev
SA
LWG2
Sheet
E
37
of
52
DCBATOUT_51124
5
6
7
8
GAP-CLOSE-PWR
G96
2
GAP-CLOSE-PWR
G100
2
GAP-CLOSE-PWR
G97
2
GAP-CLOSE-PWR
G103
2
GAP-CLOSE-PWR
G101
2
1
C443
SCD1U50V3ZY-GP
1
R780
27KR2F-L-GP
SE220U2D5VDM-3GP
2
1
DY
DY
2
51124_PGD1
51124_PGD2
51124_GND
DY
R781
TPS51124RGER-GPU1
51124_TRIP1
51124_TRIP2
CPUCORE_ON
35,37,40,45
DRVL1
DRVL2
DRVH1
DRVH2
21
10
PGND1
PGND2
GND
GND
18
13
25
3
R786
1
51124_TONSEL
DY
51124_DRVH1
51124_DRVH2
2 51124_V5FILT
10KR2J-3-GP
R788
0R0402-PAD
51124_GND
51124_GND
51124_DRVL2
2
0R0402-PAD
VO1
VO2
VBST1
VBST2
TRIP1
TRIP2
17
14
LL1
LL2
20KR3F-GPR789
20KR3F-GP
R789
R790
20KR3F-GP
51124_GND
51124_DRVL1
51124_GND
G105
51124_LL1
ENG
2C878
51124_VBST1
GAP-CLOSE-PWR
SCD1U50V3ZY-GP
IND-3D3UH-55-GP
51124_LL2
2 C879
51124_VBST2
51124_GND
1
2
C447
SCD1U50V3ZY-GP
DY
Vtrip(mV)=Rtrip(Kohm)*10(uA)
Iocp=(Vtrip/Rdson)+((1/(2*L*f))*((Vin-Vout)*Vout)/Vin))
R794
51124_GND
Vout=0.75V*(R1+R2)/R2
1
2
1
1
2
R793
SCD1U50V3ZY-GP
<Variant Name>
Wistron Corporation
75KR3F-GP
ENG
30K1R3F-GP
SC33P50V3JN-GP
S
S
S
G
DY
51124_VFB2
C880
TC10
SE220U2VDM-8GP
5
6
7
8
K
1
1D05V_PWR
D
D
D
D
4
3
2
1
GAP-CLOSE-PWR
G99
2
2
4
3
2
1
S
S
S
G
SC10U35V0ZY-GP
SC10U35V0ZY-GP
EC424
OCP>14A
SCD1U25V3ZY-1GP
51124_GND
Voutsetting=1.051V
L34
51124_DRVL2
1D05V Iomax=7A
C445
1
2
1
5
6
7
8
D
D
D
D
C446
20
11
1
R784
TONSEL
EN1
EN2
DY
C877
SCD01U16V3KX-GP
51124_GND
SCD01U16V3KX-GP
DCBATOUT_51124
DY
C876
V5FILT
V5IN
23
8
2
0R0402-PAD
19
12
51124_EN1_1
51124_EN2_1
2
0R0402-PAD
2
0R0402-PAD
51124_LL1
51124_LL2
U39
AO4406-1-GP
2
15
16
22
9
1
R785
1
R787
16,30,40 PM_SLP_S5#
16,18,30,33,40,49 PM_SLP_S3#
2
5
VFB1
VFB2
U44
1
6
1
C875
SC1U10V3ZY-6GP
51124_V5FILT
C873
24
7
1D05V_PWR
1D8V_PWR
51124_VFB2
51124_VFB1
1
R783
PGOOD1
PGOOD2
R782
3D3R3J-L-GP
51124_GND
51124_LL2
GAP-CLOSE-PWR
GAP-CLOSE-PWR
51124_DRVH2
2
GAP-CLOSE-PWR
G98
2
100KR2J-1-GP
5V_S5
U40
AO4422-1-GP
51124_VFB1
3D3V_S0
GAP-CLOSE-PWR
G86
2
1D8V Iomax=7A
OCP>14A
GAP-CLOSE-PWR
G88
2
G102
Voutsetting=1.838V
Panasonic 220uF ESR=15mohm

Iripple=2.7A
GAP-CLOSE-PWR
G87
2
R779
39K2R2F-L-GP
GAP-CLOSE-PWR
G84
2
51124_DRVL1
GAP-CLOSE-PWR
GAP-CLOSE-PWR
G91
2
C874
GAP-CLOSE-PWR
G92
2
GAP-CLOSE-PWR
G32
2
SC4D7U10V5ZY-3GP
GAP-CLOSE-PWR
G85
2
DY
D28
S
S
S
G
1D8V_PWR
1D8V_PWR
TC11
SSM24PT-GP
G90
1D8V_S3
IND-3D3UH-55-GP
GAP-CLOSE-PWR
G31
2
U42
AO4406-1-GP
1D8V / 7.0A
OCP>=14A
C426
GAP-CLOSE-PWR
G30
2
1D05V_S0
D
D
D
D
1D05V_PWR
L35
4
3
2
1
1D05V_S0/7A
OCP>=14A
51124_DRVH1
51124_LL1
ENG
4
3
2
1
1
GAP-CLOSE-PWR
G29
2
SC33P50V3JN-GP
GAP-CLOSE-PWR
G28
2
C425
S
S
S
G
EC444
SCD1U25V3ZY-1GP
SC10U35V0ZY-GP
SC10U35V0ZY-GP
D
D
D
D
U43
AO4422-1-GP
G27
DCBATOUT_51124
5
6
7
8
DCBATOUT
Panasonic 220uF ESR=15mohm

Iripple=2.7A
GND
OPEN
V5FILT
230k/CH1
283k/CH2
283k/CH1
346k/CH2
346k/CH1
423k/CH2
Title
TONSEL
TPS51124 1D8V_S3/1D05V_S0
Size
A3
Document Number
Rev
SA
LWG2
Sheet
38
of
52
MAX8725_PDS
AD+
ID = 10A @
VGS = 10V
DCBATOUT
AO4433-GP
1
2
3
4
1
C567
SC1U50V5ZY-1-GP
2
2
2
1
8725_CSIN
1
2
1
CHG_PWR-3
MAX8725_CLS
R490
20KR2F-L-GP
SCD1U25V3ZY-1GP
1
C29
R488
15K4R2F-GP
ISOURCE_MAX = (0.075/R465)*(VCLS/VREF)
=4.1A
So,Constant Power=19V*4.1A=77.9W
EC50
EC49
V_REF :4.2235V (<500uA)
MAX8725ETI-GP-U
74.08725.A73
SCD1U25V3ZY-1GP
C881
SC1KP50V3KX-GP
G15
GAP-CLOSE
<Variant Name>
Pre-CHG_I = 305mA
BATA_CHG_I = (0.075/R477)*(VICTL/3.6)
=3.0A
BATB_CHG_I = (0.075/R477)*(VICTL/3.6)
=2.46A
Wistron Corporation
Title
CHARGER_MAX8725
Size
A3
Document Number
Rev
SA
LWG2

5
DY
C24
17
16
15
CSIN
BATT
GND
4
3
2
1
CCV
CCI
CCS
C13
SC10U25V0KX-3GP
8725_CSIP
18
-1 Modify
C15
SC10U25V0KX-3GP
CSIP
C14
29
C10
SC10U25V0KX-3GP
PGND
G58
GAP-CLOSE
PGND
19
G59
GAP-CLOSE
SC10U25V0KX-3GP
DLO
CSSN
5
6
7
8
25
26
2
1
1
MAX8725_DLO
20
Current limit setting:

85W(85W/20V=4.25A)
13
12
14
30
AC_IN#
Q31
2N7002-7F-GP
1st BTY
1st BTY
SA rework 0920
MAX8725_ACOK
R713
100KR2J-1-GP
U65
AO4422-1-GP
PKPRES
SC1U10V3ZY-6GP
1st BTY
1 2
D
2
MAX1909_LDO
ACOK
MAX8725_REF
1
2CHG_PWR-3 1 R477
2
IND-10UH-110-GP
D01R3720F-2-GP
REF
C25
SCD01U50V3KX-4GP
R468
47KR2J-2-GP
SCD01U50V3KX-4GP
Q38
2N7002-7F-GP
MAX8725_DHI
CLS
R15
1KR2J-1-GP
C26
CHG_PWR-2
Near MAX1909
Pin 21
1
2
5V_AUX_S5
C27
CHG_4D35V#
MAX8725_ACOK
R487
1
2 CHARGE_ON1#
100KR2J-1-GP
1 R22
2
30,41 BATA_IN#
1KR2J-1-GP
MAX8725_CCV
MAX8725_CCI
MAX8725_CCS
SC1KP50V2KX-1GP
30
MAX1909_LDO
R504
78K7R3F-GP
R500
100KR2J-1-GP
MAX8725_CLS
DY
R18
10KR2F-2-GP
C557
5V_AUX_S5
1
2
240KR2F-L-GP
2
SC1U10V3ZY-6GP
2
1
1
1
100KR2J-1-GP
C28
2
SC1U10V3ZY-6GP
2
1
IINP
MAX8725_IINP
23
MAX8725_DLOV
L3
5
6
7
8
CSSP
1
2
1
R20
20KR2F-L-GP
DHI
BT+
C48
SC1U10V3ZY-6GP
SC10U35V0MX-1GP
ACIN
33R2J-2-GP
SC10U35V0ZY-GP
21
R37
C32
SC10U35V0ZY-GP
V( MODE ) >=2.8V = 4 Cell

V( MODE ) = 1.8V = 3 Cell MAX8725_ACIN
DLOV
VCTL
ICTL
MODE
C558
22
28
2
C31
S
S
S
G
CHG_V_PWM
11
10
7
DHIV
PDL
LDO
U66
AO4419-1-GP
SC1U10V3ZY-6GP
D
D
D
D
30
DY
R503
MAX8725_ICTL
MAX8725_MODE
SC1U10V3ZY-6GP
When V(ICTL)<0.8V or DCIN<7V

-->Charge Disable MAX8725_VCTL
PDS
SRC
DCIN
D
D
D
D
R16
MAX8725_PDS 27
AD+_TO_SYS 24
MAX8725_DC_IN 1
C51
C49
SCD1U50V3KX-GP
MAX8725_DHIV
R482
100KR2F-L1-GP
U10
R19
39KR2F-GP
Near MAX1909
Pin 2
4
3
2
1
1
2
MAX1909_LDO
Near MAX1909
Pin 1
MAX8725_REF
DY
LDO :5.40V (< 5mA)
S
S
S
G
MAX1909_LDO
R17 1
100KR2J-1-GP
EC68
AD+_TO_SYS
SCD1U50V3KX-GP
MAX8725_CSSN
MAX8725_CSSP
SCD1U50V3KX-GP
C52
SCD1U25V3ZY-1GP
EC559
SCD1U50V3KX-GP
DCBATOUT
C568
D12
CH521S-30-GP-U
SET Vout MAX VCELL= 4.1998V/CELL

VBAT=CELL*VCELL==>VCELL=VBAT/CELL
=VREF+(VVCTL-1.8) /9.52 =4.1998V
CHG_I_PWM
AO4407-1-GP
G56
GAP-CLOSE
G57
GAP-CLOSE
AC_IN > 2.089V --> AC DETECT
C569
30
BT+
AC_IN Threshold 2.089V Max.
AD+
8
7
6
5
R507
13KR2F-GP
Near MAX1909
Pin 3
D
D
D
D
Near MAX1909
Pin 24
1
1
C30
SC1U10V3ZY-6GP
U16
S
S
S
G
MAX8725_ACIN
1 R465
D01R3720F-2-GP
U61
C549
SCD1U50V3KX-GP
AD+_TO_SYS
1
R489
100KR2F-L1-GP
D
D
D
D
4
3
2
1
S
S
S
G
5
6
7
8
SCD1U50V3ZY-GP
Sheet
1
39
of
52
1D5V_S0
Iomax=4.0A
FB
1D5V_S0
APL5912-KAC-GP
74.05912.A71
GAP-CLOSE-PWR
C239
R165
1K78R3F-GP
5912_FB
SO-8-P
R204
2KR2F-3-GP
TC3
ST100U4VBM-L1-GP
3
Trace Length=3cm
Trace Width=5mils
Trace Resistance>80mohm
3
4
1
VOUT
VOUT
EN
5
9
SCD01U16V2KX-3GP
2
1
1
R27
1KR2F-3-GP
OCP=6A
Vo(cal.)=1.512V
VIN
VIN
GAP-CLOSE-PWR
G16
2
POK
PM_SLP_S3#
VCNTL
GAP-CLOSE-PWR
G17
2
TC1
ST100U4VBM-L1-GP
1
2
0R0402-PAD
35,37,38,45 CPUCORE_ON
GND
R28
2K21R3F-L-GP
Rh/Rl=(Vout/0.8)-1
U22
R202
C237
SC10U10V5ZY-1GP
2D5V_S0
G18
Vo (cal.)=2.568V
74.05332.B31
C271
SC10U10V5ZY-1GP
DY
2D5V_PWR
1
2
3
4
C238
SC1U10V3ZY-6GP
1
2
C40
SC10U10V5ZY-1GP
APL5332KAC-TRLGP
VIN
BS
FB
VOUT
NC#8
NC#7
GND
NC#5
GND
U6
8
7
6
5
1D8V_S3
5V_S5
3D3V_S0
2D5V
Iomax=1A
Vo=0.8*(1+(R1/R2))
1D2V_S0
Iomax=2A
1D8V_S0
DDR_VREF_S0
1
PM_SLP_S3#
2K2R2F-GP
TPS51100DGQR-GP
C76
SCD1U16V2ZY-2GP
C774
SC10U10V5ZY-1GP
1D2V_PWR
1
3
6
VIN
VREF
VCNTL
2
9
GND
GND
VOUT
NC
NC
NC
8
7
5
C775
SC10U10V5ZY-1GP
1D2V_S0
GAP-CLOSE-PWR
TC2
ST100U4VBM-L1-GP
Trace Length=1cm (500mils)

Trace Width=8mils
Trace Resistance>25mohm
SO-8-P
Vout=1.8V*R2/(R1+R2)
2nd source: 74.02997.079
GAP-CLOSE-PWR
G22
2
U7
74.05331.B31
1
2
74.51100.079
GAP-CLOSE-PWR
G21
2
APL5331KAC-TRLGP
-1 Modify
11
R29
GAP-CLOSE-PWR
DY
SCD1U16V2ZY-2GP
C772
SC10U10V5ZY-1GP
C771
DDR_VREF_S3
APL5331_1D2V_VREF
1
2
3
4
5
GND
16,18,30,33,38,49
VIN
VDDQSNS
S5
VLDOIN
GND
VTT
S3
PGND
VTTREF VTTSNS
10
9
8
7
6
GAP-CLOSE-PWR
G19
2
GAP-CLOSE-PWR
G93
2
R30
1KR2F-3-GP
GAP-CLOSE-PWR
G94
2
Vo(cal.)=1.200V
1D8V_S0
U74
16,30,38 PM_SLP_S5#
C18
SCD1U16V2ZY-2GP
G95
1
2
C429
SC1U10V3ZY-6GP
C432
SC10U10V5ZY-1GP
0D9V_PWR
G20
5V_S5
C565
SC10U10V5ZY-1GP
1D8V_S3
5V_S5
0D9V
Iomax=1A
<Variant Name>
Wistron Corporation
Title
0D9V/1D2V/1D5V/2D5V
Size
A3
Document Number

A
Rev
SA
LWG2
Sheet
E
40
of
52
ADAPTER IN CIRCUIT
DCIN1
AD+
4
AD+_JK
U62
S
S
S
G
D
D
D
D
8
7
6
5
AO4433-GP
AD+_G
R470
100KR2F-L1-GP
Q32
R2
R1
C550
1
2
3
4
MH1
DC-JACK93-U
22.10261.011
SCD47U50V5ZY
2
1
K
D3
1
2
2
6
EC55
R469
330KR2F-L-GP
P4SSMJ24PT-GP
SCD1U50V3ZY-GP
EC51
EC56
SCD1U50V3ZY-GP
SCD1U50V3ZY-GP
30
PDTA144EU-1GPU
Q5
CHT2222APT-GP
AD_OFF
connect to KBC
MAIN BATTERY CONNECTOR
KBC_3D3V_AUX
3D3V_AUX_S5
D10
BAV99PT-GP-U
D9
BAV99PT-GP-U
D8
BAV99PT-GP-U
83.00099.K11
DY
DY
BAT1
R73
100KR2F-L1-GP
8
1
RN8
BATA_CLK_1
4
3BATA_DAT_1
1
2
30 BATA_SCL
30 BATA_SDA
30,39 BATA_IN#
SRN33J-5-GP-U
1
1
2
DY
EC9
C560
SCD1U50V3ZY-GP
C561
DUMMY-C3
SYN-CON7-15-GP
20.80352.007
DY
SCD1U10V2KX-4GP
DY
EC10
EC11
SC1KP50V3KX-GP
SCD1U10V2KX-4GP
BT+
2
3
4
5
6
7
9
<Variant Name>
Wistron Corporation
Title
AD/BATT CONN
Size
A3
Document Number
Rev
SA
LWG2
Sheet
1
41
of
52
U70A
STRAPS
PART 1 OF 7
PCIE TEST PADS

PCIE TEST POINTS MUST BE WITHIN 250 MILS
OF THE ASIC BALL WITH POSITIVE AND NEGATIVE
SIGNALS THE SAME DISTANCE
PEG_TXP0
PEG_TXN0
AJ31
AH31
PCIE_RX0P
PCIE_RX0N
PEG_TXP1
PEG_TXN1
AH30
AG30
PCIE_RX1P
PCIE_RX1N
PEG_TXP2
PEG_TXN2
AG32
AF32
PCIE_RX2P
PCIE_RX2N
PEG_TXP3
PEG_TXN3
AF31
AE31
PCIE_RX3P
PCIE_RX3N
PEG_TXP4
PEG_TXN4
AE30
AD30
PEG_TXP5
PEG_TXN5
PEG_TXP6
PEG_TXN6
TPAD28 TP72
TPAD28 TP73
AC31
AB31
AB30
AA30
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
I
N
T
E
R
F
A
C
E
PCIE_TX0P
PCIE_TX0N
1
1
SCD1U16V2KX-3GP
PEG_RXP0
2
SCD1U16V2KX-3GP
PEG_RXN0
2
STRAP_B_PTX_PWRS_ENB
GPIO0
PCIE_TX1P
PCIE_TX1N
AJ25
AH25
C75
C74
1
1
SCD1U16V2KX-3GP
PEG_RXP1
2
SCD1U16V2KX-3GP
PEG_RXN1
2
STRAP_B_PTX_DEEMPH_EN
GPIO1
PCIE_TX2P
PCIE_TX2N
AH28
AG28
C117 1
C118 1
SCD1U16V2KX-3GP
PEG_RXP2
2
SCD1U16V2KX-3GP
PEG_RXN2
2
PCIE_TX3P
PCIE_TX3N
AG27
AF27
C114 1
C113 1
SCD1U16V2KX-3GP
PEG_RXP3
2
SCD1U16V2KX-3GP
PEG_RXN3
2
PCIE_TX4P
PCIE_TX4N
AF25
AE25
C122 1
C121 1
SCD1U16V2KX-3GP
PEG_RXP4
2
SCD1U16V2KX-3GP
PEG_RXN4
2
PCIE_TX5P
PCIE_TX5N
AE28
AD28
PCIE_TX6P
PCIE_TX6N
AD27
AC27
PCIE_TX7P
PCIE_TX7N
AC25
AB25
PCIE_TX8P
PCIE_TX8N
AB28
AA28
C170 1
C171 1
SCD1U16V2KX-3GP
PEG_RXP8
2
SCD1U16V2KX-3GP
PEG_RXN8
2
ROMIDCFG(3:0)
GPIO[9,13:11]
MEMORY APERTURE SIZE
GPIO[13:11]
C115 1
C116 1
C159 1
C161 1
SCD1U16V2KX-3GP
PEG_RXP5
2
SCD1U16V2KX-3GP
PEG_RXN5
2
Y31
W31
PCIE_RX9P
PCIE_RX9N
PCIE_TX9P
PCIE_TX9N
AA27
Y27
C163 1
C162 1
SCD1U16V2KX-3GP
PEG_RXP9
2
SCD1U16V2KX-3GP
PEG_RXN9
2
PEG_TXP10
PEG_TXN10
W30
V30
PCIE_RX10P
PCIE_RX10N
PCIE_TX10P
PCIE_TX10N
Y25
W25
C158 1
C157 1
SCD1U16V2KX-3GP
PEG_RXP10
2
SCD1U16V2KX-3GP
PEG_RXN10
2
PCIE SIGNALS CONNECT TO ROOT COMPLEX
PEG_TXP11
PEG_TXN11
V32
U32
PCIE_RX11P
PCIE_RX11N
PCIE_TX11P
PCIE_TX11N
W28
V28
C167 1
C168 1
SCD1U16V2KX-3GP
PEG_RXP11
2
SCD1U16V2KX-3GP
PEG_RXN11
2
REFER TO PCI EXPRESS DESIGN GUIDE

FOR RECOMMENDED AC COUPLING CAPS
PLACEMENT ALONG THE TX INTERCONNECT
PEG_TXP12
PEG_TXN12
U31
T31
PCIE_RX12P
PCIE_RX12N
PCIE_TX12P
PCIE_TX12N
V27
U27
C169 1
C166 1
SCD1U16V2KX-3GP
PEG_RXP12
2
SCD1U16V2KX-3GP
PEG_RXN12
2
PEG_TXP13
PEG_TXN13
T30
R30
PCIE_RX13P
PCIE_RX13N
PCIE_TX13P
PCIE_TX13N
U25
T25
C160 1
C222 1
SCD1U16V2KX-3GP
PEG_RXP13
2
SCD1U16V2KX-3GP
PEG_RXN13
2
SCD1U16V2KX-3GP
PEG_RXP14
2
SCD1U16V2KX-3GP
PEG_RXN14
2
SCD1U16V2KX-3GP
PEG_RXP15
2
SCD1U16V2KX-3GP
PEG_RXN15
2
7 PEG_TXN[15..0]
PEG_RXN[15..0]
PEG_TXP[15..0]
PEG_TXN[15..0]
GPIO5
PCIE_RX14P
PCIE_RX14N
PCIE_TX14P
PCIE_TX14N
T28
R28
PEG_TXP15
PEG_TXN15
P31
N31
PCIE_RX15P
PCIE_RX15N
PCIE_TX15P
PCIE_TX15N
R27
P27
C220 1
C219 1
DEBUG ACCESS
AL28
AK28
PCIE_REFCLKP
PCIE_REFCLKN
7,16,20,22,26,30,32
PLT_RST1#
R111 1 100R2J-2-GP
VGA_RST#
2
1
2
SC100P50V2JN-3GP
C420 PCIE_TEST
AG24
PERSTB
AA24
PCIE_TEST
AF24
PERSTB_MASK
PCIE_CALRN
PCIE_CALRP
AE24
AD24
PCIE_CALRN
PCIE_CALRP
PCIE_CALI
AB24
PCIE_CALI
R112
2PERSTB_MASK
10KR2F-2-GP
Tie To VSS
M52P-GP
71.0M52P.00U
M54P:71.0M54P.A0U
M56P:71.0M56P.B0U
23
DO NOT INSTALL
10K RESISTORS
DON'T FORCE COMPLIANCE STATE(M52P,M54P,M56P)
MEMID
SERIAL FLASH ROM TYPE (M26X,M52P,M54P,M56P)

- SERIAL M25P10 ROM
1011
IF NO ROM
GPIO11(M26X) AND GPIO12,13(M52,M54,M56)
SET MEMORY APERTURE SIZE
SEE M26X,M54X,M56X DATA BOOK FOR
MEMORY,FRAME BUFFER APERATURE SETTINGS
TBD
MEMORY TYPE AND SPEED SELECT
TBD
H2SYNC
V2SYNC
GENERICC
NO STRAP FUNCTION
RSVD
PCIE_TEST
DO NOT INSTALL
10K RESISTORS
ATI FEATURE NOT ENABLED (M52P,M54P,M56P)

NO STRAP (M26X)
ATI FEATURE NOT ENABLED (M52P,M54P,M56P)

NO STRAP (M26X)
3D3V_S0
1D2V_S0
22
21
20
MEM_ID0
MEM_ID2
MEM_ID1
MEM_ID3
1
1
0
0
0
1
1
0
DO NOT INSTALL
10K RESISTORS
(3:0)
R538 1
2 2KR2F-3-GP
1 R133
2
562R3F-GP
R135 1
2 1K47R3F-GP
FOR M26X
PCIE_CALRN = 100R
PCIE CALRP = 150R
PCIE CALI = 10K
FOR M52P,M54P,M56P
PCIE_CALRN = 2K
PCIE CALRP = 562R
PCIE CALI = 1.47K
INSTALL
10K RESISTORS
NO DEBUG ACCESS (M26X)
GPIO8
Calibration
Clock
CLK_PCIE_PEG
CLK_PCIE_PEG#
3 CLK_PCIE_PEG
3 CLK_PCIE_PEG#
DO NOT INSTALL
10K RESISTOR
NO ATI FEATURE ENABLED (M52P,M54P,M56P)
NO STRAP FUNCTION
R32
P32
DO NOT INSTALL
10K RESISTORS
NO ATI FEATURE ENABLED
NORMAL RANGE (M26X)
RSVD
C221 1
C223 1
GPIO6
MEM_TYPE
PEG_TXP14
PEG_TXN14
TBD
NO ATI FEATURE ENABLED (M52P,M54P,M56P)
FORCE_COMPLIANCE
PEG_TXP9
PEG_TXN9
7 PEG_TXP[15..0]
TRANSMITTER DE-EMPHASIS ENABLE

DEPENDS ON PCIE CHIPSET BEING USED
FOR M26X,M5X
INSTALL WITH ATI RS480,RS400,RX480,
RC410,RS482 CHIPSETS
FOR M26X ONLY
DO NOT INSTALL WITH INTEL 915PM CHIPSET
NO DEBUG ACCESS (M52P,M54P,M56P)
COMMON MODE RANGE
SCD1U16V2KX-3GP
PEG_RXP7
2
SCD1U16V2KX-3GP
PEG_RXN7
2
INSTALL
10K RESISTOR
DO NOT FORCE COMPLIANCE STATE QUICKLY (M26X)
RSVD
C164 1
C165 1
TRANSMITTER POWER SAVINGS ENABLE

- FULL TX OUTPUT SWING
NOT REVERSED LANE (M26X)
GPIO4
STRAP_FORCE_COMPLIANCE
sets the desired PCIE PLL
bandwidth for M5x parts.
SCD1U16V2KX-3GP
PEG_RXP6
2
SCD1U16V2KX-3GP
PEG_RXN6
2
PCIE_RX8P
PCIE_RX8N
7 PEG_RXN[15..0]
GPIO(3:2)
DEBUG ACCESS
AA32
Y32
PEG_RXP[15..0]
RSVD
REVERSE LANES
RECOMMENDED
DESCRIPTION OF RECOMMENDED SETTING
C72
C73
PEG_TXP8
PEG_TXN8
7 PEG_RXP[15..0]
PEG_TXP7
PEG_TXN7
1
1
AD32
AC32
PCIE_RX4P
PCIE_RX4N
P
C
I
E
X
P
R
E
S
S
PIN
AK27
AJ27
0
1
1
0
1
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
MEM
64M
64M
128M
256M
128M
256M
128M
256M
SIZE
16M*16
16M*16
16M*16
32M*16
16M*16
32M*16
16M*16
32M*16
VENDOR CHIPs
Infineon
Hynix
Samsung
Samsung
Infineon
Infineon
Hynix
Hynix
x2
x2
x4
x4
x4
x4
x4
x4
43
43
43
43
43
43
43
43
43
43
43
43
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO8
GPIO11
GPIO12
GPIO13
GPIO9
43
43
43
43
43
43
43
MEM_ID3
MEM_ID2
MEM_ID1
MEM_ID0
DAC2_HSY
DAC2_VSY
GENERICC
R64 1
R52 1
R53 1
R58 1
R49 1
R51 1
1
DY R56
1
DY R66
1
DY R50
1
256M R54
1
DY R65
R61
1
DY
GPIO[9,13:11]=0000 for 128M
1
DY R59
DY R55 1
1
In128_In256 R63
R60
Hy128_In256 R106 1
DY R104 1
DY R537 1
DY R151 1
PCIE_TEST
1
DY
When no ROM
GPIO[13:12]
GPIO[13:12]
GPIO[13:12]
GPIO[13:12]
GPIO[13:12]
VGA THERMAL SENSOR
DY
DY
DY
2
2
2
2
2
2
2
2
2
2
2
2
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
2
2
2
2
2
2
2
2
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
is attached, GPIO[9] is set to 0.

is used to select the frame buffer aperture size.
= 00: 128M frame buffer, same as ROM strap 00
= 11: reserved, same as ROM strap 11
<Variant Name>
Wistron Corporation
Place near GPU

Title
IT IS REQUIRED TO DESIGN IN A THERMAL SENSOR

TO FACILITATE THERMAL EVALUATION AND TO PROTECT THE ASIC
ATI M5X-P PCIE 1/4

Size
A3
Document Number
Rev
SA
LWG2
Sheet
1
42
of
52
U70B
AL9
AM9
TX0M
TX0P
AK10
AL10
TX1M
TX1P
AL11
AM11
TX2M
TX2P
AL12
AM12
TX3M
TX3P
AK9
AJ9
&
TX4M
TX4P
AK11
AJ11
M
U
L
T
I
M
E
D
I
A
TX5M
TX5P
AK12
AJ12
2
2K2R2J-2-GP
3D3V_S0
FOR M26X MPVDD

CONNECT TO +1.8V
FOR M52P,M54P,M56P
CONNECT TO VDDC
C65
SC2200P50V2KX-2GP
AH12
VGA_PVDD
AJ14
C98
SC1U6D3V2KX-GP
AH14
VGA_MPVDD
VGA_XTALIN
TPAD28 TP71
R132
1
2
1KR2J-1-GP
A
A6
A5
C656
C657
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
2
0R0603-PAD
R591
1
2
0R0603-PAD
C66
SC10U10V5ZY-1GP
R57
VOLTAGE DIVIDER 3.3V MEM SS

MODOUT TO 1.2V XTALIN/OUT
3D3V_S0
1
AM23
VSS1DI
AL23
R2
DAC2 (TV/CRT2)
G2
B2
AK15
AM15
AL15
H2SYNC
V2SYNC
AF15
AG15
Y
C
COMP
AJ15
AJ13
AH15
R2SET
AK14
A2VDD_1
A2VDD_2
AM16
AL16
A2VSSN_1
A2VSSN_2
AM17
AL17
NC_A2VDDQ
AL14
DMINUS
PVDD
PVSS
Thermal
Diode
PLL &
XTAL
VGA_TESTEN
1 R94
2
10KR2J-3-GP
MPVDD
MPVSS
AL26
1AM26
XTALIN
XTALOUT
AG14
PLLTEST
AG22
TESTEN
AC7
ROMCSb
AK17
AJ19
AF18
AH17
AG17
AG19
AH19
M52P-GP
4
A2VSSQ
AK13
VDD2DI
AJ16
VSS2DI
AJ17
Monitor
Interface
HPD1
AH22
AH23
Test
DDC2DATA
DDC2CLK
AH13
AG13
ROM
DDC3DATA
DDC3CLK
AE12
AF12
GENERICC
AE23
LPVSS
AE18
LVSSR_10
LVSSR_9
LVSSR_8
AF22
AF17
AF21
LVSSR_1
LVSSR_2 LVDS PLL
LVSSR_3 and I/O
LVSSR_4 GND
LVSSR_5
LVSSR_6
LVSSR_7
VGA_VDD1DI
C103
DAC2_HSY
DAC2_VSY
External
SSC
LVDS PLL
and I/O
GND
3
1
R1101
R1091
R107
C106
FOR M26X AVDD

CONNECT TO +1.8V
FOR M52P,M54P,M56P
CONNECT TO +2.5V
C104
R108
2
0R0603-PAD
2D5V_S0
FOR M26X VDD1DI

CONNECT TO +1.8V
FOR M52P,M54P,M56P
CONNECT TO +2.5V
DAC2 CAN BE TV SIGNALS OR SECONDARY CRT

SIGNALS AS CONTROLLED BY AN INTERNAL MUX
DAC2_HSY 42
DAC2_VSY 42
ATI_TV_LUMA 14
ATI_TV_CRMA 14
ATI_TV_COMP 14
VGA_TV_RSET R102 1
VGA_A2VDD
VGA_A2VDDQ 1
VGA_VDD2DI
C94
2
AF11 1 R743
100KR2J-1-GP
DDC1DATA
DDC1CLK
2D5V_S0
SC1U6D3V2KX-GP
VDD1DI
R539
1
2
HCB1608KF121T30-GP
C107
AVSSQ
AVSSN_1
AVSSN_2
AK23
AK25
AJ24
VGA_AVDD
AL25
AM25
VREFG
DPLUS
2
2 510R2F-L-GP
RSET
GPIO_0
General
GPIO_1
Purpose
GPIO_2
I/O
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7_BLON
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
NC_AB6
2 1KR2F-3-GP
VGA_CRT_RSET R105 1
AVDD_1
AVDD_2
DY
adjust SWING at 1.2v
VGA_GENERICB R134 1
AL22
ATI_HSY 14
ATI_VSY 14
G792_DXN3
AC8
19
VGA_VREF
AG12
G792_DXP3
19
AF23
PLACE VREF DIVIDER AND CAP CLOSE TO ASIC
GENERICB
2D5V_S0
2 715R2F-GP
C101
TPAD28 TP70
C99
R103
C102 1
2 0R3-0-U-GP
SC1U6D3V2KX-GP
2D5V_S0
TV
R62
C100
2 0R3-0-U-GP
ATI_DDCDAT 14
ATI_DDCCLK 14
TV
2
150R2F-1-GP
2
150R2F-1-GP
2
150R2F-1-GP
1
2
49 GPIO_PWRCNTL
AJ23
AJ22
AK22
2
0R0603-PAD
1
2
1
C137
2
VGA_CORE_S0
GPIO11
GPIO12
GPIO13
HSYNC
VSYNC
GENERICA
FOR M26X TXVDDR

CONNECT TO +1.8V
FOR M52P,M54P,M56P
CONNECT TO +2.5V
ATI_RED 14
ATI_GREEN 14
ATI_BLUE 14
SCD1U10V2KX-4GP
42
42
SCD1U10V2KX-4GP42
AK24
AM24
AL24
SCD1U10V2KX-4GP
2D5V_S0
TPAD28 TP6
R
G
B
DAC / CRT
FOR M26X TPVDD

CONNECT TO +1.8V
FOR M52P,M54P,M56P
CONNECT TO +2.5V
R523
SCD1U10V2KX-4GP
FOR M26X PVDD

CONNECT TO +1.8V
FOR M52P,M54P,M56P
CONNECT TO +2.5V
AD4
AD2
AD1
AD3
AC1
AC2
AC3
1
AB2
AC6
AC5
AC4
AB3
AB4
AB5
AD5
R484
POW_SW
1
2
AB8
10KR2J-3-GP VGA_GPIO16 AA8
1VGA_ALERT#
AB7
AB6
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO8
GPIO9
R127
499R2F-2-GP
MEM_ID3
MEM_ID2
MEM_ID1
MEM_ID0
42
42
42
42
42
42
42
3D3V_S0
42
42
BE42
42
AJ7
AK7
AL7
AM7
AK8
2D5V_S0
ANY UNUSED GPIO CAN OPTIONALLY

MEMORY TYPE CONFIG STRAPS
R91
42
499R2F-2-GP
42
EDID_DAT
EDID_CLK
EDID_DAT
EDID_CLK
TXVSSR_1
TXVSSR_2
TXVSSR_3
TXVSSR_4
TXVSSR_5
R524
2
0R0603-PAD
C581
SCD1U10V2KX-4GP
13
13
VGA_TXVDDR
C603
C604
SC1U6D3V2KX-GP
4
3
1
2
RN14
SRN4K7J-8-GP
AJ6
AK6
AL6
AM6
SC1U6D3V2KX-GP
SC1U6D3V2ZY-GP
2
1
3D3V_S0
TXVDDR_1
TXVDDR_2
TXVDDR_3
TXVDDR_4
ANY UNUSED GPIO CAN OPTIONALLY BE

PANEL TYPE CONFIG STRAPS
EC: N060188
AL8
C582
SC1U6D3V2KX-GP
1KR2J-1-GP
TPVSS
VGA_TPVDD
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
AM8
12
AF2
AF1
AF3
AG1
AG2
AG3
AH2
AH3
AJ2
AJ1
AK2
AK1
AK3
AL2
AL3
AM3
AE6
AF4
AF5
AG4
AJ3
AH4
AJ4
AG5
AH5
AF6
AE7
AG6
R93
NC_DVOVMODE_0
NC_DVOVMODE_1
TPVDD
SCD1U10V2KX-4GP
X7
XTAL-27MHZ-39-GP
1MR2J-1-GP 82.30034.281
MB88154_XO
C580
DVPCNTL,DVPDATA[23..0] FOR M26X

ARE CONFIGURED FOR
CONNECT TO +1.8V OR VSS
+3.3V SIGNALING MODE
TO DEFINE DVO SIGNAL LEVEL
ON THIS DESIGN
FOR M52P,M54P,M56P
AK4
AL4
NOT CONNECTED
1
1
MB88154_XI
C579 R519
SC22P50V2JN-4GP
SC18P50V2JN-1-GP
R113
147R2F-GP
VGA_XTALIN
DUAL LINK IS
ONLY SUPPORTED ON M56P
DO NOT CONNECT TXM,P[3:5]
WITH M52P,M54P,M26X
SC1U6D3V2ZY-GP
2
1
MB88154PNF-JN-GP
71.88154.A0A
V
I
D
E
O
2
1
C576
GPIO_34
GPIO_33
GPIO_32
GPIO_31
GPIO_30
GPIO_29
GPIO_28
GPIO_27
GPIO_26
GPIO_25
GPIO_24
GPIO_23
GPIO_22
GPIO_21
GPIO_20
GPIO_19
GPIO_18
Expand GPIO
No Spread
R114
R493
R521
180R2F-1-GP
0R2J-2-GP 0R2J-2-GP
MB88154_XI
+-1.5%
+-1.0%
VGA_GPIO16
3D3V_SS_S0
1
2
3
4
CKOUT
VDD
VSS
XIN
SCD1U10V2KX-4GP
SEL1
REFOUT
SEL0
XOUT
8
VGA_XTALIN_1 7
6
MB88154_XO5
Center
Spread
+-0.5%
SEL1 SEL0
AG8
AH7
AG9
AH8
AJ8
AH9
AG10
AF10
AH6
AF8
AF7
AE9
AE10
AG7
AF9
AF13
AE13
U67
VIP Host/External TMDS
R518
0R3-0-U-GP
DY
2
1
R522
DUMMY-R2
Modulation Rate
2
150R2F-1-GP
2
150R2F-1-GP
2
150R2F-1-GP
TXCM
TXCP
Integrated
TMDS
1
R1011
R981
R100
3D3V_S0
R520
0R2J-2-GP
PART 2 OF 7
3D3V_S0
SC1U6D3V2KX-GP
FOR M26X A2VDDQ

CONNECT TO +1.8V
FOR M52P,M54P,M56P
IT IS NO CONNECT
TV
2D5V_S0
FOR M26X VDD2DI

CONNECT TO +1.8V
FOR M52P,M54P,M56P
CONNECT TO +2.5V
For CRT
For DVI
<Variant Name>
For THERMAL SENSOR
Wistron Corporation
GENERICC

42
FOR M26X GENERICC

NO CONNECT OR
EXT SPREAD SPECTRUM INPUT
FOR M52P,M54P,M56P
IT IS GPIO
2
Title
ATI M5X-P IO 2/4

Size
A3
Document Number
Rev
SA
LWG2
Sheet
1
43
of
52
DQMAb_0
DQMAb_1
DQMAb_2
DQMAb_3
DQMAb_4
DQMAb_5
DQMAb_6
DQMAb_7
H31
J29
J26
G23
E21
B15
D14
J17
QSA_0
QSA_1
QSA_2
QSA_3
QSA_4
QSA_5
QSA_6
QSA_7
J31
K29
K25
F23
D20
B16
D16
H15
QSA_0B
QSA_1B
QSA_2B
QSA_3B
QSA_4B
QSA_5B
QSA_6B
QSA_7B
K31
K28
K26
G24
D21
C16
D15
J15
ODTA
ODTA1
F29
D24
CLKA0
CLKA0b
D31
E31
CKEA0
B30
RASA0b
B28
C29
WEA0b
B31
CSA0b_0
CSA0b_1
B29
C28
1D8V_S0
CASA0b
MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63
R581
B12
C12
B11
C11
C8
B7
C7
B6
F12
D12
E11
F11
F9
D8
D7
F7
G12
G11
H12
H11
H9
E7
F8
G8
G6
G7
H8
J8
K8
L8
K9
L9
K5
L4
K4
L5
N5
N6
P4
R4
P2
R2
T3
T2
W3
W2
Y3
Y2
T4
R5
T5
T6
V5
W5
W6
Y4
R8
T8
R7
T7
V7
W7
W8
W9
DQB_0
DQB_1
DQB_2
DQB_3
DQB_4
DQB_5
DQB_6
DQB_7
DQB_8
DQB_9
DQB_10
DQB_11
DQB_12
DQB_13
DQB_14
DQB_15
DQB_16
DQB_17
DQB_18
DQB_19
DQB_20
DQB_21
DQB_22
DQB_23
DQB_24
DQB_25
DQB_26
DQB_27
DQB_28
DQB_29
DQB_30
DQB_31
DQB_32
DQB_33
DQB_34
DQB_35
DQB_36
DQB_37
DQB_38
DQB_39
DQB_40
DQB_41
DQB_42
DQB_43
DQB_44
DQB_45
DQB_46
DQB_47
DQB_48
DQB_49
DQB_50
DQB_51
DQB_52
DQB_53
DQB_54
DQB_55
DQB_56
DQB_57
DQB_58
DQB_59
DQB_60
DQB_61
DQB_62
DQB_63
read strobe
D26
F28
D28
D25
E24
E26
D27
F25
C26
B26
D29
B27
E27
E29
B25
C25
Ch-B
FOR M52P,M54P,M26X
PIN H2 IS MAB12 (BA0)
PIN H3 IS MAB13 (BA1)
PIN D5 IS MAB15 (BA2)
PIN F5 IS MAB14
FOR M56P
PIN H2 IS MA14 (BA0)
PIN H3 IS MA15 (BA1)
PIN D5 IS MA13 (BA2)
PIN F5 IS MAB12
Part 4 of 7
MAB_0
MAB_1
MAB_2
MAB_3
MAB_4
MAB_5
MAB_6
MAB_7
MAB_8
MAB_9
MAB_10
MAB_11
MAB_12
MAB_13
MAB_14
MAB_15
G4
E6
E4
H4
J5
G5
F4
H6
G3
G2
D4
F2
F5
D5
H2
H3
DQMBb_0
DQMBb_1
DQMBb_2
DQMBb_3
DQMBb_4
DQMBb_5
DQMBb_6
DQMBb_7
B8
D9
G9
K7
M5
V2
W4
T9
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
B_BA0
B_BA1
47,48
47,48
DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7
RDQSB0
RDQSB1
RDQSB2
RDQSB3
RDQSB4
RDQSB5
RDQSB6
RDQSB7
B9
D10
H10
K6
N4
U2
U4
V8
QSB_0B
QSB_1B
QSB_2B
QSB_3B
QSB_4B
QSB_5B
QSB_6B
QSB_7B
B10
E10
G10
J7
M4
U3
V4
V9
WDQSB0
WDQSB1
WDQSB2
WDQSB3
WDQSB4
WDQSB5
WDQSB6
WDQSB7
D6
J4
ODTB0
ODTB1
ODTB
ODTB1
MAB12_14 47,48
TP10 TPAD28
QSB_0
QSB_1
QSB_2
QSB_3
QSB_4
QSB_5
QSB_6
QSB_7
CLKB0
CLKB0b
B4
B5
CLKB0
CLKB0#
CKEB0
C2
CKEB0
RASB0b
E2
RASB0#
CASB0b
D3
CASB0#
WEB0b
B2
WEB0#
CSB0b_0
CSB0b_1
D2
E3
CSB0_0#
CSB0_1#
CLKB1
CLKB1b
N2
P3
CLKB1
CLKB1#
For GDDR2
47
47,48
RASB0#
RASB1#
47
47,48
CASB0#
CASB1#
47
47,48
WEB0#
WEB1#
47
CSB0_0#
47,48
CSB1_0#
47
47,48
CKEB0
CKEB1
47
47
CLKB0
CLKB0#
48
48
CLKB1
CLKB1#
RASB0#
RASB1#
CASB0#
CASB1#
WEB0#
WEB1#
CSB0_0#
CSB1_0#
C
CKEB0
CKEB1
CLKB0
CLKB0#
CLKB1
CLKB1#
RDQSB[7..0]
47,48 RDQSB[7..0]
ODTB0 47
ODTB1 47,48
DQMB#[7..0]
47,48 DQMB#[7..0]
MDB[63..0]
47,48 MDB[63..0]
MAB[11..0]
47,48 MAB[11..0]
WDQSB[7..0]
47,48 WDQSB[7..0]
TP9
TPAD28
TP8
TPAD28
100R2F-L1-GP-U
B22
WEA1b
B21
CSA1b_0
CSA1b_1
B23
C23
CASA1b
R590
100R2F-L1-GP-U
1D8V_S0
M52P-GP
B3
C3
MVREFD_1
MVREFS_1
CKEB1
L3
CKEB1
AA3
DRAM_RST
RASB1b
J2
RASB1#
AA5
TEST_MCLK
CASB1b
L2
CASB1#
AA2
TEST_YCLK
WEB1b
M2
WEB1#
AA7
MEMTEST
CSB1b_0
CSB1b_1
K2
K3
CSB1_0#
CSB1_1#
B24
2
RASA1b
MVREFD1
MVREFS1
C666
SCD1U10V2KX-4GP
CKEA1
C22
4
3
B20
C19
CLKA1
CLKA1b
MVREFD_0
MVREFS_0
read strobe
C31
C30
MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14
MAA_15
DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63
write strobe
M31
M30
L31
L30
H30
G31
G30
F31
M27
M29
L28
L27
J27
H29
G29
G27
M26
L26
M25
L25
J25
G28
H27
H26
F26
G26
H25
H24
H23
H22
J23
J22
E23
D22
D23
E22
E20
F20
D19
D18
B19
B18
C17
B17
C14
B14
C13
B13
D17
E18
E17
F17
E15
E14
F14
D13
H18
H17
G18
G17
G15
G14
H14
J14
MEMORY INTERFACE A
U70D
Ch-A
FOR M52P,M54P,M26X
PIN B25 IS MA12 (BA0)
PIN C25 IS MA13 (BA1)
PIN E29 IS MA15 (BA2)
PIN E27 IS MA14
FOR M56P
PIN B25 IS MA14 (BA0)
PIN C25 IS MA15 (BA1)
PIN E29 IS MA13 (BA2)
PIN E27 IS MA12
Part 3 of 7
write strobe
U70C
MEMORY INTERFACE B
R580
RN15
SRN4K7J-8-GP
M52P-GP
R714
243R3F-GP
PLACE MVREF DIVIDERS

AND CAPS CLOSE TO ASIC
R589
1
2
C665
SCD1U10V2KX-4GP
100R2F-L1-GP-U
SC Modify
<Variant Name>
100R2F-L1-GP-U
Wistron Corporation
PLACE MVREF DIVIDERS

AND CAPS CLOSE TO ASIC

Title
ATI M5X-P MEM 3/4

Size
A3
Document Number
Rev
SA
LWG2
Sheet
1
44
of
52
U70E
VGA_VDDRH1
1
2
VGA_LVDDRL1
C155
M52P-GP
C251
1
2
1
2
1
2
1
2
C208
C154
FOR M26X VDD25

CONNECT TO +1.5V
FOR M52P,M54P,M56P
CONNECT TO +2.5V
C148 1 R130
2
0R0603-PAD
2D5V_S0
FOR M26X VDDPLL

CONNECT TO VDDC
FOR M52P,M54P,M56P
CONNECT TO +1.2V
C147
1 R136
2
0R0603-PAD
1 R152
2
0R0603-PAD
1D2V_S0
1 R147
2
0R0805-PAD
VGA_CORE_S0
FOR M26X LPVDD

CONNECT TO +1.8V
FOR M52P,M54P,M56P
CONNECT TO +2.5V
2D5V_S0
1 R67
2
0R0805-PAD
2D5V_S0
FOR M26X LVDDR PINS

AE20,AF20,AF19
CONNECT TO +1.8V
FOR M52P,M54P,M56P
CONNECT TO +2.5V
1 R131
2
0R0805-PAD
2D5V_S0
FOR M26X LVDDR PINS

AC21,AC22,AD21,AD22,AE21,AE22
CONNECT TO +2.8V
FOR M52P,M54P,M56P
CONNECT TO +2.5V
C151
C197
1
2
1
SC4D7U6D3V3KX-GP
2
1
2
1
1
2
1
2
C149
C146
C153
SC1U6D3V2KX-GP
C97
C206
C201
1
2
1
2
1
2
1
SC1U6D3V2ZY-GP
2
1
1
2
1
1
2
1
2
C67
VGA_LVDDRL0
LVDDR/VDDL1_1
LVDDR/VDDL1_2
LVDDR/VDDL1_3
LVDDR/VDDL2_1
LVDDR/VDDL2_2
LVDDR/VDDL2_3
AC21
AC22
AD22
AE21
AD21
AE22
AF20
AE20
AF19
SC1U6D3V2KX-GP
1
2
1
2
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1 SC1U6D3V2KX-GP
2
1
2
1
2
1
2
1
SC1U6D3V2KX-GP
SC1KP16V2KX-GP
SC1KP16V2KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP
2
1
2
1
2
1
1
PCI-Express
Core
1
2
C202
VSSRH0
VSSRH1
LVDDR/VDDL0_1
LVDDR/VDDL0_2
LVDDR/VDDL0_3
1 R171
2
0R0603-PAD
A28
E1
AE19
SC1U6D3V2ZY-GP
2
1
1
2
VGA_VDDRH0
VDDRH0
VDDRH1
VGA_VDDCI
C212
SC1U6D3V2ZY-GP
2
1
1
2
1 R172
2
0R0603-PAD
A27
F1
LVDS PLL, I/O
1
2
I/O Internal
1
2
SCD01U25V2KX-3GP
SCD01U25V2KX-3GP
1
2
1
2
2
SC1U6D3V2ZY-GP
1
2
1
1SC10U6D3V5MX-3GP
SC1U6D3V2KX-GP
2
1
2
1
2
1
2
1
2
2
1
2
1
SC1U6D3V2KX-GP
2
1
SC1U6D3V2KX-GP
2
1
1
SC1U6D3V2KX-GP
VGA_VDDPLL
C172
LPVDD/VDDL0
C200
C150
VGA_LPVDD
C244
SC1U6D3V2KX-GP
2 R166
1
0R3-0-U-GP
PART 7 OF 7
SA rework 0924
Forward
3D3V_S0
1
D
Q11
2N7002-7F-GP
M56P
2
0R2J-2-GP
R149
2
VGA_BBN
VGA_BBP
0R2J-2-GP
BACK BIASING APPLIES TO M56P ONLY

IF BACK BIAS NOT USED ON M56,CONNECT
BBN PINS TO VSS AND BBP PINS TO VDDC
BBN,BBP PINS ARE NO CONNECT FOR
M26X,M54P,M52P
R148
VGA_CORE_S0
Y23
K15
R10
AC17
AC14
M23
V10
K18
BBN_4
BBN_3
BBN_2
BBN_1
BBP_4
BBP_3
BBP_2
BBP_1
L10
K22
AA10
VDD25_4
VDD25_5
VDD25_6
1
3
C210
Power)
SC1U6D3V2ZY-GP
2
1
C195
for VGATE_PWRGD have abnormal ripple when S0 power on , it may cause by 5V_S0(Vcc
VARY_BL
DIGON
GENERICD
Only used in
dual-channel
LVDS mode.
TXCLK_UP
TXCLK_UN
TXOUT_U3P
TXOUT_U3N
TXOUT_U2P
TXOUT_U2N
TXOUT_U1P
TXOUT_U1N
TXOUT_U0P
TXOUT_U0N
AJ21
AK21
AH21
AG21
AG20
AH20
AK20
AJ20
AG18
AH18
ATI_TXBCLK+ 13
ATI_TXBCLK- 13
ATI_TXBOUT2+
ATI_TXBOUT2ATI_TXBOUT1+
ATI_TXBOUT1ATI_TXBOUT0+
ATI_TXBOUT0-
13
13
13
13
13
13
LVDS channel
This channel is
used as the
transmitting
channel in single
channel LVDS mode.
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P
TXCLK_LN
TXCLK_LP
AK19
AL19
AL20
AM20
AL21
AM21
AK18
AJ18
AL18
AM18
ATI_TXAOUT0ATI_TXAOUT0+
13
13
13
13
13
13
BLON_IN 30
ATI_LCDVDD_ON
C142
13
FOR M26X GENERICD

NO CONNECT OR
EXT SPREAD SPECTRUM OUTPUT
FOR M52P,M54P
IT IS A GPIO
FOR M56P
IT IS A BACK BIAS REGULATOR CONTROL
R129
10KR2J-3-GP
ATI_TXACLK- 13
ATI_TXACLK+ 13
M52P-GP
2D5V_S0
SCD1U10V2KX-4GP
2
VGATE_PWRGD 7,16,35
0R2J-2-GP
2
CPUCORE_ON 35,37,38,40
0R2J-2-GP
SCD1U10V2KX-4GP
1 DY
R167
1
R206
BLON_IN
AD12
AE11
AD23
M56P
R205
100KR2J-1-GP
PWROK#
Control and External SSC
Compatibility
BLON CAN ALSO BE A PWM OUTPUT

FOR BRIGHTNESS CONTROL
U70G
Q10
SI2301BDS-T1-GP
DY
M52P-GP
W10
T14
W17
P16
T23
K14
U19
C205
C152
SCD1U10V2KX-4GP
VGA_VDDR5
C93
VDDR4 AND VDDR5

IN M26X CAN BE 1.8V OR 3.3V
DEPENDING ON M26X DVOMODE
OR M52P,M54P,M56P REGISTER
CONFIGURATION
1D8V_S0
VDDCI_1
VDDCI_2
VDDCI_3
VDDCI_4
VDDCI_5
VDDCI_6
VDDCI_7
VGA_VDD25
C143
C144
SC1U6D3V2KX-GP
SC1U6D3V2ZY-GP
AC15
C145
C204
SCD1U10V2KX-4GP
VDDR5_1
VDDR5_2
VDDR5_3
VDDR5_4
VDDPLL
C140
C207
SCD1U10V2KX-4GP
AE2
AE3
AE4
AE5
VGA_VDDR4
C96
C91
AC13
AC16
AC18
C108C110
VGA_CORE_S0
C198
SCD1U10V2KX-4GP
VDDR4_1
VDDR4_2
VDDR4_3
VDDR4_4
VDD25_1
VDD25_2
VDD25_3
C111
C109
1 R116
2
0R0805-PAD
R92
1
2
0R0603-PAD
AJ5
AM5
AL5
AK5
AC11
AC12
P14
U15
W14
W15
R17
R15
V15
V16
T16
U16
T17
U17
V14
R18
T18
V18
P18
P19
R19
W19
AD11
C112
1 R150
2
0R0805-PAD
SCD1U10V2KX-4GP
C95
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VGA_PCIE_VDDR12_2
C217
C213
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1
2
0R0603-PAD
VDDR3_1
VDDR3_2
VDDR3_3
VDDR3_4
VDDR3_5
VDDR3_6
VDDR3_7
VDDR3_8
AL31
AM31
AM30
AL32
AL30
AM28
AL29
AM29
AM27
SCD1U10V2KX-4GP
R536
C138
AB9
AB10
AA9
AC19
AD18
AC20
AD19
AD20
P
O
W
E
R
PCIE_VDDR_12_1
PCIE_VDDR_12_2
PCIE_VDDR_12_3
PCIE_VDDR_12_4
PCIE_VDDR_12_5
PCIE_VDDR_12_6
PCIE_VDDR_12_7
PCIE_VDDR_12_8
PCIE_VDDR_12_9
C216
1D2V_S0
FOR M26X PCIE_VDDR12

CONNECT TO +1.8V
FOR M52P,M54P,M56P
CONNECT TO +1.2V
C139
TC19
ST100U6D3VDM-5
C218
1 R153
2
0R0805-PAD
C156
C141
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C252
VGA_PCIE_VDDR12_1
VGA_VDDR3
C215
C246
N29
N28
N27
N26
N25
K23
C199
C658
PCIE_VDDR_12_10
PCIE_VDDR_12_11
PCIE_VDDR_12_12
PCIE_VDDR_12_13
PCIE_VDDR_12_14
SCD1U10V2KX-4GP
VSS_159
C214
C196
C194
PCIE_PVDD_12_1
PCIE_PVDD_12_2
PCIE_PVDD_12_3
PCIE_PVDD_12_4
SCD1U10V2KX-4GP
CORE GND
C250
C180
C209
C224
V23
N23
P23
U23
I/0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
C211
C203
VDDR1_1
VDDR1_2
VDDR1_3
VDDR1_4
VDDR1_5
VDDR1_6
VDDR1_7
VDDR1_8
VDDR1_9
VDDR1_10
VDDR1_11
VDDR1_12
VDDR1_13
VDDR1_14
VDDR1_15
VDDR1_16
VDDR1_17
VDDR1_18
VDDR1_20
VDDR1_21
VDDR1_22
VDDR1_23
VDDR1_24
VDDR1_25
VDDR1_26
VDDR1_27
VDDR1_28
VDDR1_29
VDDR1_30
VDDR1_31
VDDR1_32
VDDR1_33
VDDR1_34
VDDR1_35
VDDR1_36
VDDR1_37
VDDR1_38
VDDR1_39
VDDR1_40
VDDR1_41
VDDR1_42
VDDR1_43
VDDR1_45
VDDR1_46
Memory I/O
B1
H1
L1
P1
U1
Y1
AD7
AE8
AL1
A2
AM2
AD10
E8
H5
K10
M8
T10
E12
AC9
AF14
AD8
C5
F10
J3
L6
M6
P6
AA4
AG11
V3
AG16
R3
C6
C9
F6
H7
J6
C253
C1
J1
M1
R1
V1
AA1
A3
P9
J10
N9
P10
A9
Y10
P8
R9
Y9
J11
A21
M10
N10
Y8
J18
J19
K21
A12
H13
A15
J20
J13
K11
K19
A18
L23
K20
K24
L24
H19
A24
K13
J32
A30
C32
F32
L32
Memory
I/O
Clock
PCIE_PVSS
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
SCD1U10V2KX-4GP
W23
PCI-Express GND
PCIE_VSS_1
PCIE_VSS_2
PCIE_VSS_3
PCIE_VSS_4
PCIE_VSS_5
PCIE_VSS_6
PCIE_VSS_7
PCIE_VSS_8
PCIE_VSS_9
PCIE_VSS_10
PCIE_VSS_11
PCIE_VSS_12
PCIE_VSS_13
PCIE_VSS_14
PCIE_VSS_15
PCIE_VSS_16
PCIE_VSS_17
PCIE_VSS_18
PCIE_VSS_19
PCIE_VSS_20
PCIE_VSS_21
PCIE_VSS_22
PCIE_VSS_23
PCIE_VSS_24
PCIE_VSS_25
PCIE_VSS_26
PCIE_VSS_27
PCIE_VSS_28
PCIE_VSS_29
PCIE_VSS_30
PCIE_VSS_31
PCIE_VSS_32
PCIE_VSS_33
PCIE_VSS_34
PCIE_VSS_35
PCIE_VSS_36
PCIE_VSS_37
PCIE_VSS_38
PCIE_VSS_39
PCIE_VSS_40
PCIE_VSS_41
PCIE_VSS_42
PCIE_VSS_43
PCIE_VSS_44
PCIE_VSS_45
PCIE_VSS_46
PCIE_VSS_47
PCIE_VSS_48
PCIE_VSS_49
PCIE_VSS_50
PCIE_VSS_51
PCIE_VSS_52
PCIE_VSS_53
PCIE_VSS_54
PCIE_VSS_55
PCIE_VSS_56
PCIE_VSS_57
PCIE_VSS_58
PCIE_VSS_59
PCIE_VSS_60
PCIE_VSS_61
PCIE_VSS_62
PCIE_VSS_63
PCIE_VSS_64
PCIE_VSS_65
PCIE_VSS_66
PCIE_VSS_67
PCIE_VSS_68
PCIE_VSS_69
PCIE_VSS_70
PCIE_VSS_71
PCIE_VSS_72
PCIE_VSS_73
PCIE_VSS_74
PCIE_VSS_75
PCIE_VSS_76
PCIE_VSS_77
PCIE_VSS_78
PCIE_VSS_79
PCIE_VSS_80
PCIE_VSS_81
PCIE_VSS_82
AD16
AA6
P7
P5
M3
M9
L7
M7
AD17
AH11
A8
U7
C10
E9
F3
J9
N7
N3
Y5
AM13
AC10
Y6
U6
E5
AL13
A11
U8
U9
U10
R6
AD6
V6
AD14
AD13
D11
J12
K12
A13
F13
E13
F15
K16
J21
H16
T15
V17
C15
C4
U14
P15
A16
E16
G13
G16
P17
R16
R14
W16
C18
F16
W18
U18
AE16
AE17
A19
H32
F19
G19
N8
Y7
T19
V19
G21
C21
F21
AE14
AK16
U5
F22
F18
K30
C24
F24
M24
A25
D30
E25
G25
G20
G22
F27
E28
H21
C27
E32
H28
J30
K17
K27
M32
A22
C20
E19
H20
J24
M28
J28
J16
F30
L29
A31
B32
E30
AE15
AG23
AD9
AF16
AH10
AJ10
AD15
AH16
PART 5 OF 7
-1 Modify
SCD1U10V2KX-4GP
AH27
AC23
AL27
R23
P25
R25
T26
U26
W26
Y26
AB26
AC26
AD25
AE26
AF26
AD26
AG25
AH26
AC28
Y28
U28
P28
AH29
AF28
V29
AC29
W27
AB27
V26
AJ26
AJ32
AK29
P26
P29
R29
T29
U29
W29
Y29
AA29
AB29
AD29
AE29
AF29
AG29
AJ29
AK26
AK30
AG26
N30
R31
AF30
AC30
V31
P30
AA31
U30
AD31
AK32
AJ28
Y30
AJ30
AK31
AA23
AG31
N24
AB23
P24
R24
T24
U24
V24
W24
Y24
AC24
AH24
V25
AA25
R26
AA26
T27
AE27
VGA_PCIE_PVDD12
1D8V_S0
Part 6 of 7
SCD01U25V2KX-3GP
U70F
<Variant Name>
CONNECT THESE VDD25 PINS TO 2.5V FOR M52P,M54P,M56P

THESE VDD25 PINS ARE NO CONNECT FOR M26X
Wistron Corporation
Title
ATI M5X-P Power 4/4
Size
C
Document Number
Date:
Saturday, June 10, 2006
Rev
SA
LWG2
Sheet
1
45
of
52
Ideal Power Up Sequence
Real Power Up Sequence
VBBN
VBBN
VBBP
VBBP
VDDC
VDDC
MVDDC
PCIE_VDDR_12
MVDDC
PCIE_VDDR_12
1mS
PCIE_PVDD_12
PCIE_PVDD_12
VDD25
VDD25
VDDR1
VDDR1
<5mS
VDDR3
VDDR3
RESISTOR
Symbol name
Value
Rating
Tolerance
(J: 5%, F: 1%, D: 0.5%, B: 0.1 %)
0402=> 1/16W, 25V

0603 => 1/16W, 75V
0805 => 1/10W, 100V
Size
2=>0402, 3=>0603, 5=>0805,
6=>1206, 0=>1210
10KR3
10K Ohm
If no letter, it means J: 5%
1/16W, 75V
0603
33D3R5
33.3 Ohm
If no letter, it means J: 5%
1/10W, 100V
0805
1KR3F
1K Ohm
F: 1%
1/16W, 75V
0603
The naming rule is value + R + size + tolerance

For the value, it can be read by the number before R. (R means resistor)
For the tolerance, it can be read from the last letter.
For the rating, we don't show on the symbol name.
For the size, R2=>0402, R3=>0603, R5=>0805,....
General Guidelines:
BBN and BBP must ramp up before or at the same time as VDDC but not after.
VDDC and MVDDC must be ramped up first, followed by PCIE_VDDR_12, PCIE_PVDD12, VDD25, VDDR1 and
VDDR3 (and other I/O powers).
All powers must be ramped up within 5ms of each other (from the ramp of VDDC to 90% of VDDR3).
VDD25 can be ramped with VDDC or VDDR1 but it cannot be ramped later than VDDR1.
The power down is the opposite of the power on sequence: VDDR3/VDDR1 -> VDD25
->VDDC/MVDDC/BBN/BBP.
Due to the level shifter design in the memory I/Os, in order to avoid over-stressing the thin oxide transistors when
VDDR1 is powered on but VDDC is not, VDDC must ramp up before VDDR1. Similarly, VDDC must ramp up before
VDDR3. The level shifter design is a function of the transistor types used in 90nm technology and of the voltage level support.
The drawback of ramping up VDDC before the I/O voltages (such as VDDR1 and VDDR3) is that parasitic P/N junctions
are forward biased, thus creating a conduction path. These conduction paths will pump up VDDR1 (from the memory
IOs) and VDDR3 (from the GPIOs).
The real power up sequence will appear as follows:
Figure 2-2. Real Power Up Sequence
As long as MVDDC ramps up with VDDC, the pump voltage on VDDR1 should be all right since the DRAM spec will
not be violated.
CAPACITOR
Symbol name
Value
Tolerance
(J: +/-5, K: +/-10,
M: +/-20, Z: +80/-20)
Rating
( X5R / X7R < 80%,
Y5V/Y5U/Z5U < 1/3 )
Size
2=>0402, 3=>0603, 5=>0805,
6=>1206, 0=>1210
SCD1U10V2MX-1 0.1uF
M/X5R
10V
0402
SC10U6D3V5MX
10uF
M/X5R
6.3V
0805
SC2D2U16V5ZY
2.2uF
Z/Y5V
16V
0805
The naming rule is

Capacitor type + value + rating + size + tolerance + material
SCD1U10V2MX-1
SC=> SMT Ceremic, TC=> POS cap or SP cap
D1U => 0.1uF
10V => the voltage rating is 10V
2=> 0402, 3=>0603, 5=>0805
M=>tolerance J, K, M, Z
X=> X7R/X5R, Y=> Y5V
-1 => symbol version, nonsense to EE characteristic
<Variant Name>
Wistron Corporation
Title
ATI M5X-P POWER SEQUENCE

Size
A3
Document Number
Rev
LWG2
SA
Sheet
46
of
52
CHAN B DDR2 84BGA 32MX16 MEMORY

D
C192
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
C182
C188
C190
C185
SCD1U10V2KX-4GP
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
C186
C664
C189
1D8V_S0
DDR_VREF_S0
WEB0#
K3
WE
RASB0#
K7
RAS
CASB0#
L7
CAS
DQMB#2
DQMB#0
F3
B3
LDM
UDM
VDDL
VSSDL
R143
1KR2F-3-GP
RDQSB2
WDQSB2
F7
E8
LDQS
LDQS
RDQSB0
WDQSB0
B7
A8
UDQS
UDQS
VRAM_VREF1
J2
VREF
A2
E2
L1
R3
R7
R8
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8
(SSTL-1.8) VREF = .5*VDDQ
R144
1KR2F-3-GP C181
SCD1U10V2KX-4GP
J1
J7
ODT
1D8V_S0
K9
A1
E1
J9
M9
R1
1D8V_S0
R573
56R2J-4-GP
R575
56R2J-4-GP
C650
C183
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
SCD1U10V2KX-4GP
1D8V_S0
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
R579
1KR2F-3-GP
ODTB0
VDD1
VDD2
VDD3
VDD4
VDD5
VSS1
VSS2
VSS3
VSS4
VSS5
1
2
1
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
K8
J8
CK
CK
CKEB0
K2
CKE
CSB0_0#
L8
CS
WEB0#
K3
WE
RASB0#
K7
RAS
CASB0#
L7
CAS
DQMB#1
DQMB#3
F3
B3
LDM
UDM
ODTB0
K9
ODT
A3
E3
J3
N1
P9
SCD1U10V2KX-4GP
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDD1
VDD2
VDD3
VDD4
VDD5
A1
E1
J9
M9
R1
VDDL
VSSDL
RDQSB1
WDQSB1
F7
E8
LDQS
LDQS
RDQSB3
WDQSB3
B7
A8
UDQS
UDQS
VRAM_VREF2
J2
VREF
A2
E2
L1
R3
R7
R8
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8
R578
1KR2F-3-GP C653
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
J1
J7
MDB27
MDB28
MDB24
MDB31
MDB30
MDB25
MDB29
MDB26
MDB15
MDB9
MDB12
MDB8
MDB11
MDB13
MDB10
MDB14
44
44,48
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
VSS1
VSS2
VSS3
VSS4
VSS5
A3
E3
J3
N1
P9
44
44,48
RASB0#
RASB1#
44
44,48
CASB0#
CASB1#
44
44,48
WEB0#
WEB1#
44
44,48
CSB0_0#
CSB1_0#
44
44,48
CKEB0
CKEB1
RN22
M56P
8
7
6
5
RN93
M56P
8
7
6
5
RN92
M56P
8
7
6
5
256R2J-4-GP
256R2J-4-GP
256R2J-4-GP
ODTB0
ODTB1
R572 1
R82 1
256R2J-4-GP
256R2J-4-GP
RASB0#
RASB1#
R574 1
R83 1
256R2J-4-GP
256R2J-4-GP
CASB0#
CASB1#
R571 1
R81 1
256R2J-4-GP
256R2J-4-GP
WEB0#
WEB1#
R577 1
R555 1
256R2J-4-GP
256R2J-4-GP
CSB0_0#
CSB1_0#
R570 1
R84 1
256R2J-4-GP
256R2J-4-GP
CKEB0
CKEB1
R576 1
R86 1
256R2J-4-GP
256R2J-4-GP
1D8V_S0
FOR M56P AT DDR2 MEMORY SPEEDS ABOVE 350MHZ

MEMORY CONTROL SIGNALS WE,CAS,RAS,CS,CKE,ODT
AND MEMORY ADDRESS SIGNALS REQUIRE 55 OHM PULLUP
TO A VTT RAIL (50% OF VDDQ)
44
44
C184
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
ODTB0
ODTB1
CS
MAB12_14
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
L8
BA0
BA1
1
1
CSB0_0#
L2
L3
CLKB0#
CLKB0
CLKB0#
CLKB0
2
2
CKE
44
44
K2
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
CKEB0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
CLOSE TO MEM !!
CK
CK
B_BA0
B_BA1
K8
J8
CLKB0#
CLKB0
SC470P50V2KX-3GP
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
MDB7
MDB0
MDB5
MDB2
MDB3
MDB4
MDB1
MDB6
MDB23
MDB18
MDB20
MDB16
MDB17
MDB21
MDB19
MDB22
BC857_1
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
1
2
3
4
SRN56J-5-GP
MAB10
1
MAB9
2
MAB5
3
MAB0
4
SRN56J-5-GP
MAB4
1
MAB6
2
MAB8
3
MAB11
4
SRN56J-5-GP
B_BA0
R552 1
B_BA1
R551 1
MAB12_14
R550 1
U69
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
MAB12_14
BA0
BA1
44,48
L2
L3
B_BA0
B_BA1
44,48
44,48
MAB2
MAB7
MAB3
MAB1
C655
SC1U6D3V2KX-GP
U23
C
C578
SCD1U10V2KX-4GP
SC1U6D3V2KX-GP
C652
C662
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
C191
C663
C654
C577
1D8V_S0
CLKB0
CLKB0#
CLKB0
CLKB0#
SCD1U10V2KX-4GP
RDQSB[7..0]
44,48 RDQSB[7..0]
DQMB#[7..0]
44,48 DQMB#[7..0]
MDB[63..0]
44,48 MDB[63..0]
MAB[11..0]
44,48 MAB[11..0]
WDQSB[7..0]
44,48 WDQSB[7..0]
<Variant Name>
HY5PS561621A-25GP
72.55616.C0U
HY5PS561621A-25GP
72.55616.C0U
Wistron Corporation
72.55616.C0U IC VRAM HY5PS561621AFP-25 FBGA(16M*16, 350Mhz) Hynix-128M

72.18256.B0U IC VRAM HYB18T256161AFL25 BGA (16M*16, 350Mhz) Infineon-128M
72.18512.A0U IC VRAM HYB18T512161BF-25 BGA (32M*16, 400Mhz) Infineon-256M
Title
VRAM 1/2
Size
A3
Document Number
Rev
SA
LWG2
Sheet
1
47
of
52
SC10U6D3V5MX-3GP
2
1
SC10U6D3V5MX-3GP
C651
1
2
1
C84
1
2
1
2
1
1
2
1
1
1
2
1
C90
SCD1U10V2KX-4GP
2
1
C85
SCD1U10V2KX-4GP
SC1U6D3V2KX-GP
SCD1U10V2KX-4GP
SC1U6D3V2KX-GP
C633
C86
SCD1U10V2KX-4GP
C632
C89
SCD1U10V2KX-4GP
C634
C187
SC1U6D3V2KX-GP
C88
SCD1U10V2KX-4GP
C630
SC1U6D3V2KX-GP
SC1KP16V2KX-GP
C193
SC1U6D3V2KX-GP
C635
C661
SC1U6D3V2KX-GP
1D8V_S0
C92
SC1KP16V2KX-GP
1D8V_S0
-1 Modify
U21
K8
J8
CK
CK
CKE
L8
CS
WEB1#
K3
WE
CAS
K9
LDM
UDM
VDDL
VSSDL
ODT
RDQSB4
WDQSB4
VRAM_VREF3
R89
1KR2F-3-GP C87
SCD1U10V2KX-4GP
C83
B7
A8
UDQS
UDQS
J2
VREF
A2
E2
L1
R3
R7
R8
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
VSS1
VSS2
VSS3
VSS4
VSS5
A3
E3
J3
N1
P9
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
K2
CKE
CSB1_0#
L8
CS
WEB1#
K3
WE
RASB1#
K7
RAS
CASB1#
L7
CAS
F3
B3
LDM
UDM
SCD1U10V2KX-4GP
1D8V_S0
C631
DQMB#6
DQMB#7
ODTB1
R87
1KR2F-3-GP
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
ODT
RDQSB6
WDQSB6
F7
E8
LDQS
LDQS
RDQSB7
WDQSB7
B7
A8
UDQS
UDQS
J2
VREF
A2
E2
L1
R3
R7
R8
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8
MDB59
MDB60
MDB58
MDB62
MDB63
MDB56
MDB61
MDB57
MDB51
MDB53
MDB48
MDB55
MDB52
MDB49
MDB54
MDB50
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
VRAM_VREF4
R85
1KR2F-3-GP C82
SCD1U10V2KX-4GP
HY5PS561621A-25GP
72.55616.C0U
44,47
RASB1#
44,47
CASB1#
44,47
WEB1#
44,47
CSB1_0#
44,47
CKEB1
44,47
ODTB1
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
VDD1
VDD2
VDD3
VDD4
VDD5
A1
E1
J9
M9
R1
44,47 DQMB#[7..0]
J1
J7
44,47 WDQSB[7..0]
VDDL
VSSDL
K9
LDQS
LDQS
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
CKEB1
F7
E8
1
1
R90
1KR2F-3-GP
J1
J7
MAB12_14
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
CK
CK
SC470P50V2KX-3GP
RDQSB5
WDQSB5
F3
B3
L7
BA0
BA1
K8
J8
R556
56R2J-4-GP
RAS
CASB1#
1D8V_S0
R554
56R2J-4-GP
CLOSE TO MEM !!
K7
ODTB1
1D8V_S0
BC856_1
RASB1#
DQMB#5
DQMB#4
VDD1
VDD2
VDD3
VDD4
VDD5
A1
E1
J9
M9
R1
CLKB1#
CLKB1
L2
L3
CLKB1#
CLKB1
2
2
CSB1_0#
44
44
K2
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
CKEB1
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
B_BA0
B_BA1
44
44
1D8V_S0
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
VSS1
VSS2
VSS3
VSS4
VSS5
A3
E3
J3
N1
P9
CASB1#
WEB1#
CSB1_0#
CKEB1
ODTB1
CLKB1
CLKB1#
CLKB1
CLKB1#
RDQSB[7..0]
44,47 RDQSB[7..0]
DQMB#[7..0]
MDB[63..0]
44,47 MDB[63..0]
MAB[11..0]
44,47 MAB[11..0]
C629
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
RASB1#
WDQSB[7..0]
CLKB1#
CLKB1
U68
SCD1U10V2KX-4GP
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
MDB39
MDB32
MDB38
MDB34
MDB33
MDB37
MDB35
MDB36
MDB44
MDB43
MDB47
MDB40
MDB41
MDB46
MDB42
MDB45
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
MAB12_14
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
1
1
BA0
BA1
MAB12_14
L2
L3
44,47
B_BA0
B_BA1
B_BA0
B_BA1
44,47
44,47
C628
SC1U10V3KX-3GP
<Variant Name>
Wistron Corporation
HY5PS561621A-25GP
72.55616.C0U
Title
VRAM 2/2
Size
A3
Document Number
Rev
SA
LWG2
Sheet
1
48
of
52
VGA_CORE_S0
VGA_CORE_PWR
G2
G1
DCBATOUT
DCBATOUT_5234
GAP-CLOSE-PWR
G62
2
GAP-CLOSE-PWR 1
GAP-CLOSE-PWR
G60
2
GAP-CLOSE-PWR
2
GAP-CLOSE-PWR
2
G3
G11
1
D
4
3
2
1
Id=11A
Qg=9.8nC
Rdson=19.6~24mohm
2
5
6
7
8
U63
FDS6690A-3-GP
C23
GAP-CLOSE-PWR
2
GAP-CLOSE-PWR
2
GAP-CLOSE-PWR
2
GAP-CLOSE-PWR
2
IND-2D2UH-45-GP-U
5V_S0
AO4430-1-GP
C21
SCD1U25V3KX-GP
4
3
2
1
SC
Id=18A
Qg=48nC
Rdson=6.2~7.5mohm
SC
442R2F-GP
R33
655R3F-GP
C555
SCD1U25V3ZY-1GP
TC18
SE330U2VDM-L2GP
Non-M52 M52P
Panasonic V Size 330uF 2V

ESR=9mohm, Iripple=3.0A
USD:0.250 (Q3/05)
R14
DUMMY-R3
PWM Mode:
FPWM (High)=>Fixed PWM Mode.
FPWM (Low)=>Hysteretic Mode.
R11
C42
R13
10KR2J-3-GP
TP67
TPAD30
300KHz
74.05234.A7G
U64
5234_HDRV
5234_LDRV
14
10
M52:1.0V
M54:1.1V
M56: 1.1V
Iomax=17A
OCP>28A
VGA_CORE_PWR
Vosetting=1.0809V
L2
HDRV
LDRV
R36
1K2R3F-GP
1
2
1
2
97K6R3F-GP
1
1
2
R35
2KR2F-3-GP
5234_VSEN
SC2200P50V2KX-2GP
VSEN
VOUT
VIN
VCC
FAN5234MTCX-1GP
GAP-CLOSE-PWR
2
5234_ISEN
5234_SW
12
13
ISNS
SW
9
8
SCD01U16V2KX-3GP
PGND
AGND
S
S
S
G
C44
R34
1
C41
SCD22U16V3ZY-GP
GAP-CLOSE-PWR
Vout Setting:
0.9V/Rlow=(Vout-0.9V)/Rhigh
FPWM
BOOT
SS
ILIM
EN
PGOOD
GAP-CLOSE-PWR
2
G66
SCD1U25V3KX-GP
5
6
7
8
6
5
1
11
5234_VIN
G65
D
D
D
D
R12 2
1
0R0603-PAD
GAP-CLOSE-PWR
G5
2
G8
SC
5234_SS
5234_ILIM
5234_EN
G7
U8
16
15
7
4
3
GAP-CLOSE-PWR
G4
2
G6
C556
1
2
2
1
SSM5818SLPT-GP
C22
SC10U25V6KX-1GP
G64
GAP-CLOSE-PWR
C47
SCD1U16V2ZY-2GP
5234_BOOT
10KR2J-3-GP DCBATOUT_5234
GAP-CLOSE-PWR
G13
2
GAP-CLOSE-PWR
G63
2
DCBATOUT_5234
C46
R499
DUMMY-R2
1 R498
GAP-CLOSE-PWR
G14
2
SC10U25V6KX-1GP
PM_SLP_S3#
GAP-CLOSE-PWR
G12
2
S
S
S
G
16,18,30,33,38,40
GAP-CLOSE-PWR
G9
2
D
D
D
D
C45
SC10U10V5ZY-1GP
D5
5V_S0
SC10U25V6KX-1GP
FAN5234 FOR VGA_Core
5V_S5
GAP-CLOSE-PWR
G10
2
VGA_CORE_S0
G61
ATI M5x VGA Core
Non-M52
Q35
B
CHT2222APT-GPNon-M52
R485
1KR2J-1-GP
R483
100KR2J-1-GP
Non-M52
<Variant Name>
VGA Ver. Normal PowerPlay

M52
A12
1.0
0.95/1.0
M54
A12
1.1
0.95/0.95
1.2
0.95
1.1
0.95/0.95
M56
B24
Wistron Corporation
Title
VGA CORE 1D1V

Size
A3
Document Number
Rev
LWG2

5
GPIO_PWRCNTL 43
Non-M52
1 E
Non-M52 C566
2N7002-7F-GP
1 R497
2
20KR2J-L2-GP
G
S
Non-M52
R31
M52 : 0.95V, but don't card it.(1.0V)

don't mount Q9
R35 + R31 set Vout to 0.9994V.
R31 = 4K02R2, R33 = 655R3.
R481
10KR2J-3-GP
Q9
SC4D7U10V5ZY-3GP
M54/M56 : 1.1 / 0.95 V

High :R35 + R32 set Vout to 0.9503V.
Low : R11 set Vout to 1.0989V.
R32 = 5K9R2, R11 = 442R2.
M52P
4K02R2F-GP
2
POWERPLAY:
M56 : 1.2 / 0.95 V
high (3.3V) = set lower core voltage (e.g. VDDC = 0.95V)
low (0V) = set higher core voltage (e.g. VDDC = 1.2V)
High :R35 + R32 set Vout to 0.949875V.
R32
5K9R2F-GP
Low : R33 set Vout to 1.19925V.
Non-M52
R32 = 10KR2, R33 = 665R3F
3D3V_S0
Rilim=(11.2/Iilim)*((100+Rsense)/Rdson)
SA
Sheet
1
49
of
52
EMI CAP
5V_S0
BT+
DCBATOUT
EC48
EC45
SCD1U25V3ZY-1GP
SCD1U25V3ZY-1GP
EC46
EC43
EC44
SCD1U25V3ZY-1GP
SCD1U25V3ZY-1GP
SCD1U25V3ZY-1GP
EC47
EC40
SCD1U25V3ZY-1GP
SCD1U25V3ZY-1GP
EC39
SCD1U25V3ZY-1GP
EC38
EC37
SCD1U25V3ZY-1GP
EC22
11
TSAHCT125PW-GP
SCD1U25V3ZY-1GP
12
SCD1U25V3ZY-1GP
1
8
TSAHCT125PW-GP
U59D
13
14
U59C
10
14
5V_S0
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
EC64
EC65
SCD1U16V2ZY-2GP
EC57
EC59
EC60
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
EC62
EC63
1
2
1
2
EC58
SCD1U16V2ZY-2GP
K2
SPRING-U3
EC41
SCD1U16V2ZY-2GP
SPRING-U3
EC66
SCD1U16V2ZY-2GP
SPRING-U3
EC61
SCD1U16V2ZY-2GP
K4
EC42
SCD1U16V2ZY-2GP
K3
SCD1U16V2ZY-2GP
K1
SCD1U16V2ZY-2GP
EC67
SCD1U16V2ZY-2GP
3D3V_S0
SPRING-23-GP
DIMMY-SB
VGA_CORE_S0
3D3V_S0
34.40U07.001
MINIC MINIC
H34
H27
H37
HOLE
H30
H38
HOLE
H28
1
2
EC71
EC72
1
2
EC70
SCD1U16V2ZY-2GP
IO Bracket
H31
SCD1U16V2ZY-2GP
IO Bracket
H26
SCD1U16V2ZY-2GP
FOR MDC
H24
EC69
EC73
BOTTOM SIDE:
SCD1U16V2ZY-2GP
34.39S07.001
SCD1U16V2ZY-2GP
34.40U07.001
34.40U07.001
H29
34.4A902.001
34.4A903.001
34.4A904.001
34.4f901.001
34.4A906.001
SB ADDS EMI
SW2
34.4A907.001
SW3
1
SPRING-7
SPRING-7
H10
HOLE
H16
HOLE
H20
HOLE
H4
HOLE
H2
HOLE
H1
HOLE
H6
HOLE
H9
HOLE
H3
HOLE
H11
HOLE
H14
HOLE
H8
HOLE
H5
HOLE
H18
HOLE
H15
HOLE
SW4
1
K5
SPRING-7
1
SPRING-23-GP
H17
H7
H12
H13
H32
H21
HOLE
H22
HOLE
H36
HOLE
H19
HOLE
H33
HOLE
H35
HOLE
34.39S07.002
DIMMY
<Variant Name>
Wistron Corporation
Title
SPRING & BOSS

Size
A3
Document Number
Rev
LWG2

A
SA
Sheet
E
50
of
52
CLOSE TO PHY PINS
DY
4401E R795
CHDTC124EU-1GP
84.00124.F1K
1KR2J-1-GP
EEDATA_PXE
EECLK_PXE
E12
E11
3 MDI1+_M
4 MDI1-_M
SRN49D9F-GP
2
1
2
1
3D3V_LAN_S5
LAN_ACT_LED# 22,23
100M_LED# 22,23
10M_LED# 22,23
LAN_X0
LAN_X1
C381
XTAL-25MHZ-70GP
82.30020.581
4401E
D
C751
C753
1
2
C729
Wistron Corporation
1 R297
2
200R2J-L1-GP
X4
1
2
4401E
C727
C749
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C750
C754
4401E
C756
4401E
2
10KR2J-3-GP
1 R635
2DY
4K7R2J-2-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B4
B7
B12
E2
F6
F7
F8
F9
G5
G6
G7
G8
G9
G10
H5
H6
H7
H8
H9
H10
J6
J7
J8
J9
K2
N1
N9
P9
4401E
1 R634
MDI0+_M
MDI0-_M
MDI1+_M
MDI1-_M
B
SCD1U16V2ZY-2GP
2
VAUXPRSNT
2
L6
A10
K13
J12
VAUX_PRSNT
TEST_MODE
RDAC
VREF
N8
N10
P8
P10
4401E 4401E 4401E 4401E 4401E 4401E 4401E
GPIO0
GPIO1
G12
H13
XTALI
XTALO
EXT_POR
SCD1U10V2KX-4GP
J14 1D8V_LAN_S5
2
1
L14
3D3V_LAN_S5
K14
REG18OUT
REGSUP18
REGSUP18
H14 XTALVDD
XTALVDD
PLLVDD
A14 BIASVDD
G14
PLLVDD
F12
F13
VESD1
VESD2
VESD3
EPHY_AVDD
EPHY_AVDD
P1
G2
A1
B3
A7
C5
E1
E4
G1
K3
L4
P2
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
VDDIO_PCI
D11
G11
K12
LINK_LED10
LINK_LED100
ACT_LED
COL_LED
3D3V_LAN_S5
<Variant Name>
ICH_PME# 16
23
23
23
23
A
RSVD#N8
RSVD#N10
RSVD#P8
RSVD#P10
N6
P6
R1
A8
A9
A13
B9
C10
C12
D5
D8
D9
D10
D13
D14
E13
E14
F4
F11
F14
G13
H11
J13
K9
K10
L5
L7
L8
L11
L12
L13
M6
M8
M9
M10
M11
M12
M13
M14
N11
N14
P11
P13
P14
DC#A8
DC#A9
DC#A13
DC#B9
DC#C10
DC#C12
DC#D5
DC#D8
DC#D9
DC#D10
DC#D13
DC#D14
DC#E13
DC#E14
DC#F4
DC#F11
DC#F14
DC#G13
DC#H11
DC#J13
DC#K9
DC#K10
DC#L5
DC#L7
DC#L8
DC#L11
DC#L12
DC#L13
DC#M6
DC#M8
DC#M9
DC#M10
DC#M11
DC#M12
DC#M13
DC#M14
DC#N11
DC#N14
DC#P11
DC#P13
DC#P14
SC27P50V2JN-2-GP
3 OUT
R2
IN
4401E 4401E
1D8V_LAN_S5
SC27P50V2JN-2-GP
2
1
P12
N12
L9
71.04401.C0U
A11
B11
B10
A12
GND 2
PME#_LAN
4401E
SPROM_DIN
SPROM_DOUT
SPROM_CLK
SPROM_CS
BCM4401EKFBG-GP
4401E
Q14
C351
U36
NC#N6
NC#P6
N13
J11
K11
L10
1
2
R292 0R2J-2-GP
PME#_LAN
FRAME#
IRDY#
TRDY#
PERR#
SERR#
REQ
GNT#
DEVSEL#
IDSEL
PAR
PCI_RST#
INTA#
PCI_CLK
CLKRUN#
STOP#
PME#
SPROMDIN
SPROMDOUT
SPROMCLK
SPROMCS
3D3V_LAN_S5
LAN_IDSEL
F2
F1
G3
J2
A2
C3
J3
H3
A4
J1
C2
H2
A3
H4
H1
A6
C350
4401E
IDSEL:AD23
INTA-->:INT_PIRQH#
GNT:PCI_GNT#2
REQ:PCI_REQ#2
CBE_0#
CBE_1#
CBE_2#
CBE_3#
4401E
RN51
R290 11K24R2F-GP
2
BCM4401E
TRD0+
TRD0TRD1+
TRD1-
16,25 PCI_FRAME#
16,25
PCI_IRDY#
16,25
PCI_TRDY#
16,25
PCI_PERR#
16,25 PCI_SERR#
16 PCI_REQ#2
16 PCI_GNT#2
16,25 PCI_DEVSEL#
PCI_AD23
R310 1 100R2F-L1-GP-U
2
4401E 16,24 PCI_PAR
16,25,27 PCIRST1#
16 INT_PIRQH#
3 PCLK_LAN
16,25,30 PM_CLKRUN#
16,25 PCI_STOP#
PCI_C/BE#0 M4
L3
PCI_C/BE#2 F3
C4
C377
Broadcom LAN
B13
B14
C13
C14
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
VDDIO
VDDIO
VDDIO
B8
E5
E6
E7
E8
E9
E10
F5
F10
G4
J4
J5
J10
K4
K5
K6
K7
K8
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
16,24
16,24
16,24
16,24
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
TCK
TDI
TDO
TMS
TRST#
4401E
M7
N7
P7
P5
N5
M5
P4
N4
P3
N3
N2
M1
M2
M3
L1
L2
K1
E3
D1
D2
D3
C1
B1
B2
D4
A5
B5
B6
C6
C7
C8
C9
D7
H12
D6
C11
D12
DY
C470
SCD1U10V2KX-4GP
C444
PLLVDD
C424
1 L15
2
0R0603-PAD
4401E
2
1
SCD47U10V3ZY-GP
SCD1U10V2KX-4GP
Place PLLVDD/AVDDL
CKT as close to chip as
possible
DY
C471
AVDDL
SCD47U10V3ZY-GP
1 L14
2
0R0603-PAD
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
SCD1U10V2KX-4GP
4401E
BIASVDD
4401E
4K7R2J-2-GP
C728
1D8V_LAN_S5
3
1 R649
2
0R0603-PAD
3D3V_S5
1 L7
2
0R0603-PAD
4401E
R288
4401E
1
2
SCD1U10V2KX-4GP
C349
4401E
3D3V_LAN_S5
4401E
BIASVDD
1D8V_LAN_S5
16,24,25 PCI_AD[0..31]
C270
AVDDL
AT93C46-10SU-1GP
3D3V_LAN_S5
DY
4401E
VCC
DC
ORG
GND
SCD1U10V2KX-4GP
CS
SK
DI
DO
R201
10KR2J-3-GP
8
7
6
5
1
2
3
4
SPROMCS
SPROMCLK
SPROMDOUT
SPROMDIN
C355
U26
RN50
4401E
4
4401E
SCD1U16V2ZY-2GP
2
3D3V_LAN_S5
1 L9
2XTALVDD
0R0603-PAD
C378
3
4
3D3V_LAN_S5
SRN49D9F-GP
MDI0+_M
MDI0-_M

Title
C404
4401E Size
A3
BCM4401E
Document Number
Rev
LWG2
SA
Sheet
E
51
of
52
SA change to SB version change notes

D
1. Page 16 _ C773,C807,C811 for OC# cap -->Dimmy

3. Page 18 _ modify Q36/Q37 mirror
4. Page 50 _ Adds EMI Spring SW2,SW3, SW4 & K5 -- >34.49U26.001
5. Page 16 _ Adds R47 for MDC detect function -- > MDC_KILL# to SB GPIO24
6. Page 21 _ Adds R850,R844 for USB pull low
7. Page 21 _ Adds R25,R26,R38 for USB control to SB GPIO 25/26/27 pin (if use KBC GPIO then Dimmy)
8. Page 21 _ Adds R39,R40,R46 for USB control to KBC GPIO P-25/26/27 pin (if use SB GPIO then Dimmy)
9. Page 21 _ Add D44 for MDC_KILL#
C
10. Page 50 _ Adds EMI 5 pcs 0.1uF cap

11. Page 19 _ Adds TP118,TP119 tesr pad for test
12. Page 19 _ mirror L12,L13
13. Page 50 _ K4 Dimmy -- > BOM change
14. Page 14 _ L17,L18,L19 change to 47 Ohm -- >68.00084.271
15. Page 23 _ EC2 change to 78.1022N.24L
16. Page 15 _ adds R553 for ACZ_RST# signal to MDC & ALC883
one signal ACZ_RST_ALC# to audio to page 28
B
one signal ACZ_RST_MDC# to modem detect page 21
17. Page 21 _ adds R69 for D44 pull-hi-->63.10334.1DL

18. Page 35/37/38/40/49_Power Open Gap change to Power Close Gap
19. Page 31_ Wireless-BT & NOVO-BT pin change
20. Page 50_ K5 Dimmy
Title
<Title>
Size
B
Date:
5
Document Number
<Doc>
Monday, June 12, 2006
Rev
<RevCode>
Sheet
1
52
of
52

LWG2-D Block Diagram (Discrete) Mobile CPU

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LWG2-D Block Diagram (Discrete) Mobile CPU

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A

Project code: 91.4Q801.001

PCI Express x16

Ver. : B0, 71.ICH7M.A0U / QK65

ATI M54 DC/DC

Date: Wednesday, June 21, 2006

ICH7M Integrated Pull-up

ICH7-M EDS 17837

EE_DIN, EE_DOUT, GNT[3:0], GPIO[25],

954305D 27Mhz/LCDCLK Spread

Calistoga Strapping Signals and

FSB Frequency Select

ICH7 internal 20K pull-ups

ICH7 internal 11.5K pull-downs

ICH7 internal 20K pull-downs

ICH7 internal 15K pull-downs

ICH7 internal 15K pull-up

DD[15:0], DIOW#, DIOR#, DREQ,

ICH7M Functional Strap Definitions

Allows entrance to XOR Chain testing when TP3

Sets bit0 of RPC.PC(Config Registers:Offset 224h)

This signal should not be pull high.

This signal should not be pull low.

This signal should not be pull low.

Sampled low:Top-Block Swap mode(inverts A16 for

Boot BIOS Destination

Controllable via Boot BIOS Destination bit

FSB Dynamic ODT

0 = Dynamic ODT Disabled

Global R-comp Disable

0 = All R-comp Disable

DMI Lane Reversal

0 = Normal operation (Default):lane

0 = Only SDVO or PCIE x1 is

This signal should not be pull high.

This signal should not be pull low.

Requires an external pull-up resistor.

XOR Chain Selection.

This signal should not be pull low.

If sampled high, the system is strapped to the

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

INT -> PIRQ

IORDY, DA[2:0], DCS1#,

0 = Reverse Lanes,15->0,14->1 ect..

ICH7 internal 100K pull-down

ICH7M IDE Integrated Series

PCI Express Graphics

XOR Chain Entrance.

Enables integrated VccSus1_05 VRM when

This signal should not be pull low unless using

Date: Saturday, June 10, 2006

PCLK_FWH & PCLK_PCM

Dummy when use UMA

Clock Generator IDT CVT125PAG

Date: Saturday, June 10, 2006

2nd source: 62.10053.401

All place within 2" to CPU

Date: Saturday, June 10, 2006

VCCSENSE and VSSSENSE lines

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Date: Saturday, June 10, 2006

Place them near to the chip ( < 0.5")