D.S.

D PRACTICAL FILE

SUBMITTED TO:-

SUBMITTED BY:-

MRS. PARUL MAM

rahul

CLASS:- CSE-B(6TH SEM) ROLL NO.:- 41083 UNI. RL.NO.:-1136617468

EXPERIMENT 01
AIM:- Write a VHDL code different gates (a). AND GATE (BEHAVIOURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity and_gates is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end and_gates; architecture Behavioral of and_gates is begin process(a,b) begin c <= a and b ; end process; end Behavioral;

(DATA FLOW)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity and_g is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end and_g;

architecture dataflow of and_g is begin c<=a and b; end dataflow;

(STUCTURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity and_g1 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end and_g1; Architecture structural of and_g1 is component andgate is port(p,q:in std_logic; r: out std_logic); end component; begin A1:andgate port map(a,b,c); end structural;

RTL SCHEMATIC:-

SIMULATION:-

(b). OR GATE

(BEHAVIOURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity or_gate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end or_gate; architecture Behavioral of or_gate is begin process(a,b) begin c<= a or b; end process; end Behavioral;

(DATA FLOW)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity or_gate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end or_gate;

architecture dataflow of or_gate is begin c<= a or b; end dataflow;

(STUCTURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity or_gate1 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end or_gate1; architecture structural of or_gate1 is component orgate port(x,y:in std_logic; z: out std_logic); end component; begin A1: orgate port map(a,b,c); end stuctural;

RTL SCHEMATIC:-

SIMULATION:-

(c). NOT GATE (BEHAVIOURAL)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity not12 is Port ( a : in STD_LOGIC;

b : out STD_LOGIC); end not12; architecture Behavioral of not12 is begin process(a) begin b<=not a; end process; end Behavioral;

(DATA FLOW)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity not_gate is Port ( a : in STD_LOGIC; b : out STD_LOGIC); end not_gate; architecture dataflow of not_gate is begin b<=(not a); end dataflow;

(STUCTURAL):library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity not_gate1 is Port ( a : in STD_LOGIC; b : out STD_LOGIC); end not_gate1; architecture stuctural of not_gate1 is component not_gate2 is port(p: in std_logic; q: out std_logic); end component; begin X1:not_gate2 port map(a,b); end stuctural;

RTL SCHEMATIC:-

SIMULATION:-

(d). NOR GATE (BEHAVIOURAL)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity nor12 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end nor12; architecture Behavioral of nor12 is begin process(a,b) begin c<=a nor b;

end process; end Behavioral;

(DATA FLOW)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity nor_gate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end nor_gate; architecture dataflow of nor_gate is

begin c<=a nor b; end dataflow;

(STUCTURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity nor_gate1 is Port ( a : in STD_LOGIC; b : in STD_LOGIC;

c : out STD_LOGIC); end nor_gate1; architecture structural of nor_gate1 is component norgate is port(x,y:in std_logic;z: out std_logic); end component; begin A1:norgate port map(a,b,c); end structural;

RTL SCHEMATIC:-

SIMULATION:-

(e). NAND GATE (BEHAVIOURAL)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity nand12 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end nand12; architecture Behavioral of nand12 is begin process(a,b) begin c<=a nand b; end process;

end Behavioral;

(DATA FLOW)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity nand_gate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end nand_gate; architecture dataflow of nand_gate is begin c<=a nand b; end dataflow;

(STRUCTURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity nand_gate2 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end nand_gate2; architecture structural of nand_gate2 is

component nandgate is port(x,y: in std_logic;z:out std_logic); end component; begin A1:nandgate port map(a,b,c); end structural;

RTL SCHEMATIC:-

SIMULATION:-

(f). XOR GATE (BEHAVIOURAL)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity xor12 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end xor12; architecture Behavioral of xor12 is begin process(a,b) begin c<=a xor b; end process; end Behavioral;

(DATA FLOW)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity xor_gate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC);

end xor_gate; architecture dataflow of xor_gate is begin c<=a xor b; end dataflow;

(STUCTURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity xor_gate1 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end xor_gate1; architecture structural of xor_gate1 is component xorgate is port(x,y:in std_logic;z:out std_logic); end component; begin A1:xorgate port map(a,b,c) end structural;

RTL SCHEMATIC:-

SIMULATION:-

(g).XNOR GATE (BEHAVOIURAL)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity xnor12 is Port ( a : in STD_LOGIC; b : in STD_LOGIC;

c : out STD_LOGIC); end xnor12; architecture Behavioral of xnor12 is begin process(a,b) begin c<=a xnor b; end process; end Behavioral;

(DATA FLOW)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity xnor_gate is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end xnor_gate; architecture dataflow of xnor_gate is begin c<=a xnor b; end dataflow;

(STUCTURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity xnor_gate1 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end xnor_gate1; architecture structural of xnor_gate1 is component xnorgate is port(x,y:in std_logic;z:out std_logic); end component; begin A1:xnorgate port map(a,b,c); end structural;

RTL SCHEMATIC:-

SIMULATION:-

EXPERIMENT:-02 AIM:-Design a adder using VHDL language.

(a).HALF ADDER (BEHAVIOURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity half_add is Port ( a : in STD_LOGIC; b : in STD_LOGIC; s : out STD_LOGIC; c : out STD_LOGIC); end half_add; architecture Behavioral of half_add is begin process(a,b) beggin s<=a xor b; c<=a and b; end process; end Behavioral;

(STUCTURAL)
library IEEE;

use IEEE.STD_LOGIC_1164.ALL; entity ha_add13 is Port ( x : in STD_LOGIC; y : in STD_LOGIC; S : out STD_LOGIC; C : out STD_LOGIC); end ha_add13; architecture Structural of ha_add13 is component and12 port(a,b:in STD_LOGIC;c:out STD_LOGIC); end component; component xor12 port(a,b:in STD_LOGIC;c:out STD_LOGIC); end component; begin X1:and12 port map(x,y,C); X2:xor12 port map(x,y,S); end Structural;

(DATAFLOW)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity half_adder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC;

d : out STD_LOGIC); end half_adder; architecture Dataflow of half_adder is begin c <= a xor b; d<= a and b; end Dataflow;

RTL SCHEMATIC:-

SIMULATION:-

(b). FULL ADDER (BEHAVIOURAL)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity full_add is Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : in STD_LOGIC; s : out STD_LOGIC; c : out STD_LOGIC); end full_add; architecture Behavioral of full_add is begin process(a,b) begin s<=x xor y xor z; c<=(x and y) or (y and z) or (z and x); end process; end Behavioral;

(STRUCTURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity full_adder is

Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; c_in : out STD_LOGIC; S : out STD_LOGIC); end full_adder; architecture structral of full_adder is component xorgate12 Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : out STD_LOGIC; end component; component andgate12 Port ( l : in STD_LOGIC; m : in STD_LOGIC; n : out STD_LOGIC); end component; component orgate12 Port ( l1 : in STD_LOGIC; l2 : in STD_LOGIC; l3 : in STD_LOGIC; l4 : out STD_LOGIC); end component; signal e,f,g,h:std_logic;

begin a1:xorgate12 port map(a,b,e); a2:xorgate12 port map(e,c,s); a3:andgate12 port map(a,b,f); a4:andgate12 port map(b,c,g); a5:andgate12 port map(c,a,h); a6:orgate12 port map(f,g,h,c_in); end structral;

(DATAFLOW) library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity full_add is Port ( x : in STD_LOGIC; y : in STD_LOGIC; z : in STD_LOGIC; s : out STD_LOGIC; c : out STD_LOGIC); end full_add; architecture Dataflow of full_add is begin s<=x xor y xor z; c<=(x and y) or (y and z) or (z and x); end Dataflow;

RTL SHEMATIC:-

SIMULATION:-

EXPERIMENT:-03
AIM:- Write a VHDL code for SUBTRACTORS. (a).HALF SUBTRACTOR (BEHAVIOURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity hs_sub12 is Port ( x : in STD_LOGIC; y : in STD_LOGIC; s : out STD_LOGIC; b : out STD_LOGIC); end hs_sub12; architecture Behavioral of hs_sub12 is begin process(x,y) begin s <= x xor y; b <= not x and y; end process; end Behavioral;

(STUCTURAL)
library IEEE;

use IEEE.STD_LOGIC_1164.ALL; entity hs_sub13 is Port ( x : in STD_LOGIC; y : in STD_LOGIC; R : out STD_LOGIC; B : out STD_LOGIC); end hs_sub13; architecture Structural of hs_sub13 is component and12 port(a,b:in STD_LOGIC;c:out STD_LOGIC); end component; component not12 port(a:in STD_LOGIC;b:out STD_LOGIC); end component; component xor12 port(a,b:in STD_LOGIC;c:out STD_LOGIC); end component; signal f,g:STD_LOGIC; begin X1:not12 port map(x,f); X2:and12 port map(f,y,B); X3:xor12 port map(x,y,R); end Structural;

(DATAFLOW)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity hs_sub12 is Port ( x : in STD_LOGIC; y : in STD_LOGIC; s : out STD_LOGIC; b : out STD_LOGIC); end hs_sub12; architecture Dataflow of hs_sub12 is begin s <= x xor y; b <= not x and y; end Dataflow;

RTL SCHEMATIC:-

SIMULATION:-

(b). FULL SUBTRACTOR (BEHAVIOURAL)

library IEEE use IEEE.STD_LOGIC_1164.ALL; entity full_substractor is Port ( a : in STD_LOGIC; b : in STD_LOGIC; bin : in STD_LOGIC; diff : out STD_LOGIC; bout : out STD_LOGIC); end full_substractor; architecture Behavioral of full_substractor is begin process(a,b,bin) begin diff<= (a xor b xor bin); bout<= ((b and bin) or (not a and (b xor bin))); end process; end Behavioral;

(DATAFLOW)
library IEEE use IEEE.STD_LOGIC_1164.ALL; entity full_substractor is Port ( a : in STD_LOGIC; b : in STD_LOGIC; bin : in STD_LOGIC; diff : out STD_LOGIC; bout : out STD_LOGIC); end full_substractor; architecture Dataflow of full_substractor is begin diff<= (a xor b xor bin); bout<= ((b and bin) or (not a and (b xor bin))); end Dataflow;

(STUCTURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity fullstrucsub is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; diff : out STD_LOGIC; borrow : out STD_LOGIC); end fullstrucsub; architecture Stucural of fullstrucsub is component xor1_gate port(l,m,n: in std_logic; o:out std_logic); end component;

component xor_gate port(g,h: in std_logic; i:out std_logic); end component; component and_gate port (x,y : in std_logic; z:out std_logic); end component; component or_gate port (s,t : in std_logic; u: out std_logic); end component; component not_gate port(p :in std_logic; q: out std_logic); end component; signal s1,s2,s3,f1: std_logic; begin A1:xor1_gate port map(a,b,c,diff); A2:xor_gate port map(a,b,s3); A3:and_gate port map (a,b,s1); A4:not_gate port map(c,s2); A5:and_gate port map (s2,s3,f1); A6:or_gate port map(s1,f1,borrow); end Stuctural;

RTL SCHEMATICS:-

SIMULTAION:-

EXPERIMENT:-04

AIM:- Write a VHDL code for 4:1 mux and 1:4 demux. (a).4:1 MUX (BEHAVIOURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity mux12 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; s : in STD_LOGIC_vector(1 downto 0); y : out STD_LOGIC); end mux12; architecture Behavioral of mux12 is begin process(a,b,c,d,s) begin case s is when "00"=> y <=a; when "01"=> y <=b; when "10"=> y <=c; when others=> y<=d; end case; end process;

end Behavioral;

(DATA FLOW)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity mux1 is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; s0 : in STD_LOGIC; s1 : in STD_LOGIC; y : out STD_LOGIC); end mux1; architecture dataflow of mux1 is begin y<=(a and(not s1)and(not s0)) or (b and (not s1) and s0) or (c and s1 and (not s0)) or (d and s1 and s0); end dataflow;

(STUCTURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity muxstruc is Port ( i : in STD_LOGIC_VECTOR (3 downto 0);

s : in STD_LOGIC_VECTOR (1 downto 0); y : out STD_LOGIC); end muxstruc; architecture Stuctural of muxstruc is component and_g port ( l,m,n : in std_logic; o:out std_logic); end component; component or_gate port (q,t,u,v: in std_logic; w:out std_logic); end component; component not_g port (a:in std_logic; b: out std_logic); end component; signal f1,f2,f3,f4,f5,f6: std_logic; begin A1:not_g port map(s(1),f1); A2:not_g port map(s(0),f2); A3:and_g port map(i(0),f1,f2,f3); A4:and_g port map(i(1),f1,s(0),f4); A5:and_g port map(i(2),s(1),f2,f5); A6:and_g port map(i(3),s(1),s(0),f6); A7:or_gate port map (f3,f4,f5,f6,y); end Stucural;

RTL SCHEMATIC:-

SIMULATION:-

(b).1:4 DEMUX (BEHAVOIURAL)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity demux is Port ( a : in STD_LOGIC; s : in STD_LOGIC_VECTOR (01 downto 0); b : out STD_LOGIC_VECTOR (03 downto 0)); end demux; architecture Behavioral of demux is begin process(s) begin if(a='0') then b<="0000"; else case s is when"00"=>b<="0001"; when"01"=>b<="0010"; when"10"=>b<="0100"; when others=>b<="1000"; end case; end if; end process; end Behavioral;

(STUCTURAL)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity demuxstruct is Port ( d : in STD_LOGIC; s : in STD_LOGIC_VECTOR (1 downto 0); i : out STD_LOGIC_VECTOR (3 downto 0)); end demuxstruct; architecture Stuctural of demuxstruct is component notg port (t: in std_logic; u:out std_logic); end component; component andg port (a,b,c: in std_logic; e:out std_logic); end component; signal f1,f2: std_logic; begin a1: notg port map (s(0),f1); a2: notg port map (s(1),f2); a3: andg port map (d,f1,f2,i(0)); a4: andg port map (d,f1,s(1),i(1)); a5: andg port map (d,s(0),f2,i(2)); a6: andg port map (d,s(0),s(1),i(3)); end Stuctural;

(DATA FLOW)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity demux1 is Port ( s0 : in STD_LOGIC; s1 : in STD_LOGIC;

y : in STD_LOGIC; a : out STD_LOGIC; b : out STD_LOGIC; c : out STD_LOGIC; d : out STD_LOGIC); end demux1; architecture dataflow of demux1 is begin a<=y and(not s0)and(not s1); b<=y and(not s1)and(s0); c<=y and(not s0)and(s1); d<=(y and s0) and s1; end dataflow;

RTL SCHEMATIC:-

SIMULATION:-

PROGRAM NO-5 AIM:- Write a VHDL code for encoder and decoder.

ENCODER:(BEHAVIOURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity encod12 is Port ( i : in bit_vector(0 to 7); s : out bit_vector(0 to 2)); end encod12; architecture Behavioral of encod12 is begin process(i) begin if i="10000000" then s<="000"; elsif i="01000000" then s<="001"; elsif i="00100000" then s<="010"; elsif i="00010000" then s<="011"; elsif i="00001000" then s<="100"; elsif i="00000100" then s<="101";

elsif i="00000010" then s<="110"; else s<="111"; end if; end process; end Behavioral;

(STUCTURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity encoderstruc is Port ( I : in STD_LOGIC_VECTOR (7 downto 0); Y : out STD_LOGIC_VECTOR (2 downto 0); en: in std_logic); end encoderstruc; architecture structural of encoderstruc is component or_gate port (a,b,c,d,e: in std_logic; f:out std_logic); end component; begin a1:or_gate port map (i(4),i(5),i(6),i(7),en,y(0)); a2:or_gate port map (i(2),i(3),i(6),i(7),en,y(1)); a3:or_gate port map (i(1),i(3),i(5),i(7),en,y(2)); end structural;

(DATA FLOW)
library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity encoder is Port ( i0,i1,i2,i3,i4,i5,i6 : in STD_LOGIC; Y0,y1,y2 : out STD_LOGIC); end encoder; architecture dataflow of encoder is begin y0<=(i0 or i2) or (i4 or i6); y1<=(i0 or i1) or (i4 or i5); y2<=(i0 or i1) or (i2 or i3); end dataflow;

RTL SCHEMATICS:-

SIMULATION:-

(b).DECODER
(BEHAVIOURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decod12 is Port ( s : in bit_vector(0 to 2); i : out bit_vector(0 to 7)); end decod12; architecture Behavioral of decod12 is begin process(s) begin case s is when "111"=>i<="10000000"; when "011"=>i<="01000000";

when "101"=>i<="00100000"; when "001"=>i<="00010000"; when "110"=>i<="00001000"; when "010"=>i<="00000100"; when "100"=>i<="00000010"; when others=>i<="00000001"; end case; end process; end Behavioral;

(STUCTURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decoderstruc is Port ( y : in STD_LOGIC_VECTOR (2 downto 0); i : out STD_LOGIC_VECTOR (7 downto 0); en : in STD_LOGIC); end decoderstruc; architecture Stuctural of decoderstruc is component not_gate port (a:in std_logic; b: out std_logic); end component; component and_gate port (c,d,e,f:in std_logic; g: out std_logic); end component; signal f1,f2,f3: std_logic;

begin A1:not_gate port map(y(2),f1); A2:not_gate port map(y(1),f2); A3:not_gate port map(y(0),f3); A4:and_gate port map(y(2),y(1),y(0),en,i(0)); A5:and_gate port map(y(2),y(1),f3,en,i(1)); A6:and_gate port map(y(2),f2,y(0),en,i(2)); A7:and_gate port map(y(2),f2,f3,en,i(3)); A8:and_gate port map(f1,y(1),y(0),en,i(4)); A9:and_gate port map(f1,y(1),f3,en,i(5)); A10:and_gate port map(f1,f2,y(0),en,i(6)); A11:and_gate port map(f1,f2,f3,en,i(7)); end Stuctural;

(DATA FLOW)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decoder is Port ( s0,s1,s2: in STD_LOGIC; Y0,y1,y2,y3,y4,y5,y6,y7 : out STD_LOGIC); end decoder; architecture dataflow of decoder is begin y0<=(s0 and s1) and s2; y1<= (not s0) and s1 and s2; y2<= s0 and (not s1) and s2; y3<=(not s0) and (not s1) and s2; y4<= s0 and s1 and (not s2);

y5<=(not s0) and s1 and (not s2); y6<= s0 and (not s1) and (not s2); y7<=(not s0) and (not s1) and (not s2); end dataflow;

RTL SCHEMATIC:-

SIMULATION:-

PROGRAM NO -6 AIM:- Write a VHDL code for convert fron binary to grey code.
(BEHAVIOURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity binarytogray is Port ( b : in STD_LOGIC_vector(2 downto 0); g : out STD_LOGIC_vector (2 downto 0)); end binarytogray; architecture Behavioral of binarytogray is begin process(b) begin case b is when "000"=>g<="000"; when"001"=>g<="001"; when"010"=>g<="011"; when"011"=>g<="010"; when"100"=>g<="110"; when"101"=>g<="111"; when"110"=>g<="101"; when others=>g<="100"; end case;

end process; end Behavioral;

(DATA FLOW)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity binarytogray is Port ( w : in STD_LOGIC; x : in STD_LOGIC; y : in STD_LOGIC; z : in STD_LOGIC; a : out STD_LOGIC; b : out STD_LOGIC; c : out STD_LOGIC; d : out STD_LOGIC); end binarytogray; architecture dataflow of binarytogray is begin a<= (w and not x) or (not y); b<= (not w and x) or (w and not x); c<=(w and x and not y) or (not w and not x and y); d<=(not w and not y and z) or (not w and y and not z); end dataflow;

(STRUCTURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity structbinarytogray is Port ( w : in STD_LOGIC; x : in STD_LOGIC; y : in STD_LOGIC; z : in STD_LOGIC; a : out STD_LOGIC; b : out STD_LOGIC; c : out STD_LOGIC; d : out STD_LOGIC); end structbinarytogray; architecture structural of structbinarytogray is component not12 is port(a1:in STD_LOGIC ; o1:out STD_LOGIC); end component; component and12 is port(a2,a3:in STD_LOGIC ; o2:out STD_LOGIC); end component; component and22 is port(a4,a5,a6:in STD_LOGIC ; o3:out STD_LOGIC); end component; component or12 is

port(a7,a8:in STD_LOGIC ; o4:out STD_LOGIC); end component; signal p,q,r,s,t,l,m,n,o,u,v:std_logic; begin g1:not12 port map(w,p); g2:not12 port map(x,q); g3:not12 port map(y,r); g4:not12 port map(z,s); g5:and12 port map(w,q,l); g6:and12 port map(p,x,m); g7:and12 port map(q,w,n); g8:and22 port map(w,x,r,o); g9:and22 port map(p,q,y,t); g10:and22 port map(z,p,r,u); g11:and22 port map(p,y,s,v); g12:or12 port map(l,r,a); g13:or12 port map(m,n,b); g14:or12 port map(o,t,c); g15:or12 port map(u,v,d); end structural;

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SIMULATION:-

PROGRAM NO-7 AIM:- Write a VHDL code for convert fron BCD to 7-segment display.
(BEHAVOIURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity bcdtosevensegment is Port ( a : in STD_LOGIC_vector(3 downto 0); b : out STD_LOGIC_vector(6 downto 0)); end bcdtosevensegment; architecture Behavioral of bcdtosevensegment is begin process(a) begin case a is when"0000"=>b<="1111110"; when"0001"=>b<="0110000"; when"0010"=>b<="1101101"; when"0011"=>b<="1111001"; when"0100"=>b<="0110011"; when"0101"=>b<="1011011"; when"0110"=>b<="1011111"; when"0111"=>b<="1110000"; when"1000"=>b<="1111111";

when others=>b<="1111011"; end case; end process; end Behavioral;

(DATAFLOW)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity seven12 is Port ( w : in STD_LOGIC; x : in STD_LOGIC; y : in STD_LOGIC; z : in STD_LOGIC; a : out STD_LOGIC; b : out STD_LOGIC; c : out STD_LOGIC; d : out STD_LOGIC; e : out STD_LOGIC; f : out STD_LOGIC; g : out STD_LOGIC); end seven12; architecture Dataflow of seven12 is begin a<=((x and not w) or (not x and not y and not z) or (y and not w)); b<=((not w and not x) or (not w and not y and not z) or (z and y and not w) or (not x and not y and not z)); c<=((x and not w) or (not x and not y and not z) or (z and not w) or (not y and not w)); d<=((not x and not y and not z) or (x and not w and not y and z) or (y and not w and not x) or (w and not y and not z)); e<=((not x and not y and not z) or ( not w and y and not z)); f<=((not x and not y and not z) or (not w and x and not y) or (not w and x and not z)); g<=((w and not x and not y and not z ) or ( x and not y and not w) or (y and not w and not x) or (y and not z and not w)); end Dataflow;

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PROGRAM NO-8 AIM:- Write a VHDL code for 1-bit comparator.

(BEHAVOIURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity comparator is Port ( a : in STD_LOGIC; b : in STD_LOGIC; agb : out STD_LOGIC; aeb : out STD_LOGIC; alb : out STD_LOGIC); end comparator; architecture Behavioral of comparator is begin process (a,b) begin if(a>b) then agb<='1'; aeb<='0'; alb<='0'; else if(a=b) then agb<='0'; aeb<='1'; alb<='0'; else if(a<b) then agb<='0'; aeb<='0'; alb<='1'; end if; end if; end if; end process;

end Behavioral;

(STUCTURAL)
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity comparator_grey is Port ( a : in STD_LOGIC; b : in STD_LOGIC; agb : out STD_LOGIC; aeb : out STD_LOGIC; alb : out STD_LOGIC); end comparator_grey; architecture Stuctural of comparator_grey is component not_gate port (a:in std_logic; b: out std_logic); end component; component and_gate port (c,d:in std_logic; e: out std_logic); end component; component xor_gate port (f,g:in std_logic; h: out std_logic); end component; signal f1,f2: std_logic; begin A1:not_gate port map (a,f1); A2:not_gate port map (b,f2); A3:and_gate port map (f1,b,alb); A4:and_gate port map (f2,a,agb); A5:xor_gate port map (a,b,aeb); end Stuctural;

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SIMULATION:-