CPLD Vs.

FPGA Positioning Presentation

LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 1

Agenda

Architecture Descriptions
CPLD FPGA Advantages / Disadvantages

Gate Counting Common Terms Positioning

LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 2

Basic Definitions

CPLD
Course Grained Architecture Best for Wide, Fast Function Processing Relatively Small Designs

FPGA
Fine Grained Architecture Best for Narrow / Pipelined Functions Large Designs
4

LUT

LUT

LUT

LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 3

FPGA Architecture

Input Bus Generic Logic Block

Input Bus Generic Logic Block

Input Bus Generic Logic Block Boundary Scan Interface

TDI TDO

VCCIO I/O 287 I/O 286 I/O 285 I/O 284 I/O 267 I/O 266 I/O 265 I/O 264

I/O 72 I/O 73 I/O 74 I/O 75 I/O 92 I/O 93 I/O 94 I/O 95

Generic Logic Block

Input Bus

I/O 263 I/O 262 I/O 261 I/O 260 I/O 243 I/O 242 I/O 241 I/O 240 I/O 239 I/O 238 I/O 237 I/O 236 I/O 219 I/O 218 I/O 217 I/O 216 Global Routing Pool (GRP)

I/O 96 I/O 97 I/O 98 I/O 99 I/O 116 I/O 117 I/O 118 I/O 119 I/O 120 I/O 121 I/O 122 I/O 123 I/O 140 I/O 141 I/O 142 I/O 143

Generic Logic Block Generic Logic Block

Input Bus Input Bus

Generic Logic Block Input Bus SET/RESET

Generic Logic Block Input Bus

Generic Logic Block Input Bus

CPLD

FPGA

LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 4

High Density Logic Overview FPGA HDPLD or CPLD

A B

Field Programmable Gate Arrays

Small Logic Building Blocks Register Intensive Distributed Interconnect

High-Density or Complex PLDs

Large Logic Building Blocks PLD-Like Architectures Centralized Interconnect

Slower pin to pin performance, due to lots of routing, but pipelining can help Good at Narrow Gating Funcitions Datapath Random Logic

Fast Predictable Performance Good at Wide Gating Functions State Machines Counters

FPGAs and CPLDs Can Compliment One Another In the Same Design!
LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 5

Performance
LE
4

FPGA - 4 input Look Up Table (LUT)

Two possible implementations Pipelining (preferred) High internal frequency achievable higher latency Two levels of logic Lower latency, but high frequencies not achievable
LE
4

LUT

LUT

LE
4

LUT

Row Interconnect

CPLDs have wide fan in

Local Interconnect

Single level allows high frequency AND low latency Very small functions burn logic

4 4

LUT LUT

LUT

Macrocell
68

LUT

Logic

LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 6

Predictability and Delay

Row / column design of FPGA

Design changes potentially changes routing Routing changes result in timing changes Larger delta in I/O to I/O delay Design for worst case delay

Centralized routing of CPLDs

Consistent Routing through GRP All GRP lines equally loaded Re-route has minimal effect on timing Wide inputs results in fewer paths Higher speed Better predictability

LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 7

FPGA Architecture

FPGAs use fine grain logic blocks

Many of these logic blocks are used to implement logic functions due to fine grain blocks, 16 LBs for 16-Bit adder

FPGAs Work Best With One - hot encoding for state functions
Fine Grain / Abundance of Registers makes One-Hot a good fit

Register Logic Register Logic Register

LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 8

FPGA EPROM

Most FPGAs are volatile SRAM

FPGA
EPROM or P

Devices are reprogrammed on power-up

Program can be stored in companion, EPROM next to FPGAs Device can be programmed with P via Flash programming Logic is not available when power is initially applied

LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 9

FPGA Vs CPLD Logic Element

FPGA Has a Basic, Fine Grain Logic Element

Typical FPGA has 4 Inputs and 8 Product Terms Per Logic Element Wide Designs Speed Limitation Can be Overcome with Pipelining

CPLD Has Complex Logic Element

5KVG Family has 68 Inputs and 32 Product Terms Per Logic Element The CPLD Has Less Registers but uses these registers more efficiently Simple Designs Use up the Registers and Logic Elements are Under Utilized
CPLD vs FPGA Input Ratio = 17 : 1

CPLD vs FPGA Product Term Ratio = 4 : 1

FPGA CPLD

Logic Element 8 PTs

68

Logic Element 32 PTs

LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 10

Technology Comparisons

Feature Reprogrammability In-System Programmable Program Time Erase Time Fast

E2CMOS Yes Yes Fast Slow

Flash Yes Yes Med. Fast

SRAM Yes Yes

(Volatile)

Antifuse NO NO Slow

Fast N/A (OTP)

Testability
External Hardware

Full
No

Full
No

Full
EPROM

Limited
Pgmr

LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 11

Gate Counting

LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 12

CPLD Vs. FPGA Fitting

Number of PLD Gates or Registers Doesnt Tell the Entire Story, The Application Does
Even among equivalent product types, Gate count is specsmanship, the only real way to see if a design will fit or fit better is to run it!

Applications Needing High Speed and Predictability Should Use CPLD Large Register Intensive Logic Applications Should Use FPGA Most Designs Have a Mixture of Qualities that Could Fit Either, So Both CPLD and FPGA Should Be Considered

LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 13

A Gate Is a Gate Is a Gate

FPGA and CPLD Both Build Gates Out of Transistors
The Basic CMOS Gates Are the Same in Both Architectures
Inverter NAND NOR

Example NAND
VCC

A F B F B

LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 14

CPLD Gate Count Vs FPGA Gate Count

It is Difficult to Compare Apples to Apples What Is an Equivalent PLD Gate?
A Simple PLD Gate Is Considered 2-input AND

How Many Simple PLD Gates to Build an 8-input AND?

Seven

FPGA Vendors Have Different Standards for Gate Counts

A Higher Percentage of Gates Are Used for Interconnect in FPGA and some Vendors count Memory in Total Gate Count

The First Order of Importance Is to Have Enough Registers to Compete, Not Fight Over Gate Counts

The Only Way To Know if a Design Fits is to FIT IT!!!

LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 15

Terms

LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 16

FPGA Terms
FPGA - Field Programmable Gate Array SRAM - Static RAM
Program stored in outside EPROM, intelligent controller or through JTAG Port, FPGAs must be reprogrammed on every power-up

Configuration EPROM
External hardware used to hold FPGA programming file

ICR - In-Circuit Reconfigurability Anti-fuse - One-Time Programmable (OTP)

(Quicklogic and Actel)

Interconnect - Basic Routing element

FPGAs rely on a Fine Grain routing structure

LUT - Look-Up Table

4-input SRAM based look-up table produces the output of any 4 input function

LE/CLB - Logic Element

Smallest logic unit. 4 input Look-Up Table, Carry/cascade chains, register and register control signals
LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 17

FPGA Terms
LAB - Logic Array Block (Altera)
Consists of 8 LEs and associated control signals and routing

EAB - Embedded Array Block (Altera)

High level building block, includes Ram and registers

One Hot Encoding

When single registers (bits) are used to represent states instead of the common binary method Example: 20 state-state machine One Hot: 20 registers (bits) Binary: 5 registers (bits)

Pipeline
Putting functions in an assembly line format. Small portions done quickly allows a high clock speed and results at short intervals. The drawback is results take longer to get from input to output (latency)

Register

Register

Register

Register

No Clk Delay
LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 18

1 Clk Delay

2 Clk Delay

3 Clk Delay

FPGA Terms
SoC
System on a Chip

MPI
Microprocessor Interface

EBR
Embedded Block RAM

PLC
Programmable Logic Cell

PIO
Programmable Input/Output Cells

CIB
Common Interface Block

PFU
Programmable Function Unit

SLIC
Decoder / PAL like logic

LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 19

Positioning

LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 20

CPLDProduct Positioning

FPGA/FPSC Mach
ASSP

FPGA/FPSC
ASIC

Memory

ROM

GDX 5K GDX
MicroProcessor

Chip Set

5K

SPEED

DENSITY

LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 21

CPLD Product Positioning

FPGA / FPSC
Data Path Logic consolidation DSP Functions

5KVG
Wide Decode Buss Control (16-32-64 bit Buses) In One Level Complex High Speed Control Fast Muxing

Density

Mach/Mach4K
High Speed Decode

Small High speed Control

ASIC Fixes PCI Arbitration

Speed
LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 22

CPU Requirements
Large

Datapath
FPSCs

Fast Control / Datapath

Density

FPGAs

5K Family

Wide Datapath Switching

M4K Family

Fast address decode and Control logic Bus Arbitration

CPU Fast Slow

Small

LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 23

Propagation Delay

Some CPLDs Can Do Large Designs

5KVG Mach4K

FPGA

CPLD

Some Small Designs Fit Better in Large CPLDs, Some Designs Require FPGA features

LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 24

Summary
Understand the Design
Dont Assume the Best Hardware is an FPGA or CPLD

CPLDs Are Best Suited for:

Wide Designs Speed Critical, Low Latency, Low Skew Relatively Small Hot-Plugable

FPGAs Are Best Suited for:

Large Register Intensive Designs Narrow Gating, Pipeline-able

Fit the Design to Determine the Size in Our Devices

LATTICE SEMICONDUCTOR CORPORATION CPLD VS FPGA February, 02 25