00000054 <__ctors_end>:

54:
11 24
56:
1f be
58:
cf e5
5a:
d8 e0
5c:
de bf
5e:
cd bf

eor
out
ldi
ldi
out
out

r1, r1
0x3f, r1
r28, 0x5F
r29, 0x08
0x3e, r29
0x3d, r28

;
;
;
;
;

63
95
8
62
61

00000060 <__do_copy_data>:
60:
11 e0
62:
a0 e6
64:
b0 e0
66:
ec e4
68:
f0 e1
6a:
02 c0
art>

ldi
ldi
ldi
ldi
ldi
rjmp

r17,
r26,
r27,
r30,
r31,
.+4

;
;
;
;
;
;

1
96
0
76
16
0x70 <.do_copy_data_st

0x01
0x60
0x00
0x4C
0x10

0000006c <.do_copy_data_loop>:
6c:
05 90
lpm
6e:
0d 92
st

r0, Z+
X+, r0

00000070 <.do_copy_data_start>:
70:
a0 38
cpi
72:
b1 07
cpc
74:
d9 f7
brne
op>

r26, 0x80
r27, r17
.-10

; 128

00000076 <__do_clear_bss>:
76:
11 e0
78:
a0 e8
7a:
b1 e0
7c:
01 c0
art>

r17, 0x01
r26, 0x80
r27, 0x01
.+2

;
;
;
;

ldi
ldi
ldi
rjmp

0000007e <.do_clear_bss_loop>:
7e:
1d 92
st
00000080 <.do_clear_bss_start>:
80:
a2 3c
82:
b1 07
84:
e1 f7
op>
86:
0e 94 f0 00
8a:
0c 94 24 08
0000008e <__bad_interrupt>:
8e:
0c 94 00 00

; 0x6c <.do_copy_data_lo

1
128
1
0x80 <.do_clear_bss_st

X+, r1

cpi
cpc
brne

r26, 0xC2
r27, r17
.-8

; 194

call
jmp

0x1e0 ; 0x1e0 <main>

0x1048 ; 0x1048 <_exit>

jmp

; 0x7e <.do_clear_bss_lo

; 0x0 <__vectors>

00000092 <int0_init>:
}
void int0_init( void )
{
MCUCR |= (1<<ISC01);
92:
85 b7
94:
82 60
96:
85 bf

//falling edge
in
r24, 0x35
ori
r24, 0x02
out
0x35, r24

; 53
; 2
; 53

GICR |= (1<<INT0);
98:
8b b7
9a:
80 64
9c:
8b bf

//enable INT0
in
r24, 0x3b
ori
r24, 0x40
out
0x3b, r24

; 59
; 64
; 59

}
9e:

08 95

ret

000000a0 <getPulseWidth>:
uint16_t getPulseWidth()
{
a0:
80 e0
a2:
90 e0
a4:
a0 e0
a6:
b0 e0
a8:
0b c0
20>
uint32_t i,result;

ldi
ldi
ldi
ldi
rjmp

//Wait for the rising edge

for(i=0;i<600000;i++)
aa:
01 96
adiw
ac:
a1 1d
adc
ae:
b1 1d
adc
b0:
80 3c
cpi
b2:
27 e2
ldi
b4:
92 07
cpc
b6:
29 e0
ldi
b8:
a2 07
cpc
ba:
20 e0
ldi
bc:
b2 07
cpc
be:
b9 f1
breq

r24,
r25,
r26,
r27,
.+22

0x00
0x00
0x00
0x00

r24, 0x01
r26, r1
r27, r1
r24, 0xC0
r18, 0x27
r25, r18
r18, 0x09
r26, r18
r18, 0x00
r27, r18
.+110

;
;
;
;
;

0
0
0
0
0xc0 <getPulseWidth+0x

; 1
; 192
; 39
; 9
; 0
; 0x12e <getPulseWidth+0

x8e>
{
c0:
c2:

if(!(US_PIN & (1<<US_POS))) continue; else break;

c8 9b
sbis
0x19, 0 ; 25
f3 cf
rjmp
.-26
; 0xaa <getPulseWidth+0x

a>
return 0xffff; //Indicates time out
//High Edge Found
//Setup Timer1
TCCR1A=0X00;
c4:
1f bc
TCCR1B=(1<<CS11);
c6:
82 e0
c8:
8e bd
TCNT1=0x00;
ca:
1d bc
cc:
1c bc
ce:
20 e0
d0:
30 e0
d2:
40 e0
d4:
50 e0
d6:
11 c0

out
0x2f, r1
//Prescaler = Fcpu/8
ldi
r24, 0x02
out
0x2e, r24
//Init counter
out
0x2d, r1
out
0x2c, r1
ldi
r18, 0x00
ldi
r19, 0x00
ldi
r20, 0x00
ldi
r21, 0x00
rjmp
.+34

5a>
//Now wait for the falling edge
for(i=0;i<600000;i++)
{

; 47
; 2
; 46
;
;
;
;
;
;
;

45
44
0
0
0
0
0xfa <getPulseWidth+0x

d8:
da:
dc:
de:
e0:

if(US_PIN & (1<<US_POS))

{
if(TCNT1 > 60000) break; else continue;
8c b5
in
r24, 0x2c
; 44
9d b5
in
r25, 0x2d
; 45
81 56
subi
r24, 0x61
; 97
9a 4e
sbci
r25, 0xEA
; 234
70 f4
brcc
.+28
; 0xfe <getPulseWidth+0x

5e>
TCCR1A=0X00;
TCCR1B=(1<<CS11);
TCNT1=0x00;

//Prescaler = Fcpu/8
//Init counter

//Now wait for the falling edge

for(i=0;i<600000;i++)
e2:
2f 5f
subi
e4:
3f 4f
sbci
e6:
4f 4f
sbci
e8:
5f 4f
sbci
ea:
20 3c
cpi
ec:
87 e2
ldi
ee:
38 07
cpc
f0:
89 e0
ldi
f2:
48 07
cpc
f4:
80 e0
ldi
f6:
58 07
cpc
f8:
d1 f0
breq

r18,
r19,
r20,
r21,
r18,
r24,
r19,
r24,
r20,
r24,
r21,
.+52

0xFF
0xFF
0xFF
0xFF
0xC0
0x27
r24
0x09
r24
0x00
r24

;
;
;
;
;
;

255
255
255
255
192
39

; 9
; 0
; 0x12e <getPulseWidth+0

x8e>
{
fa:
fc:

if(US_PIN & (1<<US_POS))

c8 99
sbic
0x19, 0 ; 25
ed cf
rjmp
.-38

; 0xd8 <getPulseWidth+0x

38>
if(i==600000)
return 0xffff; //Indicates time out
//Falling edge found
result=TCNT1;
fe:
8c b5
100:
9d b5
102:
a0 e0
104:
b0 e0

in
in
ldi
ldi

r24,
r25,
r26,
r27,

//Stop Timer
TCCR1B=0x00;
106:
1e bc

out

0x2e, r1

; 46

if(result > 60000)

108:
81 36
10a:
2a ee
10c:
92 07
10e:
20 e0
110:
a2 07
112:
20 e0
114:
b2 07
116:
38 f4

cpi
ldi
cpc
ldi
cpc
ldi
cpc
brcc

r24,
r18,
r25,
r18,
r26,
r18,
r27,
.+14

; 97
; 234

x86>
return 0xfffe; //No obstacle
else

0x2c
0x2d
0x00
0x00

0x61
0xEA
r18
0x00
r18
0x00
r18

;
;
;
;

44
45
0
0

; 0
; 0
; 0x126 <getPulseWidth+0

118:
11a:
11c:
11e:
120:

return (result>>1);
b6 95
lsr
a7 95
ror
97 95
ror
87 95
ror
9c 01
movw

r27
r26
r25
r24
r18, r24

}
122:
c9 01
124:
08 95
result=TCNT1;

movw
ret

r24, r18

//Stop Timer
TCCR1B=0x00;
if(result > 60000)
126:
2e ef
ldi
r18, 0xFE
128:
3f ef
ldi
r19, 0xFF
return 0xfffe; //No obstacle
else
return (result>>1);

; 254
; 255

}
12a:
c9 01
12c:
08 95
TCCR1B=0x00;

movw
ret

r24, r18

if(result > 60000)

return 0xfffe; //No obstacle
else
return (result>>1);
12e:
2f ef
ldi
r18, 0xFF
130:
3f ef
ldi
r19, 0xFF

; 255
; 255

}
132:
134:

c9 01
08 95

movw
ret

00000136 <Wait1>:
milliseconds can be achieved.
*/
void
_delay_loop_2(uint16_t __count)
{
__asm__ volatile (
136:
20 e0
ldi
138:
30 e0
ldi
13a:
c9 01
movw
13c:
01 97
sbiw
13e:
f1 f7
brne
140:
fc cf
rjmp

r24, r18

r18,
r19,
r24,
r24,
.-4
.-8

0x00
0x00
r18
0x01

; 0
; 0

r18,
r20,
r21,
r24,

0x00
0x00
0x00
r20

; 0
; 0
; 0

; 1
; 0x13c <Wait1+0x6>
; 0x13a <Wait1+0x4>

00000142 <Wait>:
for(i=0;i<1000;i++)
_delay_loop_2(0);
}
void Wait()
{
142:
144:
146:
148:

20
40
50
ca

e0
e0
e0
01

ldi
ldi
ldi
movw

14a:
01 97
sbiw
14c:
f1 f7
brne
uint8_t i;
for(i=0;i<50;i++)
14e:
2f 5f
subi
150:
22 33
cpi
152:
d1 f7
brne
_delay_loop_2(0);

r24, 0x01
.-4

; 1
; 0x14a <Wait+0x8>

r18, 0xFF
r18, 0x32
.-12

; 255
; 50
; 0x148 <Wait+0x6>

}
154:

08 95

ret

00000156 <__vector_1>:
#define US_NO_OBSTACLE 0xfffe

ISR( INT0_vect )
{
156:
1f 92
push
158:
0f 92
push
15a:
0f b6
in
15c:
0f 92
push
15e:
11 24
eor
160:
2f 93
push
162:
3f 93
push
164:
4f 93
push
166:
5f 93
push
168:
6f 93
push
16a:
7f 93
push
16c:
8f 93
push
16e:
9f 93
push
170:
af 93
push
172:
bf 93
push
174:
ef 93
push
176:
ff 93
push
// Int_flag = Int_flag + 1;
UWriteString("6000");
178:
80 e6
ldi
17a:
90 e0
ldi
17c:
0e 94 25 02
call
PORTC |= (1 << 0); // Set PORTC bit
180:
a8 9a
sbi
PORTC |= (1 << 2); // Set PORTC bit
182:
aa 9a
sbi
184:
20 e0
ldi
186:
40 e0
ldi
188:
50 e0
ldi
18a:
ca 01
movw
18c:
01 97
sbiw
18e:
f1 f7
brne
>
}
void Wait()
{
uint8_t i;
for(i=0;i<50;i++)
190:
2f 5f
192:
22 33
194:
d1 f7

subi
cpi
brne

r1
r0
r0, 0x3f
r0
r1, r1
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r30
r31

; 63

r24, 0x60
; 96
r25, 0x00
; 0
0x44a ; 0x44a <UWriteString>
2 high
0x15, 0 ; 21
2 high
0x15, 2 ; 21
r18, 0x00
; 0
r20, 0x00
; 0
r21, 0x00
; 0
r24, r20
r24, 0x01
; 1
.-4
; 0x18c <__vector_1+0x36

r18, 0xFF
r18, 0x32
.-12

; 255
; 50
; 0x18a <__vector_1+0x34

>
// Int_flag = Int_flag + 1;
UWriteString("6000");
PORTC |= (1 << 0); // Set PORTC bit
PORTC |= (1 << 2); // Set PORTC bit
Wait();
PORTC |= (1 << 1); // Set PORTC bit
196:
a9 9a
sbi
198:
20 e0
ldi
19a:
40 e0
ldi
19c:
50 e0
ldi
19e:
ca 01
movw
1a0:
01 97
sbiw
1a2:
f1 f7
brne

2 high
2 high
2 high
0x15, 1 ; 21
r18, 0x00
r20, 0x00
r21, 0x00
r24, r20
r24, 0x01
.-4

; 0
; 0
; 0
; 1
; 0x1a0 <__vector_1+0x4a

>
}
void Wait()
{
uint8_t i;
for(i=0;i<50;i++)
1a4:
2f 5f
1a6:
22 33
1a8:
d1 f7
>
PORTC |= (1 << 0); // Set
PORTC |= (1 << 2); // Set
Wait();
PORTC |= (1 << 1); // Set
Wait();
PORTC &= ~(1 <<1); // Set
1aa:
a9 98
1ac:
20 e0
1ae:
40 e0
1b0:
50 e0
1b2:
ca 01
1b4:
01 97
1b6:
f1 f7
>
}

subi
cpi
brne

r18, 0xFF
r18, 0x32
.-12

PORTC bit 2 high

PORTC bit 2 high
PORTC bit 2 high
PORTC bit
cbi
ldi
ldi
ldi
movw
sbiw
brne

void Wait()
{
uint8_t i;
for(i=0;i<50;i++)
1b8:
2f 5f
subi
1ba:
22 33
cpi
1bc:
d1 f7
brne
>
Wait();
PORTC &= ~(1 <<1); // Set PORTC bit
Wait();

2 low
0x15, 1 ; 21
r18, 0x00
r20, 0x00
r21, 0x00
r24, r20
r24, 0x01
.-4

r18, 0xFF
r18, 0x32
.-12
2 low

}
1be:
1c0:
1c2:
1c4:
1c6:

ff
ef
bf
af
9f

91
91
91
91
91

; 255
; 50
; 0x19e <__vector_1+0x48

pop
pop
pop
pop
pop

r31
r30
r27
r26
r25

; 0
; 0
; 0
; 1
; 0x1b4 <__vector_1+0x5e

; 255
; 50
; 0x1b2 <__vector_1+0x5c

1c8:
1ca:
1cc:
1ce:
1d0:
1d2:
1d4:
1d6:
1d8:
1da:
1dc:
1de:

8f
7f
6f
5f
4f
3f
2f
0f
0f
0f
1f
18

91
91
91
91
91
91
91
90
be
90
90
95

pop
pop
pop
pop
pop
pop
pop
pop
out
pop
pop
reti

r24
r23
r22
r21
r20
r19
r18
r0
0x3f, r0
r0
r1

000001e0 <main>:
uint8_t i;
for(i=0;i<50;i++)
_delay_loop_2(0);
}
void main()
{
1e0:
bf 92
push
r11
1e2:
cf 92
push
r12
1e4:
df 92
push
r13
1e6:
ef 92
push
r14
1e8:
ff 92
push
r15
1ea:
0f 93
push
r16
1ec:
1f 93
push
r17
1ee:
df 93
push
r29
1f0:
cf 93
push
r28
1f2:
cd b7
in
r28, 0x3d
1f4:
de b7
in
r29, 0x3e
1f6:
2a 97
sbiw
r28, 0x0a
1f8:
0f b6
in
r0, 0x3f
1fa:
f8 94
cli
1fc:
de bf
out
0x3e, r29
1fe:
0f be
out
0x3f, r0
200:
cd bf
out
0x3d, r28
DDRC |= (1 << 0) ; // Set PORTC bit 2 as an output
202:
a0 9a
sbi
0x14, 0 ; 20
DDRC |= (1 << 1); // Set PORTC bit 2 as an output
204:
a1 9a
sbi
0x14, 1 ; 20
DDRC |= (1 << 2); // Set PORTC bit 2 as an output
206:
a2 9a
sbi
0x14, 2 ; 20
PORTC &= ~(1 <<0); // Set PORTC bit 2 low
208:
a8 98
cbi
0x15, 0 ; 21
PORTC &= ~(1 <<1); // Set PORTC bit 2 low
20a:
a9 98
cbi
0x15, 1 ; 21
PORTC &= ~(1 <<2); // Set PORTC bit 2 low
20c:
aa 98
cbi
0x15, 2 ; 21
unsigned int d;
unsigned char c[10];
uint16_t r;
USARTInit(51);
20e:
83 e3
ldi
r24, 0x33
210:
90 e0
ldi
r25, 0x00
212:
0e 94 67 01
call
0x2ce ; 0x2ce
216:
20 e0
ldi
r18, 0x00
218:
40 e0
ldi
r20, 0x00
21a:
50 e0
ldi
r21, 0x00
21c:
ca 01
movw
r24, r20

; 63

;
;
;
;

61
62
10
63

; 62
; 63
; 61

; 51
; 0
<USARTInit>
; 0
; 0
; 0

21e:
220:

01 97
f1 f7

sbiw
brne

r24, 0x01
.-4

; 1
; 0x21e <main+0x3e>

subi
cpi
brne

r18, 0xFF
r18, 0x32
.-12

; 255
; 50
; 0x21c <main+0x3c>

}
void Wait()
{
uint8_t i;
for(i=0;i<50;i++)
222:
2f 5f
224:
22 33
226:
d1 f7
}

void int0_init( void )

{
MCUCR |= (1<<ISC01); //falling edge
228:
85 b7
in
r24, 0x35
22a:
82 60
ori
r24, 0x02
22c:
85 bf
out
0x35, r24
GICR |= (1<<INT0);
//enable INT0
22e:
8b b7
in
r24, 0x3b
230:
80 64
ori
r24, 0x40
232:
8b bf
out
0x3b, r24
unsigned char c[10];
uint16_t r;
USARTInit(51);
Wait();
int0_init();
sei();
234:
78 94
sei
236:
7e 01
movw
r14, r28
238:
08 94
sec
23a:
e1 1c
adc
r14, r1
23c:
f1 1c
adc
r15, r1
can be achieved.
*/
void
_delay_loop_1(uint8_t __count)
{
__asm__ volatile (
23e:
55 e3
ldi
r21, 0x35
240:
c5 2e
mov
r12, r21
milliseconds can be achieved.
*/
void
_delay_loop_2(uint16_t __count)
{
__asm__ volatile (
242:
40 e5
ldi
r20, 0x50
244:
b4 2e
mov
r11, r20
246:
3a e6
ldi
r19, 0x6A
248:
d3 2e
mov
r13, r19
24a:
00 e0
ldi
r16, 0x00
24c:
10 e0
ldi
r17, 0x00
while(1)
{
24e:

US_DDR|=(1<<US_POS);
d0 9a
sbi

0x1a, 0 ; 26

; 53
; 2
; 53
; 59
; 64
; 59

; 53

; 80
; 106
; 0
; 0

can be achieved.
*/
void
_delay_loop_1(uint8_t __count)
{
__asm__ volatile (
250:
8c 2d
mov
r24, r12
252:
8a 95
dec
r24
254:
f1 f7
brne
.-4
_delay_us(10);
//Give the US pin a 15us High Pulse
US_PORT|=(1<<US_POS); //High
256:
d8 9a
sbi
0x1b, 0 ; 27
258:
8b 2d
mov
r24, r11
25a:
8a 95
dec
r24
25c:
f1 f7
brne
.-4
_delay_us(15);
US_PORT&=(~(1<<US_POS));//Low
25e:
d8 98
cbi
0x1b, 0 ; 27
260:
8d 2d
mov
r24, r13
262:
8a 95
dec
r24
264:
f1 f7
brne
.-4
_delay_us(20);
//Now make the pin input
US_DDR&=(~(1<<US_POS));
266:
d0 98
cbi
0x1a, 0 ; 26
//Measure the width of pulse
r=getPulseWidth();
268:
0e 94 50 00
call
0xa0
; 0xa0

26c:
26e:
270:
272:

274:
276:
278:
27a:

27c:
27e:
280:
282:
286:
288:
28a:
28c:
28e:
292:

//Handle Errors
if(r==US_ERROR)
2f ef
ldi
r18, 0xFF
8f 3f
cpi
r24, 0xFF
92 07
cpc
r25, r18
19 f1
breq
.+70
{
UWriteString(" Error !");
}
else
if(r==US_NO_OBSTACLE)
2f ef
ldi
r18, 0xFF
8e 3f
cpi
r24, 0xFE
92 07
cpc
r25, r18
21 f1
breq
.+72
}
else
{
d=(r/58.0);
itoa(d,
bc 01
80 e0
90 e0
0e 94 3a 05
20 e0
30 e0
48 e6
52 e4
0e 94 0a 04
0e 94 34 02

; 0x252 <main+0x72>

; 0x25a <main+0x7a>

; 0x262 <main+0x82>

<getPulseWidth>

; 255
; 255
; 0x2ba <main+0xda>

; 255
; 254
; 0x2c4 <main+0xe4>

//Convert to cm
c, 10);
movw
r22, r24
ldi
r24, 0x00
; 0
ldi
r25, 0x00
; 0
call
0xa74 ; 0xa74 <__floatunsisf>
ldi
r18, 0x00
; 0
ldi
r19, 0x00
; 0
ldi
r20, 0x68
; 104
ldi
r21, 0x42
; 66
call
0x814 ; 0x814 <__divsf3>
call
0x468 ; 0x468 <__fixunssfsi>

296:
298:
29a:
29c:
29e:
2a0:

dc
cb
b7
4a
50
0e
//

01
movw
r26, r24
01
movw
r24, r22
01
movw
r22, r14
e0
ldi
r20, 0x0A
; 10
e0
ldi
r21, 0x00
; 0
94 df 07
call
0xfbe ; 0xfbe <itoa>
f=(c & "cm");
UWriteString(c);
2a4:
c7 01
movw
r24, r14
2a6:
0e 94 25 02
call
0x44a ; 0x44a <UWriteString>
2aa:
20 e0
ldi
r18, 0x00
; 0
milliseconds can be achieved.
*/
void
_delay_loop_2(uint16_t __count)
{
__asm__ volatile (
2ac:
c8 01
movw
2ae:
01 97
sbiw
2b0:
f1 f7
brne
}
void Wait()
{
uint8_t i;
for(i=0;i<50;i++)
2b2:
2f 5f
subi
2b4:
22 33
cpi
2b6:
d1 f7
brne
2b8:
ca cf
rjmp
r=getPulseWidth();

2ba:
2bc:
2be:
2c2:

2c4:
2c6:
2c8:
2cc:

r24, r16
r24, 0x01
.-4

; 1
; 0x2ae <main+0xce>

r18, 0xFF
r18, 0x32
.-12
.-108

;
;
;
;

255
50
0x2ac <main+0xcc>
0x24e <main+0x6e>

//Handle Errors
if(r==US_ERROR)
{
UWriteString(" Error !");
85 e6
ldi
r24, 0x65
; 101
90 e0
ldi
r25, 0x00
; 0
0e 94 25 02
call
0x44a ; 0x44a <UWriteString>
c5 cf
rjmp
.-118
; 0x24e <main+0x6e>
}
else
if(r==US_NO_OBSTACLE)
{
UWriteString(" Clear !");
8e e6
ldi
r24, 0x6E
; 110
90 e0
ldi
r25, 0x00
; 0
0e 94 25 02
call
0x44a ; 0x44a <UWriteString>
c0 cf
rjmp
.-128
; 0x24e <main+0x6e>

000002ce <USARTInit>:
#include "usart.h"
void USARTInit(uint16_t ubrrvalue)
{
//Setup q
UQFront=UQEnd=-1;
2ce:
2f ef
ldi
2d0:
20 93 81 01
sts
2d4:
20 91 81 01
lds
2d8:
20 93 80 01
sts

r18, 0xFF
0x0181, r18
r18, 0x0181
0x0180, r18

; 255

//Set Baud rate

UBRRH=(unsigned char)(ubrrvalue>>8);
2dc:
90 bd
out
0x20, r25
UBRRL=(unsigned char)ubrrvalue;
2de:
89 b9
out
0x09, r24
Asynchronous mode
No Parity
1 StopBit
char size 8
*/
UCSRC=(1<<URSEL)|(3<<UCSZ0);
2e0:
86 e8
ldi
r24, 0x86
2e2:
80 bd
out
0x20, r24
/*Enable Interrupts
RXCIE- Receive complete
UDRIE- Data register empty
Enable The recevier and transmitter
*/
UCSRB=(1<<RXCIE)|(1<<RXEN)|(1<<TXEN);
2e4:
88 e9
ldi
r24, 0x98
2e6:
8a b9
out
0x0a, r24
sei();
2e8:
78 94
sei

; 32
; 9

; 134
; 32

; 152
; 10

}
2ea:

08 95

ret

000002ec <__vector_13>:
//The USART ISR
ISR(USART_RXC_VECT)
{
2ec:
1f 92
2ee:
0f 92
2f0:
0f b6
2f2:
0f 92
2f4:
11 24
2f6:
2f 93
2f8:
3f 93
2fa:
4f 93
2fc:
8f 93
2fe:
9f 93
300:
ef 93
302:
ff 93
//Read the data
char data=UDR;
304:
4c b1

push
push
in
push
eor
push
push
push
push
push
push
push

r1
r0
r0, 0x3f
r0
r1, r1
r18
r19
r20
r24
r25
r30
r31

in

r20, 0x0c

; 63

; 12

//Now add it to q
if(((UQEnd==RECEIVE_BUFF_SIZE-1) && UQFront==0) || ((UQEnd+1)==UQFront))
306:
80 91 81 01
lds
r24, 0x0181
30a:
8f 33
cpi
r24, 0x3F
; 63
30c:
89 f1
breq
.+98
; 0x370 <__vector_13+0x8
4>
30e:
312:
316:
318:

80
20
99
87

91 81 01
91 80 01
27
fd

lds
lds
eor
sbrc

r24,
r18,
r25,
r24,

0x0181
0x0180
r25
7

31a:
31c:
31e:
320:
322:
324:
326:
328:

90
01
33
27
30
82
93
39

95
96
27
fd
95
17
07
f1

com
adiw
eor
sbrc
com
cp
cpc
breq

r25
r24,
r19,
r18,
r19
r24,
r25,
.+78

0x01
r19
7

; 1

r18
r19
; 0x378 <__vector_13+0x8

c>
UQFront++;
if(UQFront==RECEIVE_BUFF_SIZE) UQFront=0;
}
if(UQEnd==RECEIVE_BUFF_SIZE-1)
32a:
80 91 81 01
lds
r24, 0x0181
32e:
8f 33
cpi
r24, 0x3F
330:
91 f1
breq
.+100

; 63
; 0x396 <__vector_13+0xa

a>
UQEnd=0;
else
UQEnd++;
80 91 81 01
8f 5f
80 93 81 01

lds
subi
sts

r24, 0x0181
r24, 0xFF
0x0181, r24

URBuff[UQEnd]=data;
33c:
e0 91 81 01
340:
ff 27
342:
e7 fd
344:
f0 95
346:
ee 57
348:
fe 4f
34a:
40 83

lds
eor
sbrc
com
subi
sbci
st

r30, 0x0181
r31, r31
r30, 7
r31
r30, 0x7E
r31, 0xFE
Z, r20

if(UQFront==-1) UQFront=0;
34c:
80 91 80 01
lds
350:
8f 3f
cpi
352:
11 f4
brne

r24, 0x0180
r24, 0xFF
.+4

354:

sts

0x0180, r1

pop
pop
pop
pop
pop
pop
pop
pop
out
pop
pop
reti

r31
r30
r25
r24
r20
r19
r18
r0
0x3f, r0
r0
r1

332:
336:
338:

; 255

; 126
; 254

; 255
; 0x358 <__vector_13+0x6

c>
10 92 80 01

}
358:
ff 91
35a:
ef 91
35c:
9f 91
35e:
8f 91
360:
4f 91
362:
3f 91
364:
2f 91
366:
0f 90
368:
0f be
36a:
0f 90
36c:
1f 90
36e:
18 95
//Read the data
char data=UDR;
//Now add it to q

; 63

if(((UQEnd==RECEIVE_BUFF_SIZE-1) && UQFront==0) || ((UQEnd+1)==UQFront))

370:
80 91 80 01
lds
r24, 0x0180
374:
88 23
and
r24, r24
376:
59 f6
brne
.-106
; 0x30e <__vector_13+0x2
2>
{
378:
37c:
37e:
382:
386:
388:

//Q Full
UQFront++;
80 91 80 01
lds
r24, 0x0180
8f 5f
subi
r24, 0xFF
; 255
80 93 80 01
sts
0x0180, r24
if(UQFront==RECEIVE_BUFF_SIZE) UQFront=0;
80 91 80 01
lds
r24, 0x0180
80 34
cpi
r24, 0x40
; 64
81 f6
brne
.-96
; 0x32a <__vector_13+0x3

e>
38a:
}

10 92 80 01

sts

0x0180, r1

if(UQEnd==RECEIVE_BUFF_SIZE-1)
38e:
80 91 81 01
lds
r24, 0x0181
392:
8f 33
cpi
r24, 0x3F
394:
71 f6
brne
.-100

; 63
; 0x332 <__vector_13+0x4

6>
396:
39a:

UQEnd=0;
10 92 81 01
d0 cf

sts
rjmp

0x0181, r1
.-96

; 0x33c <__vector_13+0x5

//Check if q is empty
if(UQFront==-1)
39c:
80 91 80 01
3a0:
8f 3f
3a2:
c9 f0
return 0;

lds
cpi
breq

r24, 0x0180
r24, 0xFF
.+50

; 255
; 0x3d6 <UReadData+0x3a>

data=URBuff[UQFront];
3a4:
e0 91 80 01
3a8:
ff 27
3aa:
e7 fd
3ac:
f0 95
3ae:
ee 57
3b0:
fe 4f
3b2:
e0 81

lds
eor
sbrc
com
subi
sbci
ld

r30,
r31,
r30,
r31
r30,
r31,
r30,

lds
lds
cp
breq

r25, 0x0180
r24, 0x0181
r25, r24
.+28

0>
0000039c <UReadData>:
char UReadData()
{
char data;

if(UQFront==UQEnd)
3b4:
90 91 80 01
3b8:
80 91 81 01
3bc:
98 17
3be:
71 f0
//So empty q
UQFront=UQEnd=-1;
}

0x0180
r31
7
0x7E
0xFE
Z

; 126
; 254

; 0x3dc <UReadData+0x40>

else
{
3c0:
3c4:
3c6:
3ca:
3ce:
3d0:

UQFront++;
80 91 80 01
8f 5f
80 93 80 01

lds
subi
sts

r24, 0x0180
r24, 0xFF
0x0180, r24

if(UQFront==RECEIVE_BUFF_SIZE)
80 91 80 01
lds
r24, 0x0180
80 34
cpi
r24, 0x40
71 f0
breq
.+28
UQFront=0;

; 255

; 64
; 0x3ee <UReadData+0x52>

}
return data;
}
3d2:
8e 2f
3d4:
08 95
char UReadData()
{
char data;

mov
ret

r24, r30

//Check if q is empty
if(UQFront==-1)
3d6:
e0 e0
ldi
r30, 0x00
if(UQFront==RECEIVE_BUFF_SIZE)
UQFront=0;
}

; 0

return data;
}
3d8:
3da:

8e 2f
08 95

mov
ret

r24, r30

if(UQFront==UQEnd)
{
//If single data is left
//So empty q
UQFront=UQEnd=-1;
3dc:
8f ef
ldi
r24, 0xFF
3de:
80 93 81 01
sts
0x0181, r24
3e2:
80 91 81 01
lds
r24, 0x0181
3e6:
80 93 80 01
sts
0x0180, r24
if(UQFront==RECEIVE_BUFF_SIZE)
UQFront=0;
}
return data;
}
3ea:
3ec:
else
{

8e 2f
08 95

mov
ret

r24, r30

UQFront++;

3ee:
}

if(UQFront==RECEIVE_BUFF_SIZE)
UQFront=0;
10 92 80 01
sts
0x0180, r1

; 255

return data;
}
3f2:
3f4:

8e 2f
08 95

mov
ret

r24, r30

000003f6 <UWriteData>:
void UWriteData(char data)
{
//Wait For Transmitter to become ready
while(!(UCSRA & (1<<UDRE)));
3f6:
5d 9b
sbis
0x0b, 5 ; 11
3f8:
fe cf
rjmp
.-4
//Now write
UDR=data;
3fa:
8c b9

out

3fc:

ret

0x0c, r24

; 0x3f6 <UWriteData>

; 12

}
08 95

000003fe <UDataAvailable>:
uint8_t UDataAvailable()
{
if(UQFront==-1) return 0;
3fe:
80 91 80 01
lds
r24, 0x0180
402:
8f 3f
cpi
r24, 0xFF
; 255
404:
e1 f0
breq
.+56
; 0x43e <UDataAvailable+
0x40>
if(UQFront<UQEnd)
406:
90 91 80 01
lds
r25, 0x0180
40a:
80 91 81 01
lds
r24, 0x0181
40e:
98 17
cp
r25, r24
410:
74 f0
brlt
.+28
; 0x42e <UDataAvailable+
0x30>
return(UQEnd-UQFront+1);
else if(UQFront>UQEnd)
412:
90 91 80 01
lds
r25, 0x0180
416:
80 91 81 01
lds
r24, 0x0181
41a:
89 17
cp
r24, r25
41c:
9c f4
brge
.+38
; 0x444 <UDataAvailable+
0x46>
return (RECEIVE_BUFF_SIZE-UQFront+UQEnd+1);
41e:
90 91 81 01
lds
r25, 0x0181
422:
80 91 80 01
lds
r24, 0x0180
426:
9f 5b
subi
r25, 0xBF
; 191
428:
98 1b
sub
r25, r24
else
return 1;
}
42a:
89 2f
mov
r24, r25
42c:
08 95
ret
uint8_t UDataAvailable()
{
if(UQFront==-1) return 0;
if(UQFront<UQEnd)
return(UQEnd-UQFront+1);
42e:
90 91 81 01
lds
r25, 0x0181
432:
80 91 80 01
lds
r24, 0x0180

436:
9f 5f
subi
r25, 0xFF
; 255
438:
98 1b
sub
r25, r24
else if(UQFront>UQEnd)
return (RECEIVE_BUFF_SIZE-UQFront+UQEnd+1);
else
return 1;
}
43a:
89 2f
43c:
08 95
UDR=data;

mov
ret

r24, r25

}
uint8_t UDataAvailable()
{
if(UQFront==-1) return 0;
43e:
90 e0
ldi
r25, 0x00
; 0
return(UQEnd-UQFront+1);
else if(UQFront>UQEnd)
return (RECEIVE_BUFF_SIZE-UQFront+UQEnd+1);
else
return 1;
}
440:
89 2f
mov
r24, r25
442:
08 95
ret
uint8_t UDataAvailable()
{
if(UQFront==-1) return 0;
if(UQFront<UQEnd)
return(UQEnd-UQFront+1);
else if(UQFront>UQEnd)
444:
91 e0
ldi
r25, 0x01
; 1
return (RECEIVE_BUFF_SIZE-UQFront+UQEnd+1);
else
return 1;
}
446:
89 2f
mov
r24, r25
448:
08 95
ret
0000044a <UWriteString>:
void UWriteString(char *str)
{
44a:
fc 01
while((*str)!='\0')
44c:
80 81
44e:
88 23
450:
39 f0
16>
}

movw

r30, r24

ld
and
breq

r24, Z
r24, r24
.+14

void UWriteData(char data)

{
//Wait For Transmitter to become ready
while(!(UCSRA & (1<<UDRE)));
452:
5d 9b
sbis
0x0b, 5 ; 11
454:
fe cf
rjmp
.-4
8>
//Now write
UDR=data;

; 0x460 <UWriteString+0x

; 0x452 <UWriteString+0x

456:
8c b9
out
void UWriteString(char *str)
{
while((*str)!='\0')
{
UWriteData(*str);
str++;
458:
31 96
adiw
return 1;
}
void UWriteString(char *str)
{
while((*str)!='\0')
45a:
80 81
45c:
88 23
45e:
c9 f7
8>
}

ld
and
brne

0x0c, r24

; 12

r30, 0x01

; 1

r24, Z
r24, r24
.-14

; 0x452 <UWriteString+0x

void UWriteData(char data)

{
//Wait For Transmitter to become ready
while(!(UCSRA & (1<<UDRE)));
460:
5d 9b
sbis
0x0b, 5 ; 11
462:
fe cf
rjmp
.-4
16>
//Now write
UDR=data;
464:
1c b8
out
UWriteData(*str);
str++;
}

0x0c, r1

; 0x460 <UWriteString+0x

; 12

UWriteData('\0');
}
466:

08 95

00000468 <__fixunssfsi>:
468:
ef 92
46a:
ff 92
46c:
0f 93
46e:
1f 93
470:
7b 01
472:
8c 01
474:
20 e0
476:
30 e0
478:
40 e0
47a:
5f e4
47c:
0e 94 b6 04
480:
88 23
482:
8c f0
3e>
484:
c8 01
486:
b7 01
488:
20 e0
48a:
30 e0
48c:
40 e0
48e:
5f e4

ret
push
push
push
push
movw
movw
ldi
ldi
ldi
ldi
call
and
brlt

r14
r15
r16
r17
r14, r22
r16, r24
r18, 0x00
; 0
r19, 0x00
; 0
r20, 0x00
; 0
r21, 0x4F
; 79
0x96c ; 0x96c <__gesf2>
r24, r24
.+34
; 0x4a6 <__fixunssfsi+0x

movw
movw
ldi
ldi
ldi
ldi

r24,
r22,
r18,
r19,
r20,
r21,

r16
r14
0x00
0x00
0x00
0x4F

;
;
;
;

0
0
0
79

490:
494:
498:
49a:
49c:
49e:
4a0:
4a2:
4a4:

0e
0e
9b
ac
20
30
40
50
06

94 ac 03
94 e6 04
01
01
50
40
40
48
c0

call
call
movw
movw
subi
sbci
sbci
sbci
rjmp

0x758 ; 0x758 <__subsf3>

0x9cc ; 0x9cc <__fixsfsi>
r18, r22
r20, r24
r18, 0x00
; 0
r19, 0x00
; 0
r20, 0x00
; 0
r21, 0x80
; 128
.+12
; 0x4b2 <__fixunssfsi+0x

4a6:
4a8:
4aa:
4ae:
4b0:
4b2:
4b4:
4b6:
4b8:
4ba:
4bc:
4be:

c8
b7
0e
9b
ac
b9
ca
1f
0f
ff
ef
08

01
01
94 e6 04
01
01
01
01
91
91
90
90
95

movw
movw
call
movw
movw
movw
movw
pop
pop
pop
pop
ret

r24, r16
r22, r14
0x9cc ; 0x9cc <__fixsfsi>
r18, r22
r20, r24
r22, r18
r24, r20
r17
r16
r15
r14

ldi
ldi
ldi
ldi
jmp
movw
movw
movw
ld
cpi
brcc

r26, 0x00
; 0
r27, 0x00
; 0
r30, 0x66
; 102
r31, 0x02
; 2
0xf50 ; 0xf50 <__prologue_saves__>
r26, r24
r4, r22
r30, r20
r25, X
r25, 0x02
; 2
.+2
; 0x4da <_fpadd_parts+0x

rjmp

.+626

; 0x74c <_fpadd_parts+0x

movw
ld
cpi
brcc

r28, r22
r24, Y
r24, 0x02
.+2

; 2
; 0x4e4 <_fpadd_parts+0x

rjmp

.+614

; 0x74a <_fpadd_parts+0x

cpi
brne

r25, 0x04
.+26

; 4
; 0x502 <_fpadd_parts+0x

cpi
breq

r24, 0x04
.+2

; 4
; 0x4ee <_fpadd_parts+0x

rjmp

.+606

; 0x74c <_fpadd_parts+0x

adiw
ld
sbiw
ldd
cp
brne

r26,
r25,
r26,
r24,
r25,
.+2

; 1

4a>

000004c0 <_fpadd_parts>:
4c0:
a0 e0
4c2:
b0 e0
4c4:
e6 e6
4c6:
f2 e0
4c8:
0c 94 a8 07
4cc:
dc 01
4ce:
2b 01
4d0:
fa 01
4d2:
9c 91
4d4:
92 30
4d6:
08 f4
1a>
4d8:
39 c1
28c>
4da:
eb 01
4dc:
88 81
4de:
82 30
4e0:
08 f4
24>
4e2:
33 c1
28a>
4e4:
94 30
4e6:
69 f4
42>
4e8:
84 30
4ea:
09 f0
2e>
4ec:
2f c1
28c>
4ee:
11 96
4f0:
9c 91
4f2:
11 97
4f4:
89 81
4f6:
98 17
4f8:
09 f4
3c>

0x01
X
0x01
Y+1
r24

; 1
; 0x01
; 0x4fc <_fpadd_parts+0x

4fa:

28 c1

rjmp

.+592

; 0x74c <_fpadd_parts+0x

4fc:
4fe:
500:

a7 e7
b0 e0
25 c1

ldi
ldi
rjmp

r26, 0x77
r27, 0x00
.+586

; 119
; 0
; 0x74c <_fpadd_parts+0x

502:
504:

84 30
09 f4

cpi
brne

r24, 0x04
.+2

; 4
; 0x508 <_fpadd_parts+0x

506:

21 c1

rjmp

.+578

; 0x74a <_fpadd_parts+0x

508:
50a:

82 30
a9 f4

cpi
brne

r24, 0x02
.+42

; 2
; 0x536 <_fpadd_parts+0x

50c:
50e:

92 30
09 f0

cpi
breq

r25, 0x02
.+2

; 2
; 0x512 <_fpadd_parts+0x

510:

1d c1

rjmp

.+570

; 0x74c <_fpadd_parts+0x

512:
514:
516:
518:
51a:
51c:
51e:
520:
522:
524:
526:

9a
ad
88
ea
09
ae
e9
09
9e
81
c1

01
01
e0
01
90
01
01
92
01
50
f7

movw
movw
ldi
movw
ld
movw
movw
st
movw
subi
brne

r18, r20
r20, r26
r24, 0x08
r28, r20
r0, Y+
r20, r28
r28, r18
Y+, r0
r18, r28
r24, 0x01
.-16

528:
52a:
52c:
52e:
530:
532:
534:

e2
89
11
9c
89
81
08

01
81
96
91
23
83
c1

movw
ldd
adiw
ld
and
std
rjmp

r28, r4
r24, Y+1
r26, 0x01
r25, X
r24, r25
Z+1, r24
.+528

536:
538:

92 30
09 f4

cpi
brne

r25, 0x02
.+2

; 2
; 0x53c <_fpadd_parts+0x

53a:

07 c1

rjmp

.+526

; 0x74a <_fpadd_parts+0x

53c:
53e:
540:
542:
544:
546:
548:
54a:
54c:
54e:
550:
552:
554:
556:
558:
55a:

12
2d
3c
13
eb
8a
9b
14
ad
bd
cd
dc
17
ec
fd
0e

adiw
ld
ld
sbiw
movw
ldd
ldd
adiw
ld
ld
ld
ld
sbiw
ldd
ldd
ldd

r26, 0x02
r2, X+
r3, X
r26, 0x03
r28, r22
r24, Y+2
r25, Y+3
r26, 0x04
r10, X+
r11, X+
r12, X+
r13, X
r26, 0x07
r14, Y+4
r15, Y+5
r16, Y+6

; 2

28c>

28c>
48>
28a>
76>
52>
28c>
; 8

; 1
; 0x518 <_fpadd_parts+0x

58>
; 0x01
; 1
; 0x01
; 0x746 <_fpadd_parts+0x

286>
7c>
28a>
96
90
90
97
01
81
81
96
90
90
90
90
97
80
80
81

; 3
; 0x02
; 0x03
; 4

;
;
;
;

7
0x04
0x05
0x06

55c:
55e:
560:
562:
564:
566:
568:

1f
91
28
39
b9
37
04

81
01
1b
0b
01
ff
c0

ldd
movw
sub
sbc
movw
sbrs
rjmp

r17,
r18,
r18,
r19,
r22,
r19,
.+8

Y+7
r2
r24
r25
r18
7

; 0x07

56a:
56c:
56e:
570:
572:
574:
576:

66
77
62
73
60
71
0c

27
27
1b
0b
32
05
f0

eor
eor
sub
sbc
cpi
cpc
brlt

r22,
r23,
r22,
r23,
r22,
r23,
.+2

r22
r23
r18
r19
0x20
r1

578:

61 c0

rjmp

.+194

; 0x63c <_fpadd_parts+0x

57a:
57c:
57e:

12 16
13 06
6c f5

cp
cpc
brge

r1, r18
r1, r19
.+90

; 0x5da <_fpadd_parts+0x

580:
582:
584:
586:

37
48
06
04

01
01
2e
c0

movw
movw
mov
rjmp

r6, r14
r8, r16
r0, r22
.+8

; 0x590 <_fpadd_parts+0x

588:
58a:
58c:
58e:
590:
592:

96
87
77
67
0a
d2

94
94
94
94
94
f7

lsr
ror
ror
ror
dec
brpl

r9
r8
r7
r6
r0
.-12

; 0x588 <_fpadd_parts+0x

594:
596:
598:
59a:
59c:

21
30
40
50
04

e0
e0
e0
e0
c0

ldi
ldi
ldi
ldi
rjmp

r18,
r19,
r20,
r21,
.+8

0x01
0x00
0x00
0x00

59e:
5a0:
5a2:
5a4:
5a6:
5a8:

22
33
44
55
6a
d2

0f
1f
1f
1f
95
f7

add
adc
adc
adc
dec
brpl

r18,
r19,
r20,
r21,
r22
.-12

r18
r19
r20
r21

5aa:
5ac:
5ae:
5b0:
5b2:
5b4:
5b6:
5b8:
5ba:
5bc:
5be:
5c0:
5c2:

21
30
40
50
2e
3f
40
51
21
31
41
51
21

50
40
40
40
21
21
23
23
15
05
05
05
f0

subi
sbci
sbci
sbci
and
and
and
and
cp
cpc
cpc
cpc
breq

r18,
r19,
r20,
r21,
r18,
r19,
r20,
r21,
r18,
r19,
r20,
r21,
.+8

0x01
0x00
0x00
0x00
r14
r15
r16
r17
r1
r1
r1
r1

; 0x572 <_fpadd_parts+0x

b2>

; 32
; 0x57a <_fpadd_parts+0x

ba>
17c>

11a>

d0>

c8>
;
;
;
;
;

1
0
0
0
0x5a6 <_fpadd_parts+0x

e6>

; 0x59e <_fpadd_parts+0x

de>
;
;
;
;

1
0
0
0

; 0x5cc <_fpadd_parts+0x

10c>
5c4:
5c6:
5c8:
5ca:
5cc:
5ce:
5d0:
5d2:
5d4:
5d6:
5d8:

21
30
40
50
79
8a
e6
f7
08
19
3c

e0
e0
e0
e0
01
01
28
28
29
29
c0

ldi
ldi
ldi
ldi
movw
movw
or
or
or
or
rjmp

r18, 0x01
r19, 0x00
r20, 0x00
r21, 0x00
r14, r18
r16, r20
r14, r6
r15, r7
r16, r8
r17, r9
.+120

;
;
;
;

1
0
0
0

5da:
5dc:

23 2b
d1 f1

or
breq

r18, r19
.+116

; 0x652 <_fpadd_parts+0x

5de:
5e0:
5e2:
5e4:
5e6:
5e8:

26
37
35
46
06
04

0e
1e
01
01
2e
c0

add
adc
movw
movw
mov
rjmp

r2,
r3,
r6,
r8,
r0,
.+8

; 0x5f2 <_fpadd_parts+0x

5ea:
5ec:
5ee:
5f0:
5f2:
5f4:

96
87
77
67
0a
d2

94
94
94
94
94
f7

lsr
ror
ror
ror
dec
brpl

r9
r8
r7
r6
r0
.-12

5f6:
5f8:
5fa:
5fc:
5fe:

21
30
40
50
04

e0
e0
e0
e0
c0

ldi
ldi
ldi
ldi
rjmp

r18,
r19,
r20,
r21,
.+8

0x01
0x00
0x00
0x00

600:
602:
604:
606:
608:
60a:

22
33
44
55
6a
d2

0f
1f
1f
1f
95
f7

add
adc
adc
adc
dec
brpl

r18,
r19,
r20,
r21,
r22
.-12

r18
r19
r20
r21

60c:
60e:
610:
612:
614:
616:
618:
61a:
61c:
61e:
620:
622:
624:

21
30
40
50
2a
3b
4c
5d
21
31
41
51
21

50
40
40
40
21
21
21
21
15
05
05
05
f0

subi
sbci
sbci
sbci
and
and
and
and
cp
cpc
cpc
cpc
breq

r18,
r19,
r20,
r21,
r18,
r19,
r20,
r21,
r18,
r19,
r20,
r21,
.+8

0x01
0x00
0x00
0x00
r10
r11
r12
r13
r1
r1
r1
r1

626:
628:
62a:

21 e0
30 e0
40 e0

ldi
ldi
ldi

r18, 0x01
r19, 0x00
r20, 0x00

; 0x652 <_fpadd_parts+0x

192>
192>
r22
r23
r10
r12
r22

132>

; 0x5ea <_fpadd_parts+0x

12a>
;
;
;
;
;

1
0
0
0
0x608 <_fpadd_parts+0x

148>

; 0x600 <_fpadd_parts+0x

140>
;
;
;
;

1
0
0
0

; 0x62e <_fpadd_parts+0x

16e>
; 1
; 0
; 0

62c:
62e:
630:
632:
634:
636:
638:
63a:

50
59
6a
a6
b7
c8
d9
0b

e0
01
01
28
28
28
28
c0

ldi
movw
movw
or
or
or
or
rjmp

r21,
r10,
r12,
r10,
r11,
r12,
r13,
.+22

0x00
r18
r20
r6
r7
r8
r9

; 0

63c:
63e:
640:

82 15
93 05
2c f0

cp
cpc
brlt

r24, r2
r25, r3
.+10

; 0x64c <_fpadd_parts+0x

642:
644:
646:
648:
64a:

1c
aa
bb
65
03

01
24
24
01
c0

movw
eor
eor
movw
rjmp

r2, r24
r10, r10
r11, r11
r12, r10
.+6

; 0x652 <_fpadd_parts+0x

64c:
64e:
650:
652:
654:
656:
658:
65a:
65c:
65e:

ee
ff
87
11
9c
d2
11
8c
98
09

24
24
01
96
91
01
96
91
17
f4

eor
eor
movw
adiw
ld
movw
adiw
ld
cp
brne

r14,
r15,
r16,
r26,
r25,
r26,
r26,
r24,
r25,
.+2

660:

45 c0

rjmp

.+138

; 0x6ec <_fpadd_parts+0x

662:
664:

99 23
39 f0

and
breq

r25, r25
.+14

; 0x674 <_fpadd_parts+0x

666:
668:
66a:
66c:
66e:
670:
672:

a8
97
2a
3b
4c
5d
06

01
01
19
09
09
09
c0

movw
movw
sub
sbc
sbc
sbc
rjmp

r20,
r18,
r18,
r19,
r20,
r21,
.+12

r16
r14
r10
r11
r12
r13
; 0x680 <_fpadd_parts+0x

674:
676:
678:
67a:
67c:
67e:
680:
682:

a6
95
2e
3f
40
51
57
08

01
01
19
09
0b
0b
fd
c0

movw
movw
sub
sbc
sbc
sbc
sbrc
rjmp

r20,
r18,
r18,
r19,
r20,
r21,
r21,
.+16

r12
r10
r14
r15
r16
r17
7

684:
686:
688:
68a:
68c:
68e:
690:
692:

11
33
22
24
35
46
57
1d

82
82
82
83
83
83
83
c0

std
std
std
std
std
std
std
rjmp

Z+1,
Z+3,
Z+2,
Z+4,
Z+5,
Z+6,
Z+7,
.+58

r1 ; 0x01
r3 ; 0x03
r2 ; 0x02
r18
; 0x04
r19
; 0x05
r20
; 0x06
r21
; 0x07
; 0x6ce <_fpadd_parts+0x

; 0x652 <_fpadd_parts+0x

192>

18c>

192>
r14
r15
r14
0x01
X
r4
0x01
X
r24

; 1
; 1
; 0x662 <_fpadd_parts+0x

1a2>
22c>
1b4>

1c0>

; 0x694 <_fpadd_parts+0x

1d4>

20e>
694:
696:
698:
69a:
69c:
69e:
6a0:
6a2:
6a4:
6a6:
6a8:
6aa:
6ac:
6ae:
6b0:
6b2:

81
81
33
22
88
99
dc
82
93
a4
b5
84
95
a6
b7
0d

e0
83
82
82
27
27
01
1b
0b
0b
0b
83
83
83
83
c0

ldi
std
std
std
eor
eor
movw
sub
sbc
sbc
sbc
std
std
std
std
rjmp

r24,
Z+1,
Z+3,
Z+2,
r24,
r25,
r26,
r24,
r25,
r26,
r27,
Z+4,
Z+5,
Z+6,
Z+7,
.+26

0x01
; 1
r24
; 0x01
r3 ; 0x03
r2 ; 0x02
r24
r25
r24
r18
r19
r20
r21
r24
; 0x04
r25
; 0x05
r26
; 0x06
r27
; 0x07
; 0x6ce <_fpadd_parts+0x

6b4:
6b6:
6b8:
6ba:
6bc:
6be:
6c0:
6c2:
6c4:
6c6:
6c8:
6ca:
6cc:
6ce:
6d0:
6d2:
6d4:
6d6:
6d8:
6da:
6dc:
6de:
6e0:
6e2:
6e4:
6e6:
6e8:

22
33
44
55
24
35
46
57
82
93
01
93
82
24
35
46
57
da
c9
01
a1
b1
8f
9f
af
bf
28

0f
1f
1f
1f
83
83
83
83
81
81
97
83
83
81
81
81
81
01
01
97
09
09
5f
4f
4f
43
f3

add
adc
adc
adc
std
std
std
std
ldd
ldd
sbiw
std
std
ldd
ldd
ldd
ldd
movw
movw
sbiw
sbc
sbc
subi
sbci
sbci
sbci
brcs

r18,
r19,
r20,
r21,
Z+4,
Z+5,
Z+6,
Z+7,
r24,
r25,
r24,
Z+3,
Z+2,
r18,
r19,
r20,
r21,
r26,
r24,
r24,
r26,
r27,
r24,
r25,
r26,
r27,
.-54

r18
r19
r20
r21
r18
r19
r20
r21
Z+2
Z+3
0x01
r25
r24
Z+4
Z+5
Z+6
Z+7
r20
r18
0x01
r1
r1
0xFF
0xFF
0xFF
0x3F

6ea:

0b c0

rjmp

.+22

6ec:
6ee:
6f0:
6f2:
6f4:
6f6:
6f8:
6fa:
6fc:
6fe:
700:
702:

91
33
22
ea
fb
0c
1d
e4
f5
06
17
83

std
std
std
add
adc
adc
adc
std
std
std
std
ldi

Z+1,
Z+3,
Z+2,
r14,
r15,
r16,
r17,
Z+4,
Z+5,
Z+6,
Z+7,
r24,

20e>

;
;
;
;
;
;
;
;
;
;
;
;
;

0x04
0x05
0x06
0x07
0x02
0x03
1
0x03
0x02
0x04
0x05
0x06
0x07

; 1
;
;
;
;
;

255
255
255
63
0x6b4 <_fpadd_parts+0x

1f4>
; 0x702 <_fpadd_parts+0x

242>
83
82
82
0c
1c
1d
1d
82
82
83
83
e0

r25
; 0x01
r3 ; 0x03
r2 ; 0x02
r10
r11
r12
r13
r14
; 0x04
r15
; 0x05
r16
; 0x06
r17
; 0x07
0x03
; 3

704:
706:
708:
70a:
70c:
70e:
710:

80
24
35
46
57
57
1a

83
81
81
81
81
ff
c0

st
ldd
ldd
ldd
ldd
sbrs
rjmp

Z, r24
r18, Z+4
r19, Z+5
r20, Z+6
r21, Z+7
r21, 7
.+52

712:
714:
716:
718:
71a:
71c:
71e:
720:
722:
724:
726:
728:
72a:
72c:
72e:
730:
732:
734:
736:
738:
73a:
73c:
73e:
740:
742:
744:
746:
748:

c9
aa
97
a0
ba
81
90
a0
b0
56
47
37
27
82
93
a4
b5
84
95
a6
b7
82
93
01
93
82
df
01

01
27
fd
95
2f
70
70
70
70
95
95
95
95
2b
2b
2b
2b
83
83
83
83
81
81
96
83
83
01
c0

movw
eor
sbrc
com
mov
andi
andi
andi
andi
lsr
ror
ror
ror
or
or
or
or
std
std
std
std
ldd
ldd
adiw
std
std
movw
rjmp

r24,
r26,
r25,
r26
r27,
r24,
r25,
r26,
r27,
r21
r20
r19
r18
r24,
r25,
r26,
r27,
Z+4,
Z+5,
Z+6,
Z+7,
r24,
r25,
r24,
Z+3,
Z+2,
r26,
.+2

74a:
74c:
74e:
750:
752:
754:

d2
cd
cd
de
e2
0c

01
01
b7
b7
e1
94 c4 07

movw
movw
in
in
ldi
jmp

r26, r4
r24, r26
r28, 0x3d
r29, 0x3e
r30, 0x12
0xf88 ; 0xf88

; 61
; 62
; 18
<__epilogue_restores__>

ldi
ldi
ldi
ldi
jmp

r26, 0x20
r27, 0x00
r30, 0xB2
r31, 0x03
0xf68 ; 0xf68

; 32
; 0
; 178
; 3
<__prologue_saves__+0x18

std
std
std
std
std
std
std
std
ldi

Y+1,
Y+2,
Y+3,
Y+4,
Y+5,
Y+6,
Y+7,
Y+8,
r30,

;
;
;
;
;
;
;
;
;

;
;
;
;

0x04
0x05
0x06
0x07

; 0x746 <_fpadd_parts+0x

286>
r18
r26
7
r26
0x01
0x00
0x00
0x00

r18
r19
r20
r21
r24
r25
r26
r27
Z+2
Z+3
0x01
r25
r24
r30

;
;
;
;

1
0
0
0

;
;
;
;
;
;
;
;
;

0x04
0x05
0x06
0x07
0x02
0x03
1
0x03
0x02

; 0x74c <_fpadd_parts+0x

28c>

00000758 <__subsf3>:
758:
a0 e2
75a:
b0 e0
75c:
e2 eb
75e:
f3 e0
760:
0c 94 b4 07
>
764:
69 83
766:
7a 83
768:
8b 83
76a:
9c 83
76c:
2d 83
76e:
3e 83
770:
4f 83
772:
58 87
774:
e9 e0

r22
r23
r24
r25
r18
r19
r20
r21
0x09

0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
9

776:
778:
77a:
77c:
77e:
780:
782:
784:
788:
78a:
78c:
78e:
790:
792:
794:
798:
79a:
79c:
79e:
7a0:
7a2:
7a4:
7a6:
7a8:
7aa:
7ae:
7b2:
7b4:
7b6:

ee
f1
ec
fd
ce
01
b7
0e
8e
0f
1f
ce
05
b8
0e
8a
91
89
8a
c7
b8
ae
47
5f
0e
0e
a0
e6
0c

2e
2c
0e
1e
01
96
01
94
01
5e
4f
01
96
01
94
89
e0
27
8b
01
01
01
5e
4f
94
94
96
e0
94

d7 06

d7 06

60 02
02 06
d0 07

mov
mov
add
adc
movw
adiw
movw
call
movw
subi
sbci
movw
adiw
movw
call
ldd
ldi
eor
std
movw
movw
movw
subi
sbci
call
call
adiw
ldi
jmp

r14, r30
r15, r1
r14, r28
r15, r29
r24, r28
r24, 0x01
r22, r14
0xdae ;
r16, r28
r16, 0xEF
r17, 0xFF
r24, r28
r24, 0x05
r22, r16
0xdae ;
r24, Y+18
r25, 0x01
r24, r25
Y+18, r24
r24, r14
r22, r16
r20, r28
r20, 0xE7
r21, 0xFF
0x4c0 ;
0xc04 ;
r28, 0x20
r30, 0x06
0xfa0 ;

ldi
ldi
ldi
ldi
jmp

r26, 0x20
r27, 0x00
r30, 0xE3
r31, 0x03
0xf68 ; 0xf68

std
std
std
std
std
std
std
std
ldi
mov
mov
add
adc
movw
adiw
movw
call
movw
subi
sbci
movw
adiw

Y+1, r22
; 0x01
Y+2, r23
; 0x02
Y+3, r24
; 0x03
Y+4, r25
; 0x04
Y+5, r18
; 0x05
Y+6, r19
; 0x06
Y+7, r20
; 0x07
Y+8, r21
; 0x08
r31, 0x09
; 9
r14, r31
r15, r1
r14, r28
r15, r29
r24, r28
r24, 0x01
; 1
r22, r14
0xdae ; 0xdae <__unpack_f>
r16, r28
r16, 0xEF
; 239
r17, 0xFF
; 255
r24, r28
r24, 0x05
; 5

; 1
0xdae <__unpack_f>
; 239
; 255
; 5
0xdae <__unpack_f>
; 0x12
; 1
; 0x12

; 231
; 255
0x4c0 <_fpadd_parts>
0xc04 <__pack_f>
; 32
; 6
0xfa0 <__epilogue_restores__+0

x18>
000007ba <__addsf3>:
7ba:
a0 e2
7bc:
b0 e0
7be:
e3 ee
7c0:
f3 e0
7c2:
0c 94 b4 07
>
7c6:
69 83
7c8:
7a 83
7ca:
8b 83
7cc:
9c 83
7ce:
2d 83
7d0:
3e 83
7d2:
4f 83
7d4:
58 87
7d6:
f9 e0
7d8:
ef 2e
7da:
f1 2c
7dc:
ec 0e
7de:
fd 1e
7e0:
ce 01
7e2:
01 96
7e4:
b7 01
7e6:
0e 94 d7 06
7ea:
8e 01
7ec:
0f 5e
7ee:
1f 4f
7f0:
ce 01
7f2:
05 96

; 32
; 0
; 227
; 3
<__prologue_saves__+0x18

7f4:
7f6:
7fa:
7fc:
7fe:
800:
802:
804:
808:
80c:
80e:
810:

b8
0e
c7
b8
ae
47
5f
0e
0e
a0
e6
0c

01
94
01
01
01
5e
4f
94
94
96
e0
94

d7 06

60 02
02 06
d0 07

movw
call
movw
movw
movw
subi
sbci
call
call
adiw
ldi
jmp

r22, r16
0xdae ;
r24, r14
r22, r16
r20, r28
r20, 0xE7
r21, 0xFF
0x4c0 ;
0xc04 ;
r28, 0x20
r30, 0x06
0xfa0 ;

ldi
ldi
ldi
ldi
jmp

r26, 0x18
r27, 0x00
r30, 0x10
r31, 0x04
0xf60 ; 0xf60

std
std
std
std
std
std
std
std
ldi
mov
mov
add
adc
movw
adiw
movw
call
movw
subi
sbci
movw
adiw
movw
call
ldd
cpi
brcc
rjmp
ldd
cpi
brcc
movw
rjmp
ldd
ldd
eor
std
cpi
breq

Y+1, r22
; 0x01
Y+2, r23
; 0x02
Y+3, r24
; 0x03
Y+4, r25
; 0x04
Y+5, r18
; 0x05
Y+6, r19
; 0x06
Y+7, r20
; 0x07
Y+8, r21
; 0x08
r27, 0x09
; 9
r14, r27
r15, r1
r14, r28
r15, r29
r24, r28
r24, 0x01
; 1
r22, r14
0xdae ; 0xdae <__unpack_f>
r16, r28
r16, 0xEF
; 239
r17, 0xFF
; 255
r24, r28
r24, 0x05
; 5
r22, r16
0xdae ; 0xdae <__unpack_f>
r18, Y+9
; 0x09
r18, 0x02
; 2
.+2
; 0x85c <__divsf3+0x48>
.+252
; 0x958 <__stack+0xf9>
r19, Y+17
; 0x11
r19, 0x02
; 2
.+4
; 0x866 <__stack+0x7>
r22, r16
.+248
; 0x95e <__stack+0xff>
r24, Y+10
; 0x0a
r25, Y+18
; 0x12
r24, r25
Y+10, r24
; 0x0a
r18, 0x04
; 4
.+4
; 0x876 <__stack+0x17>

0xdae <__unpack_f>

; 231
; 255
0x4c0 <_fpadd_parts>
0xc04 <__pack_f>
; 32
; 6
0xfa0 <__epilogue_restores__+0

x18>
00000814 <__divsf3>:
814:
a8 e1
816:
b0 e0
818:
e0 e1
81a:
f4 e0
81c:
0c 94 b0 07
>
820:
69 83
822:
7a 83
824:
8b 83
826:
9c 83
828:
2d 83
82a:
3e 83
82c:
4f 83
82e:
58 87
830:
b9 e0
832:
eb 2e
834:
f1 2c
836:
ec 0e
838:
fd 1e
83a:
ce 01
83c:
01 96
83e:
b7 01
840:
0e 94 d7 06
844:
8e 01
846:
0f 5e
848:
1f 4f
84a:
ce 01
84c:
05 96
84e:
b8 01
850:
0e 94 d7 06
854:
29 85
856:
22 30
858:
08 f4
85a:
7e c0
85c:
39 89
85e:
32 30
860:
10 f4
862:
b8 01
864:
7c c0
866:
8a 85
868:
9a 89
86a:
89 27
86c:
8a 87
86e:
24 30
870:
11 f0

; 24
; 0
; 16
; 4
<__prologue_saves__+0x10

872:
874:
876:
878:
87a:
87c:
87e:
880:
882:
884:
886:
888:
88a:
88c:
88e:
890:
892:
894:
896:
898:
89a:
89c:
89e:
8a0:
8a2:
8a4:
8a6:
8a8:
8aa:
8ac:
8ae:
8b0:
8b2:
8b4:
8b6:
8b8:
8ba:
8bc:
8be:
8c0:
8c2:
8c4:
8c6:
8c8:
8ca:
8cc:
8ce:
8d0:
8d2:
8d4:
8d6:
8d8:
8da:
8dc:
8de:
8e0:
8e2:
8e4:
8e6:
8e8:

22
31
23
09
6e
67
70
6e
34
39
1d
1e
1f
18
1c
1b
04
32
21
84
89
b7
5f
2b
3c
8b
9c
28
39
3c
2b
ed
fe
0f
18
ad
be
cf
d8
ea
fb
0c
1d
40
ee
ff
00
11
21
30
3c
2b
20
30
40
50
80
90
a0
b0

30
f4
17
f0
c0
e7
e0
c0
30
f4
86
86
86
8a
86
86
c0
30
f4
e0
87
01
c0
85
85
89
89
1b
0b
87
87
84
84
85
89
88
88
88
8c
14
04
05
05
f4
0c
1c
1f
1f
50
40
87
87
e0
e0
e0
e0
e0
e0
e0
e4

cpi
brne
cp
breq
rjmp
ldi
ldi
rjmp
cpi
brne
std
std
std
std
std
std
rjmp
cpi
brne
ldi
std
movw
rjmp
ldd
ldd
ldd
ldd
sub
sbc
std
std
ldd
ldd
ldd
ldd
ldd
ldd
ldd
ldd
cp
cpc
cpc
cpc
brcc
add
adc
adc
adc
subi
sbci
std
std
ldi
ldi
ldi
ldi
ldi
ldi
ldi
ldi

r18, 0x02
.+12
r18, r19
.+2
.+220
r22, 0x77
r23, 0x00
.+220
r19, 0x04
.+14
Y+13, r1
Y+14, r1
Y+15, r1
Y+16, r1
Y+12, r1
Y+11, r1
.+8
r19, 0x02
.+8
r24, 0x04
Y+9, r24
r22, r14
.+190
r18, Y+11
r19, Y+12
r24, Y+19
r25, Y+20
r18, r24
r19, r25
Y+12, r19
Y+11, r18
r14, Y+13
r15, Y+14
r16, Y+15
r17, Y+16
r10, Y+21
r11, Y+22
r12, Y+23
r13, Y+24
r14, r10
r15, r11
r16, r12
r17, r13
.+16
r14, r14
r15, r15
r16, r16
r17, r17
r18, 0x01
r19, 0x00
Y+12, r19
Y+11, r18
r18, 0x00
r19, 0x00
r20, 0x00
r21, 0x00
r24, 0x00
r25, 0x00
r26, 0x00
r27, 0x40

; 2
; 0x882 <__stack+0x23>
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;

0x87c
0x958
119
0
0x95e
4
0x894
0x0d
0x0e
0x0f
0x10
0x0c
0x0b
0x89c
2
0x8a0
4
0x09

<__stack+0x1d>
<__stack+0xf9>

;
;
;
;
;

0x95e <__stack+0xff>
0x0b
0x0c
0x13
0x14

;
;
;
;
;
;
;
;
;
;

0x0c
0x0b
0x0d
0x0e
0x0f
0x10
0x15
0x16
0x17
0x18

<__stack+0xff>
<__stack+0x35>

<__stack+0x3d>
<__stack+0x41>

; 0x8da <__stack+0x7b>

;
;
;
;
;
;
;
;
;
;
;
;

1
0
0x0c
0x0b
0
0
0
0
0
0
0
64

8ea:
8ec:
8ee:
8f0:
8f2:
8f4:
8f6:
8f8:
8fa:
8fc:
8fe:
900:
902:
904:
906:
908:
90a:
90c:
90e:
910:
912:
914:
916:
918:
91a:
91c:
91e:
920:
922:
924:
926:
928:
92a:
92c:
92e:
930:
932:
934:
936:
938:
93a:
93c:
93e:
940:
942:
944:
946:
948:
94a:
94c:
94e:
950:
952:
954:
956:
958:
95a:
95c:
95e:
960:

60
70
ea
fb
0c
1d
40
28
39
4a
5b
ea
fb
0c
1d
b6
a7
97
87
ee
ff
00
11
6f
7f
6f
71
31
da
c9
8f
90
a0
b0
80
91
a1
b1
61
27
0a
e1
f1
01
11
29
20
3f
4f
5f
20
2d
3e
4f
58
be
67
7f
cb
0e

e0
e0
14
04
05
05
f0
2b
2b
2b
2b
18
08
09
09
95
95
95
95
0c
1c
1f
1f
5f
4f
31
05
f7
01
01
77
70
70
70
34
05
05
05
f4
fd
c0
14
04
05
05
f0
5c
4f
4f
4f
78
87
87
87
8b
01
5f
4f
01
94 02 06

ldi
ldi
cp
cpc
cpc
cpc
brcs
or
or
or
or
sub
sbc
sbc
sbc
lsr
ror
ror
ror
add
adc
adc
adc
subi
sbci
cpi
cpc
brne
movw
movw
andi
andi
andi
andi
cpi
cpc
cpc
cpc
brne
sbrc
rjmp
cp
cpc
cpc
cpc
breq
subi
sbci
sbci
sbci
andi
std
std
std
std
movw
subi
sbci
movw
call

r22, 0x00
r23, 0x00
r14, r10
r15, r11
r16, r12
r17, r13
.+16
r18, r24
r19, r25
r20, r26
r21, r27
r14, r10
r15, r11
r16, r12
r17, r13
r27
r26
r25
r24
r14, r14
r15, r15
r16, r16
r17, r17
r22, 0xFF
r23, 0xFF
r22, 0x1F
r23, r1
.-52
r26, r20
r24, r18
r24, 0x7F
r25, 0x00
r26, 0x00
r27, 0x00
r24, 0x40
r25, r1
r26, r1
r27, r1
.+24
r18, 7
.+20
r14, r1
r15, r1
r16, r1
r17, r1
.+10
r18, 0xC0
r19, 0xFF
r20, 0xFF
r21, 0xFF
r18, 0x80
Y+13, r18
Y+14, r19
Y+15, r20
Y+16, r21
r22, r28
r22, 0xF7
r23, 0xFF
r24, r22
0xc04 ; 0xc04

; 0
; 0

; 0x908 <__stack+0xa9>

; 255
; 255
; 31
; 0x8ee <__stack+0x8f>
;
;
;
;
;

127
0
0
0
64

; 0x950 <__stack+0xf1>
; 0x950 <__stack+0xf1>

;
;
;
;
;
;
;
;
;
;

0x950 <__stack+0xf1>
192
255
255
255
128
0x0d
0x0e
0x0f
0x10

; 247
; 255
<__pack_f>

964:
966:
968:

68 96
ea e0
0c 94 cc 07

adiw
ldi
jmp

r28, 0x18
; 24
r30, 0x0A
; 10
0xf98 ; 0xf98 <__epilogue_restores__+0

ldi
ldi
ldi
ldi
jmp

r26, 0x18
r27, 0x00
r30, 0xBC
r31, 0x04
0xf68 ; 0xf68

; 24
; 0
; 188
; 4
<__prologue_saves__+0x18

std
std
std
std
std
std
std
std
ldi
mov
mov
add
adc
movw
adiw
movw
call
movw
subi
sbci
movw
adiw
movw
call
ldd
cpi
brcs
ldd
cpi
brcs
movw
movw
call
rjmp
ldi
adiw
ldi
jmp

Y+1, r22
Y+2, r23
Y+3, r24
Y+4, r25
Y+5, r18
Y+6, r19
Y+7, r20
Y+8, r21
r24, 0x09
r14, r24
r15, r1
r14, r28
r15, r29
r24, r28
r24, 0x01
r22, r14
0xdae ;
r16, r28
r16, 0xEF
r17, 0xFF
r24, r28
r24, 0x05
r22, r16
0xdae ;
r24, Y+9
r24, 0x02
.+16
r24, Y+17
r24, 0x02
.+10
r24, r14
r22, r16
0xe9e ;
.+2
r24, 0xFF
r28, 0x18
r30, 0x06
0xfa0 ;

;
;
;
;
;
;
;
;
;

ldi
ldi
ldi
ldi
jmp

r26, 0x0C
r27, 0x00
r30, 0xEC
r31, 0x04
0xf70 ; 0xf70

; 12
; 0
; 236
; 4
<__prologue_saves__+0x20

std

Y+1, r22

; 0x01

x10>
0000096c <__gesf2>:
96c:
a8 e1
96e:
b0 e0
970:
ec eb
972:
f4 e0
974:
0c 94
>
978:
69 83
97a:
7a 83
97c:
8b 83
97e:
9c 83
980:
2d 83
982:
3e 83
984:
4f 83
986:
58 87
988:
89 e0
98a:
e8 2e
98c:
f1 2c
98e:
ec 0e
990:
fd 1e
992:
ce 01
994:
01 96
996:
b7 01
998:
0e 94
99c:
8e 01
99e:
0f 5e
9a0:
1f 4f
9a2:
ce 01
9a4:
05 96
9a6:
b8 01
9a8:
0e 94
9ac:
89 85
9ae:
82 30
9b0:
40 f0
9b2:
89 89
9b4:
82 30
9b6:
28 f0
9b8:
c7 01
9ba:
b8 01
9bc:
0e 94
9c0:
01 c0
9c2:
8f ef
9c4:
68 96
9c6:
e6 e0
9c8:
0c 94
x18>

b4 07

d7 06

d7 06

4f 07

d0 07

000009cc <__fixsfsi>:
9cc:
ac e0
9ce:
b0 e0
9d0:
ec ee
9d2:
f4 e0
9d4:
0c 94 b8 07
>
9d8:
69 83

0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
9

; 1
0xdae <__unpack_f>
; 239
; 255
; 5
0xdae <__unpack_f>
; 0x09
; 2
; 0x9c2 <__gesf2+0x56>
; 0x11
; 2
; 0x9c2 <__gesf2+0x56>
0xe9e <__fpcmp_parts_f>
; 0x9c4 <__gesf2+0x58>
; 255
; 24
; 6
0xfa0 <__epilogue_restores__+0

9da:
9dc:
9de:
9e0:
9e2:
9e4:
9e6:
9e8:
9ea:
9ee:
9f0:
9f2:
9f4:
9f6:
9f8:
9fa:
9fc:
9fe:
a00:
a02:
a04:
a06:
a08:
a0a:
a0c:
a0e:
a10:
a12:
a14:
a16:
a18:
a1a:
a1c:
a1e:
a20:
a22:
a24:
a26:
a28:
a2a:
a2c:
a2e:
a30:
a32:
a34:
a36:
a38:
a3a:
a3c:
a3e:
a40:
a42:
a44:
a46:
a48:
a4a:
a4c:
a4e:
a50:
a52:

7a
8b
9c
ce
01
be
6b
7f
0e
8d
82
61
82
50
84
21
8e
88
51
2e
2f
38
37
20
6e
2f
31
1c
66
f9
23
8e
90
82
93
29
3a
4b
5c
04
56
47
37
27
8a
d2
66
b1
50
40
30
21
3f
4f
5f
0e
20
30
40
50

83
83
83
01
96
01
5f
4f
94 d7 06
81
30
f1
30
f1
30
f4
81
23
f1
c0
81
85
fd
c0
81
31
05
f0
23
f0
c0
e1
e0
1b
0b
85
85
85
85
c0
95
95
95
95
95
f7
23
f0
95
95
95
95
4f
4f
4f
c0
e0
e0
e0
e0

std
std
std
movw
adiw
movw
subi
sbci
call
ldd
cpi
breq
cpi
brcs
cpi
brne
ldd
and
breq
rjmp
ldd
ldd
sbrc
rjmp
ldd
cpi
cpc
brlt
and
breq
rjmp
ldi
ldi
sub
sbc
ldd
ldd
ldd
ldd
rjmp
lsr
ror
ror
ror
dec
brpl
and
breq
com
com
com
neg
sbci
sbci
sbci
rjmp
ldi
ldi
ldi
ldi

Y+2, r23
; 0x02
Y+3, r24
; 0x03
Y+4, r25
; 0x04
r24, r28
r24, 0x01
; 1
r22, r28
r22, 0xFB
; 251
r23, 0xFF
; 255
0xdae ; 0xdae <__unpack_f>
r24, Y+5
; 0x05
r24, 0x02
; 2
.+88
; 0xa4c <__fixsfsi+0x80>
r24, 0x02
; 2
.+84
; 0xa4c <__fixsfsi+0x80>
r24, 0x04
; 4
.+8
; 0xa04 <__fixsfsi+0x38>
r24, Y+6
; 0x06
r24, r24
.+84
; 0xa56 <__fixsfsi+0x8a>
.+92
; 0xa60 <__fixsfsi+0x94>
r18, Y+7
; 0x07
r19, Y+8
; 0x08
r19, 7
.+64
; 0xa4c <__fixsfsi+0x80>
r22, Y+6
; 0x06
r18, 0x1F
; 31
r19, r1
.+6
; 0xa1a <__fixsfsi+0x4e>
r22, r22
.+62
; 0xa56 <__fixsfsi+0x8a>
.+70
; 0xa60 <__fixsfsi+0x94>
r24, 0x1E
; 30
r25, 0x00
; 0
r24, r18
r25, r19
r18, Y+9
; 0x09
r19, Y+10
; 0x0a
r20, Y+11
; 0x0b
r21, Y+12
; 0x0c
.+8
; 0xa34 <__fixsfsi+0x68>
r21
r20
r19
r18
r24
.-12
; 0xa2c <__fixsfsi+0x60>
r22, r22
.+44
; 0xa68 <__fixsfsi+0x9c>
r21
r20
r19
r18
r19, 0xFF
; 255
r20, 0xFF
; 255
r21, 0xFF
; 255
.+28
; 0xa68 <__fixsfsi+0x9c>
r18, 0x00
; 0
r19, 0x00
; 0
r20, 0x00
; 0
r21, 0x00
; 0

a54:
a56:
a58:
a5a:
a5c:
a5e:
a60:
a62:
a64:
a66:
a68:
a6a:
a6c:
a6e:
a70:

09
2f
3f
4f
5f
04
20
30
40
50
b9
ca
2c
e2
0c

c0
ef
ef
ef
e7
c0
e0
e0
e0
e8
01
01
96
e0
94 d4 07

rjmp
ldi
ldi
ldi
ldi
rjmp
ldi
ldi
ldi
ldi
movw
movw
adiw
ldi
jmp

.+18
r18, 0xFF
r19, 0xFF
r20, 0xFF
r21, 0x7F
.+8
r18, 0x00
r19, 0x00
r20, 0x00
r21, 0x80
r22, r18
r24, r20
r28, 0x0c
r30, 0x02
0xfa8 ; 0xfa8

;
;
;
;
;
;
;
;
;
;

0xa68 <__fixsfsi+0x9c>
255
255
255
127
0xa68 <__fixsfsi+0x9c>
0
0
0
128

ldi
ldi
ldi
ldi
jmp

r26, 0x08
r27, 0x00
r30, 0x40
r31, 0x05
0xf60 ; 0xf60

; 8
; 0
; 64
; 5
<__prologue_saves__+0x10

movw
movw
cp
cpc
cpc
cpc
brne

r14,
r16,
r22,
r23,
r24,
r25,
.+6

; 0xa94 <__floatunsisf+0

ldi
std
rjmp

r24, 0x02
Y+1, r24
.+192

ldi
std
ldi
mov
mov
std
std
std
std
std
std
movw
movw
call
movw
sbiw
sbrs
rjmp

r24, 0x03
; 3
Y+1, r24
; 0x01
r24, 0x1E
; 30
r12, r24
r13, r1
Y+4, r13
; 0x04
Y+3, r12
; 0x03
Y+5, r14
; 0x05
Y+6, r15
; 0x06
Y+7, r16
; 0x07
Y+8, r17
; 0x08
r24, r16
r22, r14
0xb66 ; 0xb66 <__clzsi2>
r30, r24
r30, 0x01
; 1
r31, 7
.+118
; 0xb30 <__floatunsisf+0

eor
eor
sub
sbc
movw

r18,
r19,
r18,
r19,
r10,

; 12
; 2
<__epilogue_restores__+0

x20>
00000a74 <__floatunsisf>:
a74:
a8 e0
a76:
b0 e0
a78:
e0 e4
a7a:
f5 e0
a7c:
0c 94 b0 07
>
a80:
7b 01
a82:
8c 01
a84:
61 15
a86:
71 05
a88:
81 05
a8a:
91 05
a8c:
19 f4
x20>
a8e:
82 e0
a90:
89 83
a92:
60 c0
xe0>
a94:
83 e0
a96:
89 83
a98:
8e e1
a9a:
c8 2e
a9c:
d1 2c
a9e:
dc 82
aa0:
cb 82
aa2:
ed 82
aa4:
fe 82
aa6:
0f 83
aa8:
18 87
aaa:
c8 01
aac:
b7 01
aae:
0e 94 b3 05
ab2:
fc 01
ab4:
31 97
ab6:
f7 ff
ab8:
3b c0
xbc>
aba:
22 27
abc:
33 27
abe:
2e 1b
ac0:
3f 0b
ac2:
57 01

r22
r24
r1
r1
r1
r1

r18
r19
r30
r31
r14

; 2
; 0x01
; 0xb54 <__floatunsisf+0

ac4:
ac6:
ac8:

68 01
02 2e
04 c0

movw
mov
rjmp

r12, r16
r0, r18
.+8

; 0xad2 <__floatunsisf+0

aca:
acc:
ace:
ad0:
ad2:
ad4:

d6
c7
b7
a7
0a
d2

94
94
94
94
94
f7

lsr
ror
ror
ror
dec
brpl

r13
r12
r11
r10
r0
.-12

; 0xaca <__floatunsisf+0

ad6:
ad8:
ada:
adc:
ade:
ae0:
ae2:
ae4:
ae6:

40
50
60
70
81
90
a0
b0
04

e0
e0
e0
e0
e0
e0
e0
e0
c0

ldi
ldi
ldi
ldi
ldi
ldi
ldi
ldi
rjmp

r20,
r21,
r22,
r23,
r24,
r25,
r26,
r27,
.+8

0x00
0x00
0x00
0x00
0x01
0x00
0x00
0x00

ae8:
aea:
aec:
aee:
af0:
af2:

88
99
aa
bb
2a
d2

0f
1f
1f
1f
95
f7

add
adc
adc
adc
dec
brpl

r24,
r25,
r26,
r27,
r18
.-12

r24
r25
r26
r27

af4:
af6:
af8:
afa:
afc:
afe:
b00:
b02:
b04:
b06:
b08:

01
a1
b1
8e
9f
a0
b1
00
a1
b1
21

97
09
09
21
21
23
23
97
05
05
f0

sbiw
sbc
sbc
and
and
and
and
sbiw
cpc
cpc
breq

r24,
r26,
r27,
r24,
r25,
r26,
r27,
r24,
r26,
r27,
.+8

0x01
r1
r1
r14
r15
r16
r17
0x00
r1
r1

b0a:
b0c:
b0e:
b10:
b12:
b14:
b16:
b18:
b1a:
b1c:
b1e:
b20:
b22:
b24:
b26:
b28:
b2a:
b2c:
b2e:

41
50
60
70
4a
5b
6c
7d
4d
5e
6f
78
8e
90
8e
9f
9c
8b
12

e0
e0
e0
e0
29
29
29
29
83
83
83
87
e1
e0
1b
0b
83
83
c0

ldi
ldi
ldi
ldi
or
or
or
or
std
std
std
std
ldi
ldi
sub
sbc
std
std
rjmp

r20,
r21,
r22,
r23,
r20,
r21,
r22,
r23,
Y+5,
Y+6,
Y+7,
Y+8,
r24,
r25,
r24,
r25,
Y+4,
Y+3,
.+36

0x01
0x00
0x00
0x00
r10
r11
r12
r13
r20
r21
r22
r23
0x1E
0x00
r30
r31
r25
r24

x5e>

x56>
;
;
;
;
;
;
;
;
;

0
0
0
0
1
0
0
0
0xaf0 <__floatunsisf+0

x7c>

; 0xae8 <__floatunsisf+0

x74>
; 1

; 0
; 0xb12 <__floatunsisf+0

x9e>

xe0>

;
;
;
;

1
0
0
0

;
;
;
;
;
;

0x05
0x06
0x07
0x08
30
0

; 0x04
; 0x03
; 0xb54 <__floatunsisf+0

b30:
b32:

30 97
81 f0

sbiw
breq

r30, 0x00
.+32

; 0
; 0xb54 <__floatunsisf+0

b34:
b36:

0e 2e
04 c0

mov
rjmp

r0, r30
.+8

; 0xb40 <__floatunsisf+0

b38:
b3a:
b3c:
b3e:
b40:
b42:

ee
ff
00
11
0a
d2

0c
1c
1f
1f
94
f7

add
adc
adc
adc
dec
brpl

r14,
r15,
r16,
r17,
r0
.-12

; 0xb38 <__floatunsisf+0

b44:
b46:
b48:
b4a:
b4c:
b4e:
b50:
b52:
b54:
b56:
b58:
b5a:
b5e:
b60:
b62:

ed
fe
0f
18
ce
df
dc
cb
1a
ce
01
0e
28
ea
0c

82
82
83
87
1a
0a
82
82
82
01
96
94 02 06
96
e0
94 cc 07

std
std
std
std
sub
sbc
std
std
std
movw
adiw
call
adiw
ldi
jmp

Y+5, r14
; 0x05
Y+6, r15
; 0x06
Y+7, r16
; 0x07
Y+8, r17
; 0x08
r12, r30
r13, r31
Y+4, r13
; 0x04
Y+3, r12
; 0x03
Y+2, r1 ; 0x02
r24, r28
r24, 0x01
; 1
0xc04 ; 0xc04 <__pack_f>
r28, 0x08
; 8
r30, 0x0A
; 10
0xf98 ; 0xf98 <__epilogue_restores__+0

push
push
push
push
movw
movw
ldi
cp
ldi
cpc
ldi
cpc
ldi
cpc
brcc
ldi
cp
cpc
cpc
cpc
breq
brcs
ldi
ldi
ldi
ldi
rjmp
ldi
ldi

r14
r15
r16
r17
r14,
r16,
r24,
r14,
r24,
r15,
r24,
r16,
r24,
r17,
.+34
r24,
r14,
r15,
r16,
r17,
.+12
.+10
r24,
r25,
r26,
r27,
.+46
r24,
r25,

xe0>
xcc>
r14
r15
r16
r17

xc4>

x10>
00000b66 <__clzsi2>:
b66:
ef 92
b68:
ff 92
b6a:
0f 93
b6c:
1f 93
b6e:
7b 01
b70:
8c 01
b72:
80 e0
b74:
e8 16
b76:
80 e0
b78:
f8 06
b7a:
81 e0
b7c:
08 07
b7e:
80 e0
b80:
18 07
b82:
88 f4
b84:
8f ef
b86:
e8 16
b88:
f1 04
b8a:
01 05
b8c:
11 05
b8e:
31 f0
b90:
28 f0
b92:
88 e0
b94:
90 e0
b96:
a0 e0
b98:
b0 e0
b9a:
17 c0
b9c:
80 e0
b9e:
90 e0

r22
r24
0x00
r24
0x00
r24
0x01
r24
0x00
r24
0xFF
r24
r1
r1
r1
0x08
0x00
0x00
0x00
0x00
0x00

; 0
; 0
; 1
; 0
; 0xba6 <__clzsi2+0x40>
; 255

;
;
;
;
;
;
;
;
;

0xb9c <__clzsi2+0x36>
0xb9c <__clzsi2+0x36>
8
0
0
0
0xbca <__clzsi2+0x64>
0
0

ba0:
ba2:
ba4:
ba6:
ba8:
baa:
bac:
bae:
bb0:
bb2:
bb4:
bb6:
bb8:
bba:
bbc:
bbe:
bc0:
bc2:
bc4:
bc6:
bc8:
bca:
bcc:
bce:
bd0:
bd2:
bd4:
bd6:
bd8:
bda:
bdc:
bde:
be0:
be2:
be4:
be6:
be8:
bea:
bec:
bee:
bf0:
bf2:
bf4:
bf6:
bf8:
bfa:
bfc:
bfe:
c00:
c02:

a0
b0
12
80
e8
80
f8
80
08
81
18
28
88
90
a0
b0
04
80
90
a0
b0
20
30
40
50
28
39
4a
5b
04
16
07
f7
e7
8a
d2
f7
e1
ff
80
28
31
41
51
c9
1f
0f
ff
ef
08

e0
e0
c0
e0
16
e0
06
e0
07
e0
07
f0
e1
e0
e0
e0
c0
e1
e0
e0
e0
e2
e0
e0
e0
1b
0b
0b
0b
c0
95
95
94
94
95
f7
01
58
4f
81
1b
09
09
09
01
91
91
90
90
95

ldi
ldi
rjmp
ldi
cp
ldi
cpc
ldi
cpc
ldi
cpc
brcs
ldi
ldi
ldi
ldi
rjmp
ldi
ldi
ldi
ldi
ldi
ldi
ldi
ldi
sub
sbc
sbc
sbc
rjmp
lsr
ror
ror
ror
dec
brpl
movw
subi
sbci
ld
sub
sbc
sbc
sbc
movw
pop
pop
pop
pop
ret

r26,
r27,
.+36
r24,
r14,
r24,
r15,
r24,
r16,
r24,
r17,
.+10
r24,
r25,
r26,
r27,
.+8
r24,
r25,
r26,
r27,
r18,
r19,
r20,
r21,
r18,
r19,
r20,
r21,
.+8
r17
r16
r15
r14
r24
.-12
r30,
r30,
r31,
r24,
r18,
r19,
r20,
r21,
r24,
r17
r16
r15
r14

0x00
0x00

00000c04 <__pack_f>:
c04:
df 92
c06:
ef 92
c08:
ff 92
c0a:
0f 93
c0c:
1f 93
c0e:
fc 01
c10:
e4 80
c12:
f5 80

push
push
push
push
push
movw
ldd
ldd

r13
r14
r15
r16
r17
r30, r24
r14, Z+4
r15, Z+5

0x00
r24
0x00
r24
0x00
r24
0x01
r24
0x18
0x00
0x00
0x00
0x10
0x00
0x00
0x00
0x20
0x00
0x00
0x00
r24
r25
r26
r27

;
;
;
;

0
0
0xbca <__clzsi2+0x64>
0

; 0
; 0
; 1
;
;
;
;
;
;
;
;
;
;
;
;
;
;

0xbc2 <__clzsi2+0x5c>
24
0
0
0
0xbca <__clzsi2+0x64>
16
0
0
0
32
0
0
0

; 0xbe4 <__clzsi2+0x7e>

; 0xbdc <__clzsi2+0x76>
r14
0x81
0xFF
Z
r24
r1
r1
r1
r18

; 129
; 255

; 0x04
; 0x05

c14:
c16:
c18:
c1a:
c1c:
c1e:
c20:
c22:
c24:
c26:
c28:
c2a:
c2c:
c2e:
c30:
c32:
c34:
c36:
c38:
c3a:
c3c:
c3e:
c40:
c42:
c44:
c46:
c48:
c4a:
c4c:
c4e:
c50:
c52:
c54:
c56:
c58:
c5a:
c5c:
c5e:
c60:
c62:
c64:
c66:
c68:
c6a:
c6c:
c6e:
c70:
c72:
c74:
c76:
c78:
c7a:
c7c:
c7e:
c80:
c82:
c84:
c86:
c88:
c8a:

06
17
d1
80
82
48
80
90
a0
b0
e8
f9
0a
1b
a5
84
09
9f
82
21
ee
ff
87
05
e1
f1
01
11
19
e0
f0
96
62
73
9f
62
79
0c
5b
22
3f
26
37
2a
31
2c
20
30
40
50
2a
b8
a7
02
04
76
67
57
47
0a

81
81
80
81
30
f4
e0
e0
e1
e0
2a
2a
2b
2b
c0
30
f4
c0
30
f4
24
24
01
c0
14
04
05
05
f4
e0
e0
c0
81
81
ef
38
07
f0
c0
e8
ef
1b
0b
31
05
f0
e0
e0
e0
e0
c0
01
01
2e
c0
95
95
95
95
94

ldd
ldd
ldd
ld
cpi
brcc
ldi
ldi
ldi
ldi
or
or
or
or
rjmp
cpi
brne
rjmp
cpi
brne
eor
eor
movw
rjmp
cp
cpc
cpc
cpc
brne
ldi
ldi
rjmp
ldd
ldd
ldi
cpi
cpc
brlt
rjmp
ldi
ldi
sub
sbc
cpi
cpc
brlt
ldi
ldi
ldi
ldi
rjmp
movw
movw
mov
rjmp
lsr
ror
ror
ror
dec

r16, Z+6
r17, Z+7
r13, Z+1
r24, Z
r24, 0x02
.+18
r24, 0x00
r25, 0x00
r26, 0x10
r27, 0x00
r14, r24
r15, r25
r16, r26
r17, r27
.+330
r24, 0x04
.+2
.+318
r24, 0x02
.+8
r14, r14
r15, r15
r16, r14
.+10
r14, r1
r15, r1
r16, r1
r17, r1
.+6
r30, 0x00
r31, 0x00
.+300
r22, Z+2
r23, Z+3
r25, 0xFF
r22, 0x82
r23, r25
.+2
.+182
r18, 0x82
r19, 0xFF
r18, r22
r19, r23
r18, 0x1A
r19, r1
.+10
r18, 0x00
r19, 0x00
r20, 0x00
r21, 0x00
.+84
r22, r16
r20, r14
r0, r18
.+8
r23
r22
r21
r20
r0

; 0x06
; 0x07
; 0x01
;
;
;
;
;
;

2
0xc32 <__pack_f+0x2e>
0
0
16
0

;
;
;
;
;
;

0xd7c
4
0xc38
0xd76
2
0xc44

<__pack_f+0x178>
<__pack_f+0x34>
<__pack_f+0x172>
<__pack_f+0x40>

; 0xc4e <__pack_f+0x4a>

;
;
;
;
;
;
;
;

0xc54 <__pack_f+0x50>
0
0
0xd80 <__pack_f+0x17c>
0x02
0x03
255
130

;
;
;
;

0xc62 <__pack_f+0x5e>
0xd18 <__pack_f+0x114>
130
255

; 26
;
;
;
;
;
;

0xc7a <__pack_f+0x76>
0
0
0
0
0xcce <__pack_f+0xca>

; 0xc8a <__pack_f+0x86>

c8c:
c8e:
c90:
c92:
c94:
c96:
c98:
c9a:
c9c:
c9e:
ca0:
ca2:
ca4:
ca6:
ca8:
caa:
cac:
cae:
cb0:
cb2:
cb4:
cb6:
cb8:
cba:
cbc:
cbe:
cc0:
cc2:
cc4:
cc6:
cc8:
cca:
ccc:
cce:
cd0:
cd2:
cd4:
cd6:
cd8:
cda:
cdc:
cde:
ce0:
ce2:
ce4:
ce6:
ce8:
cea:
cec:
cee:
cf0:
cf2:
cf4:
cf6:
cf8:
cfa:
cfc:
cfe:
d00:
d02:

d2
81
90
a0
b0
04
88
99
aa
bb
2a
d2
01
a1
b1
8e
9f
a0
b1
00
a1
b1
21
81
90
a0
b0
9a
ab
28
39
4a
5b
da
c9
8f
90
a0
b0
80
91
a1
b1
39
27
09
20
3f
4f
5f
04
21
3f
4f
5f
e0
f0
20
a0
3a

f7
e0
e0
e0
e0
c0
0f
1f
1f
1f
95
f7
97
09
09
21
21
23
23
97
05
05
f0
e0
e0
e0
e0
01
01
2b
2b
2b
2b
01
01
77
70
70
70
34
05
05
05
f4
ff
c0
5c
4f
4f
4f
c0
5c
4f
4f
4f
e0
e0
30
e0
07

brpl
ldi
ldi
ldi
ldi
rjmp
add
adc
adc
adc
dec
brpl
sbiw
sbc
sbc
and
and
and
and
sbiw
cpc
cpc
breq
ldi
ldi
ldi
ldi
movw
movw
or
or
or
or
movw
movw
andi
andi
andi
andi
cpi
cpc
cpc
cpc
brne
sbrs
rjmp
subi
sbci
sbci
sbci
rjmp
subi
sbci
sbci
sbci
ldi
ldi
cpi
ldi
cpc

.-12
r24,
r25,
r26,
r27,
.+8
r24,
r25,
r26,
r27,
r18
.-12
r24,
r26,
r27,
r24,
r25,
r26,
r27,
r24,
r26,
r27,
.+8
r24,
r25,
r26,
r27,
r18,
r20,
r18,
r19,
r20,
r21,
r26,
r24,
r24,
r25,
r26,
r27,
r24,
r25,
r26,
r27,
.+14
r18,
.+18
r18,
r19,
r20,
r21,
.+8
r18,
r19,
r20,
r21,
r30,
r31,
r18,
r26,
r19,

0x01
0x00
0x00
0x00

;
;
;
;
;
;

0xc82 <__pack_f+0x7e>
1
0
0
0
0xca0 <__pack_f+0x9c>

r24
r25
r26
r27
0x01
r1
r1
r14
r15
r16
r17
0x00
r1
r1
0x01
0x00
0x00
0x00
r20
r22
r24
r25
r26
r27
r20
r18
0x7F
0x00
0x00
0x00
0x40
r1
r1
r1

; 0xc98 <__pack_f+0x94>
; 1

; 0
;
;
;
;
;

0xcc2 <__pack_f+0xbe>
1
0
0
0

;
;
;
;
;

127
0
0
0
64

; 0xcf2 <__pack_f+0xee>
7
0xC0
0xFF
0xFF
0xFF
0xC1
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
r26

;
;
;
;
;
;
;
;
;
;
;
;
;
;

0xcfa <__pack_f+0xf6>
192
255
255
255
0xcfa <__pack_f+0xf6>
193
255
255
255
0
0
0
0

d04:
d06:
d08:
d0a:
d0c:
d0e:
d10:
d12:
d14:
d16:
d18:
d1a:
d1c:
d1e:
d20:
d22:
d24:
d26:
d28:
d2a:
d2c:
d2e:
d30:
d32:
d34:
d36:
d38:
d3a:
d3c:
d3e:
d40:
d42:
d44:
d46:
d48:
d4a:
d4c:
d4e:
d50:
d52:
d54:
d56:
d58:
d5a:
d5c:
d5e:
d60:
d62:
d64:
d66:
d68:
d6a:
d6c:
d6e:
d70:
d72:
d74:
d76:
d78:
d7a:

a0
4a
a0
5a
10
e1
f0
79
8a
27
60
71
64
fb
e1
ff
d8
c7
8f
90
a0
b0
80
91
a1
b1
39
e7
0d
80
90
a0
b0
04
8f
90
a0
b0
e8
f9
0a
1b
17
05
16
07
f7
e7
31
87
16
07
f7
e7
8a
d1
05
ee
ff
87

e0
07
e4
07
f0
e0
e0
01
01
c0
38
05
f5
01
58
4f
01
01
77
70
70
70
34
05
05
05
f4
fe
c0
e4
e0
e0
e0
c0
e3
e0
e0
e0
0e
1e
1f
1f
ff
c0
95
95
94
94
96
e0
95
95
94
94
95
f7
c0
24
24
01

ldi
cpc
ldi
cpc
brcs
ldi
ldi
movw
movw
rjmp
cpi
cpc
brge
movw
subi
sbci
movw
movw
andi
andi
andi
andi
cpi
cpc
cpc
cpc
brne
sbrs
rjmp
ldi
ldi
ldi
ldi
rjmp
ldi
ldi
ldi
ldi
add
adc
adc
adc
sbrs
rjmp
lsr
ror
ror
ror
adiw
ldi
lsr
ror
ror
ror
dec
brne
rjmp
eor
eor
movw

r26,
r20,
r26,
r21,
.+4
r30,
r31,
r14,
r16,
.+78
r22,
r23,
.+88
r30,
r30,
r31,
r26,
r24,
r24,
r25,
r26,
r27,
r24,
r25,
r26,
r27,
.+14
r14,
.+26
r24,
r25,
r26,
r27,
.+8
r24,
r25,
r26,
r27,
r14,
r15,
r16,
r17,
r17,
.+10
r17
r16
r15
r14
r30,
r24,
r17
r16
r15
r14
r24
.-12
.+10
r14,
r15,
r16,

0x00
r26
0x40
r26
0x01
0x00
r18
r20
0x80
r1

; 0
; 64
; 0xd12 <__pack_f+0x10e>
; 1
; 0
; 0xd66 <__pack_f+0x162>
; 128
; 0xd76 <__pack_f+0x172>

r22
0x81
0xFF
r16
r14
0x7F
0x00
0x00
0x00
0x40
r1
r1
r1

; 129
; 255
;
;
;
;
;

127
0
0
0
64

; 0xd48 <__pack_f+0x144>
7
0x40
0x00
0x00
0x00
0x3F
0x00
0x00
0x00
r24
r25
r26
r27
7

;
;
;
;
;
;
;
;
;
;

0xd58 <__pack_f+0x154>
64
0
0
0
0xd50 <__pack_f+0x14c>
63
0
0
0

; 0xd66 <__pack_f+0x162>

0x01
0x07

; 1
; 7

; 0xd68 <__pack_f+0x164>
; 0xd80 <__pack_f+0x17c>
r14
r15
r14

d7c:
d7e:
d80:
d82:
d84:
d86:
d88:
d8a:
d8c:
d8e:
d90:
d92:
d94:
d96:
d98:
d9a:
d9c:
d9e:
da0:
da2:
da4:
da6:
da8:
daa:
dac:

ef
f0
6e
67
66
67
90
9f
d7
dd
d7
8e
86
49
46
58
5d
b7
ca
1f
0f
ff
ef
df
08

ef
e0
2f
95
27
95
2f
77
94
24
94
2f
95
2f
2b
2f
29
01
01
91
91
90
90
90
95

00000dae <__unpack_f>:
dae:
fc 01
db0:
db 01
db2:
40 81
db4:
51 81
db6:
22 81
db8:
62 2f
dba:
6f 77
dbc:
70 e0
dbe:
22 1f
dc0:
22 27
dc2:
22 1f
dc4:
93 81
dc6:
89 2f
dc8:
88 0f
dca:
82 2b
dcc:
28 2f
dce:
30 e0
dd0:
99 1f
dd2:
99 27
dd4:
99 1f
dd6:
11 96
dd8:
9c 93
dda:
11 97
ddc:
21 15
dde:
31 05
de0:
a9 f5
>
de2:
41 15
de4:
51 05
de6:
61 05
de8:
71 05
dea:
11 f4
>

ldi
ldi
mov
ror
eor
ror
mov
andi
ror
eor
ror
mov
lsr
mov
or
mov
or
movw
movw
pop
pop
pop
pop
pop
ret

r30,
r31,
r22,
r22
r22,
r22
r25,
r25,
r13
r13,
r13
r24,
r24
r20,
r20,
r21,
r21,
r22,
r24,
r17
r16
r15
r14
r13

0xFF
0x00
r30

movw
movw
ld
ldd
ldd
mov
andi
ldi
adc
eor
adc
ldd
mov
add
or
mov
ldi
adc
eor
adc
adiw
st
sbiw
cp
cpc
brne

r30, r24
r26, r22
r20, Z
r21, Z+1
r18, Z+2
r22, r18
r22, 0x7F
r23, 0x00
r18, r18
r18, r18
r18, r18
r25, Z+3
r24, r25
r24, r24
r24, r18
r18, r24
r19, 0x00
r25, r25
r25, r25
r25, r25
r26, 0x01
X, r25
r26, 0x01
r18, r1
r19, r1
.+106

cp
cpc
cpc
cpc
brne

r20,
r21,
r22,
r23,
.+4

; 255
; 0

r22
r16
0x7F

; 127

r13
r30
r25
r22
r24
r13
r14
r20

; 0x01
; 0x02
; 127
; 0

; 0x03

; 0

; 1
; 1
; 0xe4c <__unpack_f+0x9e

r1
r1
r1
r1
; 0xdf0 <__unpack_f+0x42

dec:
dee:

82 e0
37 c0

ldi
rjmp

r24, 0x02
.+110

; 2
; 0xe5e <__unpack_f+0xb0

df0:
df2:
df4:
df6:
df8:
dfa:
dfc:
dfe:
e00:
e02:
e04:
e06:
e08:
e0a:
e0c:

82
9f
13
9c
8e
12
9a
ab
67
22
33
44
55
6a
d1

e8
ef
96
93
93
97
01
01
e0
0f
1f
1f
1f
95
f7

ldi
ldi
adiw
st
st
sbiw
movw
movw
ldi
add
adc
adc
adc
dec
brne

r24, 0x82
r25, 0xFF
r26, 0x03
X, r25
-X, r24
r26, 0x02
r18, r20
r20, r22
r22, 0x07
r18, r18
r19, r19
r20, r20
r21, r21
r22
.-12

; 130
; 255
; 3

e0e:
e10:
e12:

83 e0
8c 93
0d c0

ldi
st
rjmp

r24, 0x03
X, r24
.+26

; 3

e14:
e16:
e18:
e1a:
e1c:
e1e:
e20:
e22:
e24:
e26:
e28:
e2a:
e2c:
e2e:
e30:
e32:
e34:
e36:
e38:
e3a:
e3c:

22
33
44
55
12
8d
9c
13
01
13
9c
8e
12
20
80
38
80
48
80
58
58

0f
1f
1f
1f
96
91
91
97
97
96
93
93
97
30
e0
07
e0
07
e4
07
f3

add
adc
adc
adc
adiw
ld
ld
sbiw
sbiw
adiw
st
st
sbiw
cpi
ldi
cpc
ldi
cpc
ldi
cpc
brcs

r18, r18
r19, r19
r20, r20
r21, r21
r26, 0x02
r24, X+
r25, X
r26, 0x03
r24, 0x01
r26, 0x03
X, r25
-X, r24
r26, 0x02
r18, 0x00
r24, 0x00
r19, r24
r24, 0x00
r20, r24
r24, 0x40
r21, r24
.-42

e3e:
e40:
e42:
e44:
e46:
e48:
e4a:
e4c:
e4e:
e50:

14
2d
3d
4d
5c
17
08
2f
31
79

96
93
93
93
93
97
95
3f
05
f4

adiw
st
st
st
st
sbiw
ret
cpi
cpc
brne

r26, 0x04
X+, r18
X+, r19
X+, r20
X, r21
r26, 0x07

; 4

r18, 0xFF
r19, r1
.+30

; 255

e52:
e54:
e56:
e58:

41
51
61
71

15
05
05
05

cp
cpc
cpc
cpc

r20,
r21,
r22,
r23,

>

; 2
; 7

; 0xe02 <__unpack_f+0x54

>
; 0xe2e <__unpack_f+0x80

>

; 2
; 3
; 1
; 3
; 2
; 0
; 0
; 0
; 64
; 0xe14 <__unpack_f+0x66

>

>
r1
r1
r1
r1

; 7

; 0xe70 <__unpack_f+0xc2

e5a:

19 f4

brne

.+6

; 0xe62 <__unpack_f+0xb4

e5c:
e5e:
e60:
e62:
e64:

84
8c
08
64
03

e0
93
95
ff
c0

ldi
st
ret
sbrs
rjmp

r24, 0x04
X, r24

; 4

r22, 4
.+6

; 0xe6c <__unpack_f+0xbe

e66:
e68:
e6a:

81 e0
8c 93
12 c0

ldi
st
rjmp

r24, 0x01
X, r24
.+36

e6c:
e6e:

1c 92
10 c0

st
rjmp

X, r1
.+32

e70:
e72:
e74:
e76:
e78:
e7a:
e7c:
e7e:
e80:
e82:
e84:
e86:
e88:
e8a:
e8c:

2f
30
13
3c
2e
12
83
8c
87
44
55
66
77
8a
d1

57
40
96
93
93
97
e0
93
e0
0f
1f
1f
1f
95
f7

subi
sbci
adiw
st
st
sbiw
ldi
st
ldi
add
adc
adc
adc
dec
brne

r18, 0x7F
r19, 0x00
r26, 0x03
X, r19
-X, r18
r26, 0x02
r24, 0x03
X, r24
r24, 0x07
r20, r20
r21, r21
r22, r22
r23, r23
r24
.-12

; 127
; 0
; 3

e8e:
e90:
e92:
e94:
e96:
e98:
e9a:
e9c:

70
14
4d
5d
6d
7c
17
08

64
96
93
93
93
93
97
95

ori
adiw
st
st
st
st
sbiw
ret

r23, 0x40
r26, 0x04
X+, r20
X+, r21
X+, r22
X, r23
r26, 0x07

; 64
; 4

push
movw
movw
ld
cpi
brcc

r17
r26,
r30,
r25,
r25,
.+2

rjmp

.+142

; 0xf3a <__fpcmp_parts_f

ld
cpi
brcc

r24, Z
r24, 0x02
.+2

; 2
; 0xeb4 <__fpcmp_parts_f

rjmp

.+134

; 0xf3a <__fpcmp_parts_f

cpi
brne

r25, 0x04
.+20

; 4
; 0xecc <__fpcmp_parts_f

adiw

r26, 0x01

; 1

>

>
; 1
; 0xe90 <__unpack_f+0xe2

>
; 0xe90 <__unpack_f+0xe2

>

; 2
; 3
; 7

; 0xe82 <__unpack_f+0xd4

>

00000e9e <__fpcmp_parts_f>:
e9e:
1f 93
ea0:
dc 01
ea2:
fb 01
ea4:
9c 91
ea6:
92 30
ea8:
08 f4
+0xe>
eaa:
47 c0
+0x9c>
eac:
80 81
eae:
82 30
eb0:
08 f4
+0x16>
eb2:
43 c0
+0x9c>
eb4:
94 30
eb6:
51 f4
+0x2e>
eb8:
11 96

r24
r22
X
0x02

; 7

; 2
; 0xeac <__fpcmp_parts_f

eba:
ebc:
ebe:
+0x88>
ec0:
ec2:
ec4:
ec6:
ec8:
eca:
+0xac>
ecc:
ece:
+0x3a>
ed0:
ed2:
+0x42>
ed4:
ed6:
+0xa8>
ed8:
eda:
edc:
+0xa2>
ede:
+0x9c>
ee0:
ee2:
ee4:
ee6:
ee8:
+0x88>
eea:
eec:
eee:
+0x88>
ef0:
ef2:
ef4:
ef6:
ef8:
efa:
efc:
efe:
f00:
+0x88>
f02:
f04:
f06:
+0x98>
f08:
f0a:
f0c:
f0e:
f10:
f12:
f14:
f16:
f18:
f1a:

1c 91
84 30
99 f5

ld
cpi
brne

r17, X
r24, 0x04
.+102

81
68
70
61
71
3f

81
2f
e0
1b
09
c0

ldd
mov
ldi
sub
sbc
rjmp

r24, Z+1
r22, r24
r23, 0x00
r22, r17
r23, r1
.+126

; 0x01

84 30
21 f0

cpi
breq

r24, 0x04
.+8

; 4
; 0xed8 <__fpcmp_parts_f

92 30
31 f4

cpi
brne

r25, 0x02
.+12

; 2
; 0xee0 <__fpcmp_parts_f

82 30
b9 f1

cpi
breq

r24, 0x02
.+110

; 2
; 0xf46 <__fpcmp_parts_f

81 81
88 23
89 f1

ldd
and
breq

r24, Z+1
r24, r24
.+98

; 0x01

2d c0

rjmp

.+90

; 0xf3a <__fpcmp_parts_f

11
1c
11
82
f1

96
91
97
30
f0

adiw
ld
sbiw
cpi
breq

r26,
r17,
r26,
r24,
.+60

81 81
18 17
d9 f4

ldd
cp
brne

r24, Z+1
r17, r24
.+54

; 0x01

12
2d
3c
13
82
93
82
93
94

96
91
91
97
81
81
17
07
f0

adiw
ld
ld
sbiw
ldd
ldd
cp
cpc
brlt

r26,
r18,
r19,
r26,
r24,
r25,
r24,
r25,
.+36

; 2

28 17
39 07
bc f0

cp
cpc
brlt

r18, r24
r19, r25
.+46

14
8d
9d
0d
bc
a0
24
35
46
57

adiw
ld
ld
ld
ld
mov
ldd
ldd
ldd
ldd

r26, 0x04
r24, X+
r25, X+
r0, X+
r27, X
r26, r0
r18, Z+4
r19, Z+5
r20, Z+6
r21, Z+7

96
91
91
90
91
2d
81
81
81
81

0x01
X
0x01
0x02

0x02
X+
X
0x03
Z+2
Z+3
r18
r19

; 4
; 0xf26 <__fpcmp_parts_f

; 0
; 0xf4a <__fpcmp_parts_f

; 0xf40 <__fpcmp_parts_f

; 1
; 1
; 2
; 0xf26 <__fpcmp_parts_f

; 0xf26 <__fpcmp_parts_f

; 3
; 0x02
; 0x03
; 0xf26 <__fpcmp_parts_f

; 0xf36 <__fpcmp_parts_f
; 4

;
;
;
;

0x04
0x05
0x06
0x07

f1c:
f1e:
f20:
f22:
f24:
+0x8e>
f26:
f28:
+0x9c>
f2a:
+0xa2>
f2c:
f2e:
f30:
f32:
f34:
+0xa8>
f36:
f38:
+0xa2>
f3a:
f3c:
f3e:
+0xac>
f40:
f42:
f44:
+0xac>
f46:
f48:
f4a:
f4c:
f4e:

28
39
4a
5b
18

17
07
07
07
f4

cp
cpc
cpc
cpc
brcc

r18,
r19,
r20,
r21,
.+6

11 23
41 f0

and
breq

r17, r17
.+16

; 0xf3a <__fpcmp_parts_f

0a c0

rjmp

.+20

; 0xf40 <__fpcmp_parts_f

82
93
a4
b5
40

17
07
07
07
f4

cp
cpc
cpc
cpc
brcc

r24,
r25,
r26,
r27,
.+16

11 23
19 f0

and
breq

r17, r17
.+6

; 0xf40 <__fpcmp_parts_f

61 e0
70 e0
05 c0

ldi
ldi
rjmp

r22, 0x01
r23, 0x00
.+10

; 1
; 0
; 0xf4a <__fpcmp_parts_f

6f ef
7f ef
02 c0

ldi
ldi
rjmp

r22, 0xFF
r23, 0xFF
.+4

; 255
; 255
; 0xf4a <__fpcmp_parts_f

60
70
cb
1f
08

ldi
ldi
movw
pop
ret

r22, 0x00
r23, 0x00
r24, r22
r17

; 0
; 0

push
push
push
push
push
push
push
push
push
push
push
push
push
push
push
push
push
push
in
in
sub
sbc
in
cli
out

r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r28
r29
r28, 0x3d
r29, 0x3e
r28, r26
r29, r27
r0, 0x3f

e0
e0
01
91
95

00000f50 <__prologue_saves__>:
f50:
2f 92
f52:
3f 92
f54:
4f 92
f56:
5f 92
f58:
6f 92
f5a:
7f 92
f5c:
8f 92
f5e:
9f 92
f60:
af 92
f62:
bf 92
f64:
cf 92
f66:
df 92
f68:
ef 92
f6a:
ff 92
f6c:
0f 93
f6e:
1f 93
f70:
cf 93
f72:
df 93
f74:
cd b7
f76:
de b7
f78:
ca 1b
f7a:
db 0b
f7c:
0f b6
f7e:
f8 94
f80:
de bf

r24
r25
r26
r27
; 0xf2c <__fpcmp_parts_f

r18
r19
r20
r21

0x3e, r29

; 0xf46 <__fpcmp_parts_f

; 61
; 62
; 63
; 62

f82:
f84:
f86:

0f be
cd bf
09 94

out
out
ijmp

00000f88 <__epilogue_restores__>:
f88:
2a 88
ldd
f8a:
39 88
ldd
f8c:
48 88
ldd
f8e:
5f 84
ldd
f90:
6e 84
ldd
f92:
7d 84
ldd
f94:
8c 84
ldd
f96:
9b 84
ldd
f98:
aa 84
ldd
f9a:
b9 84
ldd
f9c:
c8 84
ldd
f9e:
df 80
ldd
fa0:
ee 80
ldd
fa2:
fd 80
ldd
fa4:
0c 81
ldd
fa6:
1b 81
ldd
fa8:
aa 81
ldd
faa:
b9 81
ldd
fac:
ce 0f
add
fae:
d1 1d
adc
fb0:
0f b6
in
fb2:
f8 94
cli
fb4:
de bf
out
fb6:
0f be
out
fb8:
cd bf
out
fba:
ed 01
movw
fbc:
08 95
ret
00000fbe <itoa>:
fbe:
fb
fc0:
9f
fc2:
e8
fc4:
42
fc6:
c4
fc8:
45
fca:
b4
fcc:
4a
fce:
29
fd0:
97
fd2:
1e
fd4:
90
fd6:
81
fd8:
9f
fda:
64
fdc:
77
fde:
0e
fe2:
80
fe4:
8a
fe6:
0c
fe8:
89
fea:
81
fec:
cb
fee:
00
ff0:
a1
ff2:
16

01
01
94
30
f0
32
f4
30
f4
fb
f4
95
95
4f
2f
27
94 10 08
5d
33
f0
5d
93
01
97
f7
f4

movw
movw
clt
cpi
brlt
cpi
brge
cpi
brne
bst
brtc
com
neg
sbci
mov
eor
call
subi
cpi
brlt
subi
st
movw
sbiw
brne
brtc

0x3f, r0
0x3d, r28

; 63
; 61

r2, Y+18
r3, Y+17
r4, Y+16
r5, Y+15
r6, Y+14
r7, Y+13
r8, Y+12
r9, Y+11
r10, Y+10
r11, Y+9
r12, Y+8
r13, Y+7
r14, Y+6
r15, Y+5
r16, Y+4
r17, Y+3
r26, Y+2
r27, Y+1
r28, r30
r29, r1
r0, 0x3f

;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;

0x3e, r29
0x3f, r0
0x3d, r28
r28, r26

; 62
; 63
; 61

0x12
0x11
0x10
0x0f
0x0e
0x0d
0x0c
0x0b
0x0a
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01

; 63

r30, r22
r18, r30
r20, 0x02
; 2
.+48
; 0xff8 <itoa+0x3a>
r20, 0x25
; 37
.+44
; 0xff8 <itoa+0x3a>
r20, 0x0A
; 10
.+10
; 0xfda <itoa+0x1c>
r25, 7
.+6
; 0xfda <itoa+0x1c>
r25
r24
r25, 0xFF
; 255
r22, r20
r23, r23
0x1020 ; 0x1020 <__udivmodhi4>
r24, 0xD0
; 208
r24, 0x3A
; 58
.+2
; 0xfea <itoa+0x2c>
r24, 0xD9
; 217
Z+, r24
r24, r22
r24, 0x00
; 0
.-24
; 0xfda <itoa+0x1c>
.+4
; 0xff8 <itoa+0x3a>

ff4:
ff6:
ff8:
ffa:
ffc:

5d
51
10
c9
0c

00001000 <strrev>:
1000:
dc
1002:
fc
1004:
67
1006:
71
1008:
77
100a:
e1
100c:
32
100e:
04
1010:
7c
1012:
6d
1014:
70
1016:
62
1018:
ae
101a:
bf
101c:
c8
101e:
08

e2
93
82
01
94 00 08

ldi
st
st
movw
jmp

r21, 0x2D
; 45
Z+, r21
Z, r1
r24, r18
0x1000 ; 0x1000 <strrev>

01
01
2f
91
23
f7
97
c0
91
93
83
91
17
07
f3
95

movw
movw
mov
ld
and
brne
sbiw
rjmp
ld
st
st
ld
cp
cpc
brcs
ret

r26, r24
r30, r24
r22, r23
r23, Z+
r23, r23
.-8
r30, 0x02
.+8
r23, X
X+, r22
Z, r23
r22, -Z
r26, r30
r27, r31
.-14

sub
sub
ldi
rjmp

r26, r26
r27, r27
r21, 0x11
.+14

; 17
; 0x1036 <__udivmodhi4_e

adc
adc
cp
cpc
brcs

r26,
r27,
r26,
r27,
.+4

; 0x1036 <__udivmodhi4_e

sub
sbc

r26, r22
r27, r23

adc
adc
dec
brne

r24, r24
r25, r25
r21
.-22

com
com
movw
movw
ret

r24
r25
r22, r24
r24, r26

00001020 <__udivmodhi4>:
1020:
aa 1b
1022:
bb 1b
1024:
51 e1
1026:
07 c0
p>
00001028 <__udivmodhi4_loop>:
1028:
aa 1f
102a:
bb 1f
102c:
a6 17
102e:
b7 07
1030:
10 f0
p>
1032:
a6 1b
1034:
b7 0b
00001036 <__udivmodhi4_ep>:
1036:
88 1f
1038:
99 1f
103a:
5a 95
103c:
a9 f7
oop>
103e:
80 95
1040:
90 95
1042:
bc 01
1044:
cd 01
1046:
08 95
00001048 <_exit>:
1048:
f8 94

cli

0000104a <__stop_program>:
104a:
ff cf
>

rjmp

.-2

; 0x1004 <strrev+0x4>
; 2
; 0x1018 <strrev+0x18>

; 0x1010 <strrev+0x10>

r26
r27
r22
r23

; 0x1028 <__udivmodhi4_l

; 0x104a <__stop_program