Labs-VLSI Lab Manual

VLSI System Design
Lab Manual
Name: _________________________________________ Reg. No:___________ Section: _________ Group: ______
University of Engineering & Technology Taxila
Prepared by: Checked by: Date:
VLSI System Design Lab By Engr. Waqar Ahmad
Software Requirements
S.No. 1 Software Title
DSCH
Description The DSCH program is logic editor and Simulator.DSCH is used to validate the architecture of logic circuit before the microelectronics design is started.DSCH provides a user-friendly environment for hierarchical logic design, and fast simulation with delay analysis, which allows the design and validation of complex logic structure. DSCH also features the symbols, models and assembly support for 8051 and 80f64. DSCH also includes an interface to SPICE. The Microwind program allows the student to design and simulate an integrated circuit at physical description level. The package contains a library of common logic and analog ICs to view and simulate. Microwind includes all the commands for a mask editor as well as original tools never gathered before in a single module (2D and 3D process view Verilog Compiler, tutorial on MOS devices). You gain access to circuit simulation by pressing one single key. The electric extraction of your circuit is automatically performed and the analog simulator produces voltage and current curves immediately.
Microwind
Table of Contents
Lab No.
Lab # 1
Lab Title
Introduction to Microwind and Analysis of CMOS 0.25 micron Technology MOSFETs CMOS 0.25 micron Technology Inverter Characteristics and Layout in Microwind Layout of Basic Gates and a Complex Gate using CMOS 0.25 micron Technology in Microwind. Layout of XOR and XNOR Gates using CMOS 0.25 micron Technology in Microwind. Layout of Multiplexer, Demultiplexer and Shifter using CMOS 0.25 micron Technology in Microwind Design and implementation of Layout of Full Adder using CMOS 0.25 micron Technology in Microwind Design and implementation of Layout of 4-bit Subtractor and 2bit Comparator using CMOS 0.25 micron Technology in Microwind Design and implementation of Layout of 4x4 bit Multiplier CMOS 0.25 micron Technology in Microwind Design and implementation of Layout of RS-Latch, D Latch, Dreg, Clock Divider in CMOS 0.25 micron Technology in Microwind Design and implementation of Layout of Synchronous Counter and Asynchronous Counter in CMOS 0.25 micron Technology in Microwind Design and Implementation of Layout of Static RAM Cell using CMOS 0.25 Micron Technology in Microwind Design and Implementation of Layout of Dynamic RAM Cell using CMOS 0.25 Micron Technology in Microwind Design and Implementation of Layout of ROM Memory using CMOS 0.25 Micron Technology in Microwind
Page
5
Lab # 2
13
Lab # 3
19
Lab # 4
26
Lab # 5
31
Lab # 6
35
Lab # 7
40
Lab # 8
43
Lab # 9
46
Lab # 10
50
Lab # 11 Lab # 12
51 52
Lab # 13
53
Lab # 14
Design and Implementation of Layout of Flash Memory using CMOS 0.25 Micron Technology in Microwind Design and Implementation of Layout of Digital-Analog Converter using CMOS 0.25 Micron Technology in Microwind Design and Implementation of Layout of Analog-Digital Converter using CMOS 0.25 Micron Technology in Microwind
54
Lab # 15
55
Lab # 16
56
Lab 01
Lab Title: Introduction to Microwind and Analysis of CMOS 0.25 micron
Technology MOSFETs.
Lab Objective: In this lab students will be introduced to a Layout based EDA tool Microwind and the introduction will be accompanied with analysis of MOS transistors. The tool used in this lab is Microwind.
The tasks given in the lab include, 1 2 3 4 Familiarity and Hands on Example using the tool. Layout Design using the tool. Study of MOSFET Characteristics. Analog Simulation of MOSFETs.
Tool used: Microwind Lab Description:

MOSFET The Metal Oxide Semiconductor Field Effect Transistor is very important part of Digital Integrated Circuits. It is mostly used as switch in digital design. MOSFET is a four terminal device. The voltage applied to the gate terminal determine the current flow between drain and source terminals. The body/substrate of the transistor is the fourth terminal. Mostly the fourth terminal (body/substrate) of the device is connected to dc supply that is identical for all devices of the same type (GND fro nMOS and Vdd for pMOS). Usually this terminal is not shown on the schematics. nMOS The nMOS transistor consists of n+ drain and source diffusion regions, which are embedded in a p-type substrate. The electrons in the channel beneath the gate between source and drain terminal are responsible for the current flow. pMOS The pMOS transistor consists of p+ drain and source diffusion regions, which are embedded in an n-type substrate. The holes in the channel beneath the gate between source and drain terminal are responsible for the current flow. CMOS The CMOS (Complementary MOS) consist of both p-type and n-type MOS. The advantage of CMOS is its low power design due its Static behavior. Design/ Diagram/Circuit
Lab Instructions a) Open the Microwind2 by double clicking it located in the installed directory of microwind2-7
The following screen will be appeared
b) Select the foundry using the command File > Select Foundry
c) Select 0.25-micron process by selecting cmos025.tec file. Click Open tab to

continue.
d) Save the design as Lab01 using the command File > Save as. e) Create an nMOS by using the nMOS generator button in the Palette
You can set the width and length of MOS by typing in the fields Width MOS and Length MOS either in micron or in lambda units as indicated in the above figure. Click on Generate Device Tab to generate the device.
f) Apply the voltages and output node using the symbol buttons Vdd, Gnd, Add a Pulse, and Visible node in the Palette menu, as indicated in the following figure. You can use the Stretch/Move command button for these actions.
g) Click on the Run Tab on the Tool bar menu to start the simulation or using the command Simulate > Run Simulation.
h) Now apply the Vdd to the n+ diffusion or drain terminal instead of Vss, run the simulation again.
Analyze the simulation waveform, use different values of voltages for Vdd by double clicking on it and set the voltage level. Now we will make the above schematics.
Similarly the nMOS can be analyzed using different widths and different input voltages. j) Save the design. The characteristics of the pMOS are similar to the nMOS. Design the pMOS Layout and analyzed in the similar way as nMOS. Explore the Simulation Graphs. Explore different device parameters and the commands in the drop down menus.
Lab Report
Give a short description of the contents of the lab Include block diagram/diagrams of your design in the lab report Describe your layout design approach parameters and explain the effects of each parameter Include layout of your design Include the results in timing waveform format in your report Only follow the provided cover page format.
Simulation Analysis (Include in your Lab Report)
You can increase the table and also the entries for in depth analysis. A properly presented in depth analysis with graph based on the table entries will be highly appreciated. Discuss the Effects of width design parameter of the MOS devices on their behavior.
Lab Tasks:
Task#1: Layout design analysis of nMOS using MOS generator. Task#2: Layout design analysis of pMOS using MOS generator. Task#3: Manually design the layout of nMOS. Task#4: Manually design the layout of pMOS. Task#5: Manually design the layout of Transmission Gate.
Lab performed on (date): ___________ Signature: ______________ Checked by: ________________________ Date: ______________ Marks Awarded: ____________ Comments:
Lab 02
Lab Title: CMOS 0.25 micron Technology Inverter Characteristics and Layout in Microwind. Lab Objective: In this lab students will design and implement a CMOS Inverter. Different design Parameters effects like transistor sizing, supply voltages etc well be analyzed and delay, area, power and currents will be observed. This lab assumed that students are familiar with Microwind and Lambda based design rules. The tool used in this lab is Microwind.
The tasks given in the lab include,
Design of CMOS Inverter and transistor sizing.. Layout Design using the tool. Gate delay, area, power and current analysis and the effects of transistor sizing on these parameters.
Tool used: Microwind, DSCH Lab Description: CMOS Inverter CMOS Inverter/NOT gate is considered to be the heart of VLSI circuits, based on the understanding of NOT gate we can extend it easily to NAND and NOR gates which are the basic building blocks of more complex circuits e.g. multipliers and microprocessors. As per discussion and design on white board in the Lab, a NOT gate can be implemented using two FETs i.e. a pFET and an nFET both connected in series, in which Vdd is supplied to pFET and nFET is grounded, input x is applied to the gate terminals of both and the output is obtained at node y. Design/ Diagram/Circuit
As covered in the lectures we know that the mobility of the holes is less than that of electrons, and in CMOS inverter pFET is responsible for the conduction of current leading a logic 1 at the output, while nFET is responsible for the conduction of current leading a logic 0 at the output. This means that the gate delay form low to high will be greater than the gate delay for low to high voltage. VLSI System Design Lab By Engr. Waqar Ahmad
Lab Instructions Automated Layout from the Schematic Design 1. Open DSCH and select the foundry cmos025. 2. Save the design as Save as as Lab02. Save the design frequently during lab session. 3. Draw the circuit diagram of inverter. 4. Check for floating point if any. 5. Simulate the Design 6. Make a Verilog file of the design. 7. Open Microwind and select the foundry cmos025. 8. Compile the Verilog file of inverter Lab02.txt for Compile > Compile Verilog File command 9. Save the design. 10. Simulate the design using the Run command 11. Analyze configuration delay, gate delay, current, power, and midpoint voltage. 12. Repeat the design for different value of transistor size and supply voltage and carefully observe the changes in configuration delay, gate delay, current, power, and midpoint voltage.
Manual Layout of Inverter 1. Open Microwind and select the foundry cmos025. 2. Save the design as Save as as Lab02, and save the design frequently during the Lab session.
3. Draw the layout of nMOS using MOS Generator 4. Draw the layout of pMOS using MOS Generator by setting the appropriate width of pMOS. 5. Connect the two transistors using Metal 1 as per design. 6. Draw the rails of V DD and ground rails above and below. 7. Connect the nWell to V DD 8. Check the design using DRC for any design rule violation and correct the design in case of error, again run the DRC and check for errors. Or run the DRC after each change in the layout. 9. Check for Electrical connections to be valid. 10. Add inputs and outputs to the design; also add virtual capacitance at the output in your design. 11. Simulate the Design. Observe the values of configuration delay, gate delay, power, current, VTC, and area. 12. Repeat the design using for different values of transistors dimensions, supply voltages. And observe the changes in configuration delay, gate delay, power, current, VTC, and area carefully. Make a conclusion of your observations.
Lab Report Give a short description of the contents of the lab Include block diagram/diagrams of your design in the lab report Describe your layout design approach parameters and explain the effects of each the parameter Include layout of your design also add your name on the design for evaluation purpose. Include the results in timing waveform format in your report Only follow the provided cover page format Simulation Analysis (Include in your Lab Report)
You can increase the table and also the entries for in depth analysis. A properly presented in depth analysis with graph based on the table entries will be highly appreciated. Discuss the Effects of width design parameter of the MOS devices on their behavior Lab Tasks:
Task#1: Draw schematic (logic) diagram of CMOS inverter using the DSCH and
analyze its functionality by simulation.
Task#2: Generate the automated layout of the CMOS inverter from schematic
diagram and analyze its functionality,
Simulate the Design. Observe the values of configuration delay, gate delay, power, current, VTC, and area.
Task#3: Manually design the layout of CMOS inverter, Simulate the Design. Observe the values of configuration delay, gate delay, power, current, VTC, and area.
Task#4: Design the layout of 3-State Inverter. Task#5: Design the layout of Ring Oscillator.
Lab 03
Lab Title: Layout of Basic Gates and a Complex Gate using CMOS 0.25 micron Technology in Microwind. Lab Objective: In this lab students will design and implement the layouts of different CMOS gates, which includes NAND, AND NOR, OR and a Complex Gate. The tool used in this lab is Microwind.
The tasks given in the lab include,
. Design of CMOS NAND, AND, NOR, OR Gates and a Complex Gate. Layout Design using the tool. Gate delay, area, power and current analysis and the effects of transistor sizing on these parameters. Tool used: Microwind Lab Description: a) NAND Gate As per discussion and design on white board in the Lab, a NAND gate can be implemented using four FETS i.e. two pFETs and two nFETs as the inputs of the gate is two. pFETs are connected in parallel while nFETs are connected in series, Vdd is supplied to the parallel combination of pFETs while the series combination of nFETs is grounded. Inputs a & b are applied to the gate terminals of all FETs, and the output f is obtained from the common junction of these series and parallel combinations as illustrated in NAND circuit under the heading of Design Diagram/Circuit. b) NOR Gate As per discussion and design on white board in the Lab, a NOR gate can be implemented using four FETS i.e. two pFETs and two nFETs as the inputs of the gate is two. pFETs are connected in series while nFETs are connected in parallel, Vdd is supplied to the series combination of pFETs while the parallel combination of nFETs is grounded. Inputs a & b are applied to the gate terminals of all FETs, and the output f is obtained from the common junction of these parallel and series combinations as illustrated in NOR circuit under the heading of Design Diagram/Circuit. c) Complex Gate The expression for the complex gate is given as under
As per discussion and design on white board in the Lab, this complex gate can be implemented as under
For pFETs Array Group1: Three pFETs with inputs c, d and d at its gate terminals are connected in parallel. Group2: Two pFETs with inputs a and d are in parallel and is connected in series with Group1 For nFETs Array Group1: Three nFETs with inputs c, d and d at its gate terminals are connected in series. Group2: Two nFETs with inputs a and d are in series and is connected in parallel with Group1 Design/ Diagram/Circuit
(a) Symbol, Truth Table and CMOS circuit of NAND Gate
(b)
Symbol, Truth Table and CMOS circuit of NOR Gate
(c)
Expression and CMOS circuit of a Complex Gate
Lab Tasks:
Task#1: Design the layout of 2- Input NAND Gate. Task#2: Design the layout of 2- Input AND Gate, Simulate the Design. Observe the
values of configuration delay, gate delay, power, current, VTC, and area.
Task#3: Design the layout of 2- Input NOR Gate, Simulate the Design. Observe the
Task#4: Design the layout of 2- Input OR Gate, Simulate the Design. Observe the
Task#5: Design the layout of Complex Gate, Simulate the Design. Observe the values
of configuration delay, gate delay, power, current, VTC, and area.

.
Lab 04
Lab Title: Layout of XOR and XNOR Gates using CMOS 0.25 micron Technology in Microwind. Lab Objective: In this lab students will design and implement the layouts of XOR and XNOR GateS. The tool used in this lab is Microwind.
. The tasks given in the lab include,
Design of XOR and XNOR Gates. Layout Design using the tool. Gate delay, area, power and current analysis and the effects of transistor sizing on these parameters Tool used: Microwind Lab Description:
Figure: Schematic of XOR Gate
Lab Tasks:
Task#1: Design the layout of 2- Input XOR Gate By five different Methods as discussed on the white board, Simulate the Design. Observe the values of configuration
delay, gate delay, power, current, VTC, and area

Task#2: Design the layout of 2- Input XNOR Gate, Simulate the Design. Observe the
values of configuration delay, gate delay, power, current, VTC, and area
Lab 05
Lab Title: Layout of Multiplexer, Demultiplexer and Shifter using CMOS 0.25 micron Technology in Microwind. Lab Objective: In this lab students will design and implement the layouts of Multiplexer, Demultiplexer and Shifter. The tool used in this lab is Microwind.
. The tasks given in lab include:
Design of Multiplexer, Demultiplexer and Shifter. Layout Design using the tool. Gate delay, area, power and current analysis and the effects of transistor sizing on these parameters.
Tools used: Microwind Lab Description: Multiplexor Generally speaking, a multiplexor is used to transmit a large amount of information through a smaller number of connections. A digital multiplexor is a circuit that selects binary information from one of many input logic signals and directs it to a single input line. A behavioral description of the multiplexor is the case statement:
The usual symbol for the multiplexor is given in figure 6-67. It consists of the two multiplexed inputs in0 and in1 on the left side, the command sel at the bottom of the symbol, and the output f on the right.
Design of the Multiplexor
Task#1: Design the layout of 2-to-1 Mux, Simulate the Design. Observe the values of
configuration delay, gate delay, power, current, VTC, and area

Task#2: Design the layout of 8-to-1 Mux by using the three different methods as
explained on the white board, Simulate the Design.
Observe the values of configuration
delay, gate delay, power, current, VTC, and area

Task#3: Design the layout of Shifter(shift right, shift left, rotate left & right)
circuits, Simulate the Design. Observe the values of configuration delay, gate delay, power, current, VTC, and area
Lab 06
Lab Title: Design and implementation of Layout of Full Adder using CMOS 0.25 micron Technology in Microwind. Lab Objective: In this lab students will design and implement the layouts of Full Adder.Delay, area, power and currents of full adder will be observed. This lab assumed that students are familiar with Microwind and Lambda Based design rules. The tool used in this lab is Microwind.
Design of CMOS Full Adder layout. Layout Design using the tool. Gate delay, area, power and current analysis and the effects of transistor sizing on these parameters.
Tools used: Microwind Lab Description:
Task#1: Design the layout of Full Adder, Simulate the Design. Observe the values of
configuration delay, gate delay, power, current, VTC, and area

Task#2: Design the layout of 4-bit Ripple Carry Adder , Simulate the Design.
Observe the values of configuration delay, gate delay, power, current, VTC, and area Task#3: Design the layout of 4-bit Carry Look Ahead Adder circuit, Simulate the Design. Observe the values of configuration delay, gate delay, power, current, VTC, and area
Lab 07
Lab Title: Design and implementation of Layout of 4-bit Subtractor and 2-bit Comparator using CMOS 0.25 micron Technology in Microwind. Lab Objective: In this lab students will design and implement the layouts of 4-bit Subtractor and 2-bit Comparator .Delay, area, power and currents of 4-bit Subtractor and 2-bit Comparator will be observed. This lab assumed that students are familiar with Microwind and Lambda Based design rules. The tool used in this lab is Microwind.
Design of CMOS 4-bit Subtractor and 2-bit Comparator layout. Layout Design using the tool. Gate delay, area, power and current analysis and the effects of transistor sizing on these parameters.
Tools used: Microwind Lab Description: The substractor circuit can be built easily with a full adder structure as for the adder circuit. The main difference is the needs for a 2's complement circuit which inverts the value of b, and the replacement of the half adder by a full adder, as the initial carry must be 1. The logic circuit corresponding to the 4-bit substractor is reported in figure Some examples of substractor results are also listed.
Task#1: Design the layout of 4-bit Subtractor, Simulate the Design. Observe the
values of configuration delay, gate delay, power, current, VTC, and area
Task#2: Design the layout of 1-bit Comparator, Simulate the Design. Observe the values of configuration delay, gate delay, power, current, VTC, and area
Lab 08
Lab Title: Design and implementation of Layout of 4x4 bit Multiplier CMOS 0.25 micron Technology in Microwind. Lab Objective: In this lab students will design and implement the layouts of 4x4 bit Multiplier .Delay, area, power and currents of 4x4 bit Multiplier will be observed. This lab assumed that students are familiar with Microwind and Lambda Based design rules. The tool used in this lab is Microwind.
Design of CMOS 4x4 bit Multiplier layout. Layout Design using the tool. Gate delay, area, power and current analysis and the effects of transistor sizing on these parameters. Lab Description:
Task#1: Design the layout of 4x4 bit Multiplier,. Task#2: Simulate the Design. Observe the values of configuration delay, gate delay,
power, current, VTC, and area
Lab 09
Lab Title: Design and implementation of Layout of RS-Latch, D Latch, Dreg, Clock Divider in CMOS 0.25 micron Technology in Microwind. Lab Objective: In this lab students will design and implement the layouts of RSLatch, D Latch, Dreg, Clock Divider .Delay, area, power and currents of RS-Latch, D Latch, Dreg, Clock Divider will be observed. This lab assumed that students are familiar with Microwind and Lambda Based design rules. The tool used in this lab is Microwind.
Design of CMOS RS-Latch, D Latch, Dreg, Clock Divider layout. Layout Design using the tool. Gate delay, area, power and current analysis and the effects of transistor sizing on these parameters. Lab Description:
Task#1: Design the layout of RS-Latch and D-Latch, Simulate the Design. Observe
the values of configuration delay, gate delay, power, current, VTC, and area
Task#2: Design the layout of Dreg and Clock Divider, Simulate the Design. Observe
the values of configuration delay, gate delay, power, current, VTC, and area
Lab 10
Lab Title: Design and implementation of Layout of Synchronous Counter and Asynchronous Counter in CMOS 0.25 micron Technology in Microwind. Lab Objective: In this lab students will design and implement the layouts of Synchronous Counter and Asynchronous Counter .Delay, area, power and currents of Synchronous Counter and Asynchronous Counter will be observed. This lab assumed that students are familiar with Microwind and Lambda Based design rules. The tool used in this lab is Microwind.
Design of CMOS Synchronous Counter and Asynchronous Counter layout. Layout Design using the tool. Gate delay, area, power and current analysis and the effects of transistor sizing on these parameters. Lab Description:
Task#1: Design the layout of Synchronous Counter a, Simulate the Design. Observe the values of configuration delay, gate delay, power, current, VTC, and area Task#2: Design the layout of Asynchronous Counter, Simulate the Design. Observe the values of configuration delay, gate delay, power, current, VTC, and area
Lab 11
Lab Title: Design and Implementation of Layout of Static RAM Cell using CMOS 0.25 Micron Technology in Microwind. Lab Objective: In this lab students will design and implement the layouts of Static RAM Cell. Delay, area, power and currents of Static RAM Cell will be observed. This lab assumed that students are familiar with Microwind and Lambda Based design rules. The tool used in this lab is Microwind.
Design of CMOS Static RAM Cell layout. Layout Design using the tool. Gate delay, area, power and current analysis and the effects of transistor sizing on these parameters. Lab Description:
Task#1: Design the layout of Static RAM Cell, Task#2: Simulate the Design. Observe the values of configuration delay, gate delay,
Lab 12
Lab Title: Design and Implementation of Layout of Dynamic RAM Cell using CMOS 0.25 Micron Technology in Microwind. Lab Objective: In this lab students will design and implement the layouts of Dynamic RAM Cell. Delay, area, power and currents of Dynamic RAM Cell will be observed. This lab assumed that students are familiar with Microwind and Lambda Based design rules. The tool used in this lab is Microwind.
Design of CMOS Dynamic RAM Cell layout. Layout Design using the tool. Gate delay, area, power and current analysis and the effects of transistor sizing on these parameters. Lab Description:
Task#1: Design the layout of Dynamic RAM Cell. Task#2: Simulate the Design. Observe the values of configuration delay, gate delay,
Lab 13
Lab Title: Design and Implementation of Layout of ROM Memory using CMOS 0.25 Micron Technology in Microwind. Lab Objective: In this lab students will design and implement the layouts of ROM Memory. Delay, area, power and currents of ROM Memory will be observed. This lab assumed that students are familiar with Microwind and Lambda Based design rules. The tool used in this lab is Microwind.
Design of CMOS ROM Memory layout. Layout Design using the tool. Gate delay, area, power and current analysis and the effects of transistor sizing on these parameters. Lab Description:
Task#1: Design the layout of ROM Memory . Task#2: Simulate the Design. Observe the values of configuration delay, gate delay,
Lab 14
Lab Title: Design and Implementation of Layout of Flash Memory using CMOS 0.25 Micron Technology in Microwind. Lab Objective: In this lab students will design and implement the layouts of Flash Memory. Delay, area, power and currents of Flash Memory will be observed. This lab assumed that students are familiar with Microwind and Lambda Based design rules. The tool used in this lab is Microwind.
Design of CMOS Flash Memory layout. Layout Design using the tool. Gate delay, area, power and current analysis and the effects of transistor sizing on these parameters. Lab Description:
Task#1: Design the layout of Flash Memory Cell. Task#2: Simulate the Design. Observe the values of configuration delay, gate delay,
Lab 15
Lab Title: Design and Implementation of Layout of Digital-Analog Converter using CMOS 0.25 Micron Technology in Microwind. Lab Objective: In this lab students will design and implement the layouts of Digital-Analog Converter. Delay, area, power and currents of Digital-Analog Converter will be observed. This lab assumed that students are familiar with Microwind and Lambda Based design rules. The tool used in this lab is Microwind.
Design of CMOS Digital-Analog Converter layout. Layout Design using the tool. Gate delay, area, power and current analysis and the effects of transistor sizing on these parameters. Lab Description:
Task#1: Design the layout of Digital-Analog Converter. Task#2: Simulate the Design. Observe the values of configuration delay, gate delay,
Lab 16
Lab Title: Design and Implementation of Layout of Analog-Digital Converter using CMOS 0.25 Micron Technology in Microwind. Lab Objective: In this lab students will design and implement the layouts of Analog-Digital Converter. Delay, area, power and currents of Analog-Digital Converter will be observed. This lab assumed that students are familiar with Microwind and Lambda Based design rules. The tool used in this lab is Microwind.
Design of CMOS Analog-Digital Converter layout. Layout Design using the tool. Gate delay, area, power and current analysis and the effects of transistor sizing on these parameters. Lab Description:
Task#1: Design the layout of Analog-Digital Converter. Task#2: Simulate the Design. Observe the values of configuration delay, gate delay,

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VLSI System Design

Name: _________________________________________ Reg. No:___________ Section: _________ Group: ______

University of Engineering & Technology Taxila

Prepared by: Checked by: Date:

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

Tool used: Microwind Lab Description:

VLSI System Design Lab By Engr. Waqar Ahmad

The following screen will be appeared

c) Select 0.25-micron process by selecting cmos025.tec file. Click Open tab to

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

Simulation Analysis (Include in your Lab Report)

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

Symbol, Truth Table and CMOS circuit of NOR Gate

VLSI System Design Lab By Engr. Waqar Ahmad

Expression and CMOS circuit of a Complex Gate

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

of configuration delay, gate delay, power, current, VTC, and area.

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

Figure: Schematic of XOR Gate

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

delay, gate delay, power, current, VTC, and area

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

Design of the Multiplexor

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

configuration delay, gate delay, power, current, VTC, and area

Observe the values of configuration

delay, gate delay, power, current, VTC, and area

VLSI System Design Lab By Engr. Waqar Ahmad

Tools used: Microwind Lab Description:

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

configuration delay, gate delay, power, current, VTC, and area

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

VLSI System Design Lab By Engr. Waqar Ahmad

power, current, VTC, and area

VLSI System Design Lab By Engr. Waqar Ahmad

Name: ___________________________________ Reg. No:_ Section: _ Group: __