Comb Logic

2
Kenneth R. Laker, University of Pennsylvania, updated 23Feb11
SWITCH-RC TRANSISTOR MODLELS

nMOS
Assume: bulk at GND (W/L)n Rn
ON/ OFF
Cdbn
RnEQV = Rn/2 or GnEQV = 2Gn RnEQV = 2Rn or GnEQV = Gn/2

VDD
Cgbn
Csbn Cdbn = Csbn
I Dn 1 W G n= = KP n R n V DS L n
RpEQV = Rp/2 or GpEQV = 2Gp RpEQV = 2Rp or GpEQV = Gp/2
pMOS
Assume: bulk at VDD
VDD
Csbp Rp
VDD ON/ OFF
(W/L)p
Cgbp
Cdbp Cdbp = Csbp
I Dn 1 W G p= = KP p R p V DS L p
= ID1 + ID2
0 0 VDD VDD
n n
0 VDD 0 VDD
VDD VOL1 VOL1 VOL2 < VOL1
where for NR2: m = 0, 1 or 2
= ID1 + ID2
k'n,d
k'n,d
00
VDD VDD
VDD 0 0 VDD
VOL1 VOL1 VOL2 < VOL1
Gn
Gn
k'n
k'n
Gn = 1/Rn
I Di ID 1 W W G i= = = KP i =KP R i V DS V DS L i L
VOL for INV: 2 1 1 2 V OL =V DD V T0n k V DD V T0n k R R R knEQV L R V DD nEQV R L nEQVR L k nEQV L k nEQV L k nEQV L
INV Equivalent to NR2
0 0
Gn (Rn) Gn (Rn) 2Gn (Rn/2)
knEQV = mkn = k'n m(W/L) = k'n (W/L)EQV where m = 1 or 2

(Pattern Dependent)
Cload-NR2 = Cn-int1 + Cn-int2 + Cext = 2Cdbn + Cext Cload-INV = Cdbn + Cext
Cn-int2 Cn-int1 Cwire nCgb Cext
INV Equivalent to NR2
Cload-NR2
Cload-NR2
kn -> knEQV = mkn

(input pattern dependent)
VA = VDD, VB = 0 or VA = 0, VB = VDD
2V V T0n 2V DDV T0n knEQV RL DD k nEQV R L = =k n R L= 2 2 2V DDV T0nV OL NR2 V OLNR2 2V DDV T0n V OL INV V OL INV
VA VDD, VB = 0 or VA = 0, VB VDD 0V 0->VDD one input switching 0 VDD and the other input set to 0 V.
C load INV 2 V T0n 4V DDV T0n PHL INV = [ ln 1] k n V DDV T0n V DD V T0n V DDV OL INV
= Cdbn + 2C Cload-NR2 = 2Cdbn + Cext CCload-INV= 2 C + Cext + C + C load-NR2 gd db int gb

(VOL-NR2 = VOL-INV for Cases 1, 2) for max value)
kn -> knEQV
for 1, 2) (knEQV = kn for Cases min value)
10
(W/L)1 = (W/L)2 ... = (W/L)n = (W/L)
where for NRn: 0 m n

11
Gn = 1/Rn
Gn
Gn
Gn Vi = VDD
INV Equivalent to NRn
Vi = 0 OL V
n
IL
n
where for NRn: 0 m n

R n W = W =m W 1 EQV R EQV = = L EQV m ON L m L G ni m
Gni = mGn
input pattern dependent
12
1. Design to set max VOL to VOL spec., i.e. Vk = 0 V , Vi = 0 for all i k VDD Set (W/L)k = (W/L) = (W/L)EQV
2V 2V DD V T0n knEQV RDD V T0n k nEQV R L = =k n R L = L 2 2 2V DDV T0n V OL NRnV OL NRn 2V DDV T0n V OL INV V OL INV
2. Design to set for knEQV at min value, i.e. Vk VDD, Vi = 0 for all i k 0 0. L H and all other inputs set to 0 V.
C load INV 2 V T0n 4V DDV T0n PHL INV = [ ln 1] k n V DDV T0n V DD V T0n V DDV OL INV
Cload-INV -> Cload-NRn n Cgd Cext Cload-INV -> Cload-NRn = nCdbn + n Cdb + Cint + Cgb ->
PHL-NRn
Cload-INV Cload-NRn VOL-INV VOL-NRn k kn knEQV -> k

n nEQV
(VOL-NRn = VOL-INV worstvalue max case) (knEQV = kn worst case) min value
13
VT1 VT0n
0 0 VDD VDD
0 VDD 0 VDD
VDD VDD VDD 0
Vout = VOH = VDD

14
R = 1/G approximation: VT1 = VT0n

1 G = 2R 2
R = 1/G
R EQV ND2 =2R G EQV ND2 =
knEQV
W 1 W = L EQV 2 L
2V DD V T0n 1 k nEQV R L = k n R L = 2 2 2V DD V T0n V OLND2 V OL ND2
For INV Equivalent to ND2
15
In Pull-up Cload-ND2 and PLH-ND2 are input-pattern dependent

## CASE1: VA = VDD OH VB = VOH -> 0 DD CASE2: VA = VDD -> 0 OH VB = VDD OH VA # # VB
Cdb1 = Cdb2 = Cdbn Csb1 = Csb2 = Cdbn #Cn-int # Vx

S D
Vout
nCgb
# sb2 #
Cwire 2Cn-int
##
##
Cext
CASE1: Cload = Cgd1 + Cgs1 + Cdb1 + Csb1 + Cdb2 + Cgd2 + Cint + (worst casecase) value) Cgb (worst max C aa db1 + Csb1 + Cdb2 + Cint + Cgb (worst case) CASE2: >
Vout = low -> high Vx Vout = low -> high Vx = low .0
Cload-ND2 Cn-int1 + 2Cn-int + Cext = 3Cn-int + Cext Cload-ND2 Cn-int + Cext

PLH_ND2
PLH_ND2
Cn-int = Cdbn = Csbn

16
In Pull-down Cload-ND2 and PHL-ND2 PHL are input-pattern dependent

VA = VDD DD
Cdb1 = Cdb2 = Cdbn Csb1 = Csb2 = Cdbn

Cn-int
Vout Cext
nCgb
VB = 0 -> VDD
VA
S D
VA = 0 -> VDD
VB = VDD DD
CASE1:
VB
2Cn-int
VB
Vout = high -> low
Vx Vout = high -> low Vx = low .0 (worst case) max value) case
Cload-ND2 Cn-int1 + 2Cn-int + Cext = 3Cn-int + Cext

CASE2:
Cload-ND2 Cn-int + Cext Cn-int = Cdbn = Csbn

PLH_ND2 > PLH_ND2
17
INV Equivalent to ND2
knEQV
W 1 W = L EQV 2 L
k n R L=
2V DDV T0n 2V DD V T0n V OL INV V OL INV 2V DDV T0n

2
kn k nEQVkR L = R La = RL nEQV 2 2V DDV T0n V OL NR2V OL NR2 2
k n=2 k nEQV
C load ND2 2 V T0n 4 V DD V T0n PHL ND2 [ ln 1] k nEQV V DD V T0n V DD V T0n V DD V OL ND2 knEQV
Cload-ND2 3Cn-int + Cext (worst case)

18
VT1 VT0n
VOH &
n
VT2 VT1 VT0n
VTn = VT0n
W 1 W = L EQV n L
approximation: VT1 = VT2 = ... = VTn = VT0n

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Cn-int
Vx1 Vx2 Vxn-1
Cext
C2 2Cn-int
Vx1
<=>
Vxn-1
2Cn-int Cn
Worst-case H-L: V1 = V2 ... = Vn-1 = VDD and Vn = 0 -> VDD => Vout = VDD -> 0 DD and Vx1 = highx2 low; Vxn-1=high = high -> low xn-1 = high -> low Vx1 V -> Vx2 V -> low; ... ; V
out
Worst-case L-H: V1 = V2 ... = Vn-1 = VDD and Vn = VDD -> VOL => Vout = 0 -> VOH DD OH OH and Vx1Vx1 Vx2 Vx2 = Vout = high;-> high = low -> high = low -> high; Vxn-1 low -> low ... ; Vxn-1 Cload-NDn Cn-int1 + 2 (n - 1)Cn-int + Cext = (2n -1) Cn-int + Cext (worst case max value)
Cn-int = Cdbn = Csbn
20
W 1 W = L EQV n L
kn k nEQV R L = = RL 2 2V DDV T0n V OL NRnV OL NRn n

n
2V DD V T0n
C load NDn 2V T0n 4 V DD V T0n PHL NDn knEQV [ ln 1] k nEQV V DD V T0n V DD V T0n V DD V OL NDn
Cload-NDn (2n -1) Cn-int + Cext Cn-int = Cdbn = Csbn

(worst case max value)
21
VT = VT0p
V1 V2 1 1 1 0 0 1 0 0 approximation: VT = VT0p
VT VT0p
Vout 0 0 0 1
VT = VT0n
VT = VT0n
Gp G pEQV = 2
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G nEQV =2 G n
kp = 2 kpEQV
kn = 1/2 knEQV
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2Cp-int Vx
Cdbn1 = Cdbn2 = Cdbn Cdbp1 = Cdbp2 = Cdbp Csb1p = Csb2p = Csbp = Cdbp
Cp-int
nCgb
Cn-int Cn-int
Cext
V1 = 0, V2 = VDD -> 0 & Vx Vout = 0 -> VDD

Cload-NR2 2Cn-int + Cp-int + 2Cp-int + Cext = 2Cn-int + 3Cp-int + Cext
(worst case)
WORST CASE for PULL-DOWN => V1 = 0, V2 = 0 -> VDD & Vx Vout = VDD -> 0 Cload-NR2 2Cn-int + Cp-int + 2Cp-int + Cext = 2Cn-int + 3Cp-int + Cext (worst case) KEEP COMPLEMETARY CMOS NRn: Cload-NRn nCn-int + (2n - 1)Cp-int + Cext GATES SIMPLE (i.e. limit n) Kenneth R. Laker, University of Pennsylvania, updated 23Feb11
24
CMOS NR DESIGN STRATEGIES
C load NR2 2 V T0n 4V DD V T0n kp = n 1] m = 1 or 2 kpEQV PHL NR2 [ ln m k n V DD V T0n V DD V2 T0n V DD Vth(NRn) = VDD/2 => kp2=V T0pn 4V DD k V T0p (worst case m = 1) = (1/m) k C load NR2 n k n PLH NR2 [ ln 1]nEQV V DD k p /2V DD V T0p V DD V T0p
NOTE for NR2: m = 2 => both nMOS transistors switch simultaneously.
p
25
CMOS NR DESIGN STRATEGIES
C load NRn 2 V T0n 4V DD V T0n PHL NRn [ ln 1] 1 m n m k n V DD V T0n V DD V T0n V DD PLH NRn k p /n Vp V T0p V DD V T0p DD C load NRn [ 2V T0p ln 4 V DD V T0p V DD 1]
(worst case m = 1)
26
G pEQV =2G p
VT VT0n
nEQV
Gn G nEQV = 2
Vth(ND2) = VDD/2 => knEQV = kpEQV => kn = 4kp

kp = 1/2 kpEQV kn = 2 knEQV
27
Cp-int
Cdbp1 = Cdbp2 = Cdbp

Cp-int
Cdbn1 = Cdbn2 = Cdbn Csb1n = Csb2n = Csbn = Cdbn nCgb
V1
Vx
Cn-int 2Cn-int
Cext
V2
V1 = VDD, V2 = VDD -> 0 & Vx Vout = 0 -> VDD

Cload-ND2 Cn-in + 2Cn-int + 2Cp-int + Cext = 3Cn-int + 2Cp-int + Cext (worst case)
WORST CASE for PULL-DOWN =>V1 = VDD, V2 = 0 -> VDD & Vx Vout = VDD -> 0 Cload-ND2 Cn-in + 2Cn-int + 2Cp-int + Cext = 3Cn-int + 2Cp-int + Cext (worst case)
NDn: Cload-NRn (2n - 1)Cn-int + nCp-int + Cext

(worst case)
28
CMOS ND DESIGN STRATEGIES

Vth(ND2) = VDD/2 => knEQV = kpEQV => kn = 4kp
kp = 1/m kpEQV kn = 2 knEQV
C load ND2 2 V T0n 4V DD V T0n PHL ND2 [ ln 1] k n /2 V DD V T0n V DD V T0n V DD 2V T0p 4V DD V T0p C load ND2 PLH ND2 [ ln 1] m = 1 or 2 V DD m k p V DD V T0p V DD V T0p (worst case m = 1)
Vth(NDn) = VDD/2 => kn = n2kp
kp = 1/m kpEQV kn = n knEQV
NOTE for ND2: m = 2 => both pMOS transistors switch simultaneously. C load NDn 2 V T0n 4 V DD V T0n PHL NDn [ ln 1] k n / nV DD V T0n V DD V T0n V DD 2V T0p 4V DD V T0p C load NDn PLH NDn [ ln 1] 1 m n V DD m k p V DD V T0p V DD V T0p
(worst case m = 1)
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CMOS ND DESIGN STRATEGIES
Delay Macromodels
Cext = 0 CL = = 0.5 pF Cext 0.5 pF C = 1 pF CLext = 1.0 pF
VDD
ND3
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VDD
ND3
VDD
ND3
PLH C ext =int , LH c ext ext , LH PHL C ext =int , HL c extext , HL
C ext c ext = 1 pF
PLH =0.26 nscext2.12 ns PHL =0.42 nsc ext3.88 ns
Cext = 0
Cext = 0.5 pF Cext = 1.0 pF
cext
int , XY = PXY c ext =0
(ns) (ns) Simulation Data
31
Cext = 0 -> 1 pF. C

L
cext
cext
Cext = 0.5 pF
C ext c ext = 1 pF cext
32
33
34
NOR NAND
G G G E G AG DG E = A D G A G DG E
GB GC G BG C = G BGC
G EQV =G AG D D E G BGC
35
IL
where i = 1, 2, 3 or 4
G1 < G2 < G3 < G4
W W W W W [ ] L A L D L E L B L C W = L EQV W W W W W L A L D L E L B L C
EQV Inverter Case G4 where A = B = C = D = E = 1

G A G DG E G AG DG E = G AG DG E
G B GC G BG C = G B GC
36
W W W W W [ ] L A L D L E L B L C W = L EQV W W W W W L A L D L E L B L C
Let
W W W W W W = = = = = L n L A L B L C L D L E
G EQV =G AG D D E G BG C W W W W W 2 W 1 W 7 W = 2 = = L EQV L n L n L n L n 3 L n 2 L n 6 L n
37
W W 1 W = = L EQV L EQV ND2 2 L
38
D S
GND
39
OPTIMIZED
Arbitrary Stick Layout
40
diffusion breaks
d d d d d
i.e. n, p Euler paths with identical sequences of inputs

41
Arbitrary Stick Layout
42
Optimized Stick Layout
43
3. If no common n- and p- Euler paths are found in step 2, partition the gate n- and p- graphs into the minimum number of sub-graphs that will result in separate common n- and p- Euler paths.
44
AB AB= AB AB= AB AB AB AB= AA ABABB B=AB AB

45
SUM of Products => OR of ANDs
46
PRODUCT of SUMS => AND of ORs
47
Kenneth R. Laker, University of Pennsylvania, updated 16Mar10
48
49
Note at t = 0-: Vin = 0, Vout = 0 at t = 0+: Vin = 0 -> VDD
VDSp = - VDD + Vout
- VTp
50
kp (- VDD - VTp)2
kp [2(- VDD - Vtp) (Vout VDD) - (Vout VDD)2] kp [2(- VDD - Vtp) - (Vout VDD)]
kp [2(- VDD - Vtp) - (Vout VDD)]

51
52
53
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Z = As Bs
Z Z
F = BA + BA = AB + AB It is crucial that a conducting TG network always be provided between the output and one of the inputs.
55
A B A B F = AB + AB
Cpar
A 1 1 0 0
A 0 0 1 1
B 1 0 1 0
B 0 1 0 1
AB 0 1 Z Z
AB Z Z 1 0
F 0 (B) 1 (B) 1 (B) 0 (B)
Z = High Z
56
F1 F2 F3 F4
F 1 AB F 2 AB F 3 B A C par F 4 A B
AND(A, B)
Z= F 1AB F 2AB F 3ABF 4B A

57
NOR (A, B) Z= F 4B = B = AB A A Z = AB OR (A, B) XOR (A, B) Z= F 2AB F 3B A .= AB AB AND (A, B) Z= F 1AB= AB

Z = AB NAND (A, B)

Comb Logic

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Comb Logic

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2

Kenneth R. Laker, University of Pennsylvania, updated 23Feb11

SWITCH-RC TRANSISTOR MODLELS

RnEQV = Rn/2 or GnEQV = 2Gn RnEQV = 2Rn or GnEQV = Gn/2

Csbn Cdbn = Csbn

Cdbp Cdbp = Csbp

Kenneth R. Laker, University of Pennsylvania, updated 23Feb11

VDD VOL1 VOL1 VOL2 < VOL1

where for NR2: m = 0, 1 or 2

VOL1 VOL1 VOL2 < VOL1

Kenneth R. Laker, University of Pennsylvania, updated 23Feb11

INV Equivalent to NR2

Gn (Rn) Gn (Rn) 2Gn (Rn/2)

knEQV = mkn = k'n m(W/L) = k'n (W/L)EQV where m = 1 or 2

Cload-NR2 = Cn-int1 + Cn-int2 + Cext = 2Cdbn + Cext Cload-INV = Cdbn + Cext

Cn-int2 Cn-int1 Cwire nCgb Cext

Kenneth R. Laker, University of Pennsylvania, updated 23Feb11

INV Equivalent to NR2

kn -> knEQV = mkn

(input pattern dependent)

= Cdbn + 2C Cload-NR2 = 2Cdbn + Cext CCload-INV= 2 C + Cext + C + C load-NR2 gd db int gb

for 1, 2) (knEQV = kn for Cases min value)

(W/L)1 = (W/L)2 ... = (W/L)n = (W/L)

where for NRn: 0 m n

where for NRn: 0 m n

input pattern dependent

Kenneth R. Laker, University of Pennsylvania, updated 23Feb11

Cload-INV Cload-NRn VOL-INV VOL-NRn k kn knEQV -> k

Kenneth R. Laker, University of Pennsylvania, updated 23Feb11

VDD VDD VDD 0

Vout = VOH = VDD

R = 1/G approximation: VT1 = VT0n

R EQV ND2 =2R G EQV ND2 =

For INV Equivalent to ND2

In Pull-up Cload-ND2 and PLH-ND2 are input-pattern dependent

Cdb1 = Cdb2 = Cdbn Csb1 = Csb2 = Cdbn #Cn-int # Vx

Vout = low -> high Vx Vout = low -> high Vx = low .0

Cload-ND2 Cn-int1 + 2Cn-int + Cext = 3Cn-int + Cext Cload-ND2 Cn-int + Cext

Cn-int = Cdbn = Csbn

In Pull-down Cload-ND2 and PHL-ND2 PHL are input-pattern dependent

Cdb1 = Cdb2 = Cdbn Csb1 = Csb2 = Cdbn

Vout = high -> low

Cload-ND2 Cn-int1 + 2Cn-int + Cext = 3Cn-int + Cext

Cload-ND2 Cn-int + Cext Cn-int = Cdbn = Csbn

PLH_ND2 > PLH_ND2

INV Equivalent to ND2

2V DDV T0n 2V DD V T0n V OL INV V OL INV 2V DDV T0n

kn k nEQVkR L = R La = RL nEQV 2 2V DDV T0n V OL NR2V OL NR2 2

Cload-ND2 3Cn-int + Cext (worst case)

VT2 VT1 VT0n

approximation: VT1 = VT2 = ... = VTn = VT0n

Cn-int = Cdbn = Csbn

Kenneth R. Laker, University of Pennsylvania, updated 23Feb11

kn k nEQV R L = = RL 2 2V DDV T0n V OL NRnV OL NRn n

Cload-NDn (2n -1) Cn-int + Cext Cn-int = Cdbn = Csbn

(worst case max value)

Kenneth R. Laker, University of Pennsylvania, updated 23Feb11

V1 = 0, V2 = VDD -> 0 & Vx Vout = 0 -> VDD

CMOS NR DESIGN STRATEGIES

NOTE for NR2: m = 2 => both nMOS transistors switch simultaneously.

CMOS NR DESIGN STRATEGIES

Kenneth R. Laker, University of Pennsylvania, updated 23Feb11

Vth(ND2) = VDD/2 => knEQV = kpEQV => kn = 4kp