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Historical Overview
nMOS era: 1970-85 Pass-transistor design Domino CMOS, 1982
NORA DCVSL
CPL, DPL
DCVS-PG SRPL LEAP
SOI-CMOS
Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 2
Drawbacks:
Not compatible with existing design tools Exhibiting testability and reliability problems
Pass-Transistor Design
Another way of looking at Karnaugh Map: AND function
A B F B A
B
F
0
0 1 B
1 0
B
4
Pass-Transistor Design
A X F Y A
Two-variable function
X 0 0 1 1 0 0 1 1 B B B B B B B B
Y 0 1 0 1 B
F 0 A 1 AB
B
B 0 1 0 1
AB AB AB AB AB
A+B
A B
B
B
B
A B A B
B
5
B
B
Pass-Transistor Design
Threshold Voltage Drop problem:
A=Vdd + V th B=Vdd B A (a) (b) Fmax = Vdd-Vth Cout Vdd Vdd Vdd + V V + th th --
Pass-Transistor Design
Solving the Threshold Voltage Drop problem in CMOS:
A=Vdd + V th In=Vdd ON
+
Pass-Transistor Design
A A B B
P0
P1
F(A,B)
P2
P3
Function Generator
Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 8
Pass-Transistor Design
Full 1-bit Adder
A A S
A S
CO
A
CO
B
Prof. V.G. Oklobdzija
C
9
Pass-Transistor Design
Compact ALU Example (IBM PC/RT) Circ. 1984
10
Control Lines A - inputs Odd Operation Arithmetic A+B A+B+1 A-B B-A B+1 +1 A+1 +1 Logical 1 B 1 1 1 1 1 1 1 0 1 1 A 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 1 0 0 1 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 Subtract Subtract Increment 2s compl Increment 2s compl Add 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 1 1 1 0 1 1 0 1 1 1 1 0 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 K1 K2 Qn A A Even B Odd B B - inputs Even Odd
Output Control
Even
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
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Pass-Transistor Design
Function Generator
VH
f
A
CO
K2
VH
CO
CI
A
K2
A K1
Carry Generator
Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 12
13
Review of CMOS
Prof. Vojin G. Oklobdzija
14
CMOS Basics
Vdd ( A + B)
Karnaugh Map of Function F
F
F 0 B 1
0 1 1
1 1 0
B)
15
CMOS Basics
16
CMOS Basics
covering ones : D( A + B C ) B A D C 1 D 1 0 0 0 0 0 0 0 0 D 1 1 B 0 0
F
A
0 A 1
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CMOS Basics
A complex path example:
B
VDD
E
C Output
C E
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CMOS Basics
Primitive gates: More complex blocks are realizable in CMOS
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CMOS Deficiencies:
Various remedies:
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A A B B AB
+
AB AB
+
AB
B (a)
Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits
(b)
21
AB
AB
AB
AB
22
CMOS Basic
Inverter Transfer function:
Logic voltage levels are VOH and VOL and VIL and VIH The inverter transfer function lie within the shaded region
VDD VOH
VIH
Vout
VIL
VOL
23
A VDD
0.5VDD
D 0 0
Prof. V.G. Oklobdzija
Vtn
0.5VDD
T2
V0(t) t
Vin(t)
T1
CL
+ VDD
td
tf
Prof. V.G. Oklobdzija
tr
25
26
VDD
Ic CL
n-DEVICE
Ic VO
n-DEVICE
R c
CL
VO
SATURATION :
VO VDD Vin
VDD
LINEAR :
0 VO VDD Vin
VDD
p-DEVICE
p-DEVICE
R c
Ic
t=0 n-DEVICE
Ic CL VO
n-DEVICE
CL
VO
SATURATION
LINEAR
27
During the static state there is no current Current is only present during transistion:
0 tf tr
VDD
Short circuit current (crow-bar current) Charging and discharging of the output capacitor Leakage Current
VDD
28
29
a0
(a)
CL
a7 a6 a5 a4 a3 a2 a1
Case 2
Case 3
CL (c)
a0
a7
a4
a3 a0
(b)
CL
Cin1
Cin2
Cout
Discharge Id
Discharge Id
31
Id RND7
Id
Cin1
Cin2
RND2
Cout
RND7Cin1+RNORCin2+RND2Cout
Prof. V.G. Oklobdzija Advanced Digital Integrated Circuits 32
Fan-out of a gate
Represented as a capacitive load at the output
Number of CMOS blocks in the path. Wire delay connecting various blocks.
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34
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