8085 interrupts

8085 Interrupts
Maskable
INTR RST vectored

Non-Maskable
TRAP

Vectored
RST5.5, RST6.5, RST7.5, TRAP

Interrupt process
enable by writing EI. mp checks INTR line at each instruction. if INTR is high, mp completes the current instr, disables Interrupt Flip-flop, sends INTA signal. An RST instru is inserted by INTA through external hardware. Mp saves the memory address of the next instru into stack. Program control is transferred to CALL location. The service routine starts at CALL location. At the end of the subroutine Int Flag is enabled again by EI instru. The last instr of the subroutine is RET to trasfer back the prog control to its orginal address.

RST instructions
8 RST instructions
+5v
RST0 RST1 RST2 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 C7 CF D7 DF 0000 0008 0010 0018 Mnemon ics Binary code D7 D6 D D 5 D 4 D 3 D 2 D 1 Hex Call Lo cat ion

1 1 1 0 1 1 1 1 Enable

RST3

EF to data bus

RST4
RST5 RST6 RST7

1
1 1 1

1
1 1 1

1
1 1 1

0
0 1 1

0
1 0 1

1
1 1 1

1
1 1 1

1
1 1 1

E7
EF F7 FF

0020
0028 0030 0038

Write a program to count continuously in binary with one second delay between each Count. Service routine at XX70H to flush FFH five times when the interrrupt occurs with some appropriate delay between flash

Main program

Service routine XX70: SERV: PUSH B PUSH PSW MVI B, 0AH MVI A, 00H OUT PORT1 MVI C, 01H CALL DELAY CMA DCR B JNZ FLASH POP PSW POP B EI RET

LXI SP, XX99H EI MVI A, 00H NXTCNT: OUT PORT1 MVI C, 01H CALL DELAY INR A JMP NXTCNT

FLASH:

Interrupt instr: EF At 0028H JMP xx70H

Issues in implementing interrupts

Is there a minimum pulse width required for the INTR signals?
MP checks INTR, one clk period before the last-T state of an instruction cycle, therefore, the INTR pulse should be high at least for 17.5 T-states.

How long can the INTR pulse stay high? Can the MP be interrupted again before the completion of the first interrupt service routine?