1. What is the difference between wire and reg? Ans) Net types: (wire,tri)Physical connection between structural elements.

Value assigned by a continuous assignment or a gate output. Register type: (reg, integer, time, real, real time) represents abstract data storage element. Assigned values only within an always statement or an initial statement. The main difference between wire and reg is wire cannot hold (store) the value when there is no connection between a and b like a->b, if there is no connection in a and b, wire loose value. But reg can hold the value even if there in no connection. Default values:wire is Z,reg is x.

2. Define Timing Scoring in FPGA ? Timing score is the total time in picoseconds of all the paths that fail timing constraints. Paths that meet constraints, regardless of the amount of slack, are not counted for the timing score. If your design meets the timing constraints the score will be zero. If for example you have two failing paths, one failing by 120 picoseconds and another by 75 picoseconds, your timing score will be 120 + 75 = 195.

3. What is speed grade for an FPGA device ? A speed grade is supposed to be relative and representitave metric of how fast an FPGA can perform. Example :The -L devices are specified to run at 0.9V and all device specifications will only be guaranteed to work at this voltage. There will be separate speed files and data sheet specifications for these devices that will be the same for most parameters as the same speed grade in a regular 1.0V device, but there will be differences in some parameters. Different performance designations, specifications and speeds files is absolutely correct,

i.e. a -1L is guaranteed to perform like a -1L, and performance when operated as a -1 is purely circumstantial. You are approaching the binning strategy from the wrong direction. A -1L is indeed a -1 which is fast enough to operate at similar performance when powered at 10% lower voltage. This means that not all 1's can be binned to -1L requirements, and all -1Ls are not guaranteed by testing to operate at -1 requirements. For 100% compliance to operating specs., they must be treated as independent product grades.

For Virtex-5, -1 is the slowest (and cheapest) while -3 is the fastest (and most expensive). Note that -3 is not available in industrial grade. The datasheet (ds202.pdf) highlights the specific resource performance differences between the different speed grades. The selection ultimately is driven by the performance you need for your specific design.

4. What is difference between Inter and Intra assignment delay? Ans. //define register variables reg a, b, c;

//intra assignment delays initial beg vin a = 0; c = 0; b = #5 a + c; //Take value of a and c at the time=0, evaluate //a + c and then wait 5 time units to assign value //to b. end

//Equivalent method with temporary variables and regular delay control initial begin a = 0; c = 0; temp_ac = a + c; #5 b = temp_ac; //Take value of a + c at the current time and

//store it in a temporary variable. Even though a and c //might change between 0 and 5, //the value assigned to b at time 5 is unaffected. End

5) What is meant by inferring latches,how to avoid it?

Consider the following : always @(s1 or s0 or i0 or i1 or i2 or i3) case ({s1, s0}) 2'd0 : out = i0; 2'd1 : out = i1; 2'd2 : out = i2; endcase

in a case statement if all the possible combinations are not compared and default is also not specified like in example above a latch will be inferred ,a latch is inferred because to reproduce the previous value when unknown branch is specified. For example in above case if {s1,s0}=3 , the previous stored value is reproduced for this storing a latch is inferred. The same may be observed in IF statement in case an ELSE IF is not specified. To avoid inferring latches make sure that all the cases are mentioned if not default condition is provided.

6.What is WLM(wire load model) ? The function of wire load model is to estimate the interconnect delay A wire load model describes wire load value according to the fan-out number of a net and the physical size of the block encloses the net

A wire load model consists of a set of wire load tables. Each table contains wire load data such as capacitance, resistance, and the average wire length for a series number of fan-out.

7. what is time borrowing in latches ? Time borrowing means one latch takes the (a portion of ) clock period from its adjacent latches by inserting buffers in clock network in proper position. Time borrowing latch unlike an edge-triggered FF, a level-clocked latch is transparent during the active period of the clock. This makes the analysis and design of level-clocked circuits more complex than edge-triggered circuits, since combinational blocks are not insulated from each other by the memory elements, and multicycle paths are possible when the data is latched during the transparent phase of the clock. Even though this transparent nature introduces an additional level of complexity to the design phase, level-clocked circuits are often used for high-performance designs since they offer more flexibility than edge-triggered circuits, both in terms of the minimum clock period achievable and the minimum number of memory elements required.

8. which is transparent flip flop or latch ? why ?

Flip-flops can be either simple (transparent) or clocked; the transparent ones are commonly called latches.[1] The word latch is mainly used for storage elements, while clocked devices are described as flip-flops. Flip-Flops and Registers

9. What is the advantage of SystemVerilog over traditional verilog ? Ans) SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog. SystemVerilog is Structured (design) Structured programming is often (but not always) associated with a "top-down" approach to design. The structured program theorem provides the theoretical basis of structured programming. It states that three ways of combining programssequencing, selection, and iterationare sufficient to express any computable function

Object-oriented (verification) Object-oriented programming (OOP) is a programming paradigm using "objects" data structures consisting of data fields and methods together with their interactions to design applications and computer programs. Programming techniques may include features such as data abstraction, encapsulation, messaging, modularity, polymorphism, and inheritance. Many modern programming languages now support OOP.

10.What is OCV analysis ? On-Chip Variation(OCV) Analysis : On Chip Variations or inter-die variations could be caused due to : IR drop Vt variations Channel length variation So the normal flow of qualifying the Timing with plain worst and best corners is no more enough. Performing On-Chip Variation Analysis[From PrimeTime UG] To perform on-chip variation analysis, use the set_operating_conditions command. Because on-chip variations consider that cells and nets can operate at slightly different operating conditions, you must consider a minimum value and a maximum value for each delay of the design.Specify two operating conditions to represent the lower and upper bounds of the operating condition for on-chip variation, keeping the following guidelines in mind. Each delay of the design has an uncertainty bounded by the minimum value (computed for the minimum operating condition) and maximum value (computed for the maximum operating condition). Minimum paths are computed using the delay of the minimum operating condition. Maximum paths are computed using the delay of the maximum operating condition.

Example 1 This command sequence performs timing analysis for on-chip variation 20 percent below the worst-case commercial (WCCOM) operating condition. It also performs clock reconvergence pessimism removal for paths with positive slack. pt_shell> set_operating_conditions -analysis_type on_chip_variation WCCOM pt_shell> set_timing_derate -min 0.8 -max 1.0 pt_shell> report_timing -remove_clock_reconvergence_pessimism 0.0 Example 2 This command sequence performs timing analysis for on-chip variation between two predefined operating conditions:WCCOM_scaled andWCCOM.It also performsclock reconvergence pessimism removal for paths with slack less than 0.4 ns.

pt_shell> set_operating_conditions -analysis_type on_chip_variation \ ? -min WCCOM_scaled -max WCCOM

11. What are timing exceptions ? Ans) The increasing use of timing-exception constraints requires a reliable verification solution at both the register-transfer and netlist levels. Utilizing default timing has a real cost in the ultimate resulting hardware design. By optimizing every path--whether it's required or not-- the design's quality of results (QOR) suffers. At the leading edge of design, every square millimeter of area, nanosecond of delay, and milliwatt of power matter. Clearly, design teams have become increasingly unwilling to suffer any QOR penalty. DEFAULT-TIMING EXCEPTIONS Exceptions to the default-timing requirement come in two forms. They're referred to as false or multicycle paths. In a false path, there is a logical connection from one point to another. Because of the way the logic is designed, though, this path can never control the design's timing. For example, a small piece of a design might look like the one in Figure 1.

Figure 1: This is an illustrative example of a False Path. MULTI-CYCLE PATHS Multi-cycle paths occur when there's a valid path from one place to another, but the control logic that sequences the data through the path uses multiple clock cycles for each data item. Typically, this happens when the receiving logic only needs a valid piece of data every few clocks. Defining the path as multi-

cycle allows the synthesis tool to optimize for area rather than speed. An example design is shown in Figure 2.

Figure 2: This is an Illustrative example of a Multi_cycle path.

Figure 3: A proposed flow which only uses exceptions which are proven correct is what we call a "Reliable Exception Flow".