II.SEQUENTIAL LOGIC CIRCUITS USING VHDL 7.

FLIP FLOPS
AIM: To design and simulate JK, RS ,D and T using VHDL.

APPARATUS REQUIRED: PC with windows XP XILINX 9.2i software

PROCEDURE: Open the Xilinx 9.2i software Close if any other project is opened Open a new file from file menu and specify the project name Choose the language and simulator to be used In new source wizard select VHDL module, then in the next window assign I/O pins and select finish, now the design summary will be displayed Enter the code to be executed, save it and synthesis the entered code If the program is in structural model we have to add component in sources, do right click and add source. To simulate the output the test bench waveform is chosen from the new source. Before giving input select behavioral simulation in sources, now give the input in simulation window and save it. Now simulate the wave form and verify the output.

JK FLIPFLOP:
PROGRAM : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity jkff is Port ( j,k,clk : in STD_LOGIC; q : inout STD_LOGIC); end jkff; architecture Behavioral of jkff is begin process(j,k,clk) begin if(clk'event and clk='1') then if(j='0')and(k='0')then q<=q; elsif(j='1')and(k='0')then q<='1'; elsif(j='0')and(k='1')then q<='0'; elsif(j='1')and(k='1')then q<=(not q); end if; end if; end process; end Behavioral;

RTL SCHEMATIC DIAGRAM FOR JK FLIPFLOP:

OUTPUT WAVEFORM FOR JK FLIPFLOP:

SR FLIPFLOP : PROGRAM : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity rsff is Port ( s,r,clk : in STD_LOGIC; q : inout STD_LOGIC); end rsff; architecture Behavioral of rsff is begin process(s,r,clk) begin if(clk'event and clk='1')then if(s='0' and r='0')then q<=(not q); elsif(s='0' and r='1')then q<='0'; elsif(s='1' and r='0')then q<='1'; elsif(s='1' and r='1')then q<=X; end if; end if; end process; end Behavioral;

RTL SCHEMATIC DIAGRAM FOR SR FLIPFLOP :

OUTPUT WAVEFORM FOR SR FLIPFLOP :

D FLIPFLOP :
PROGRAM : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity dff is Port ( D : in STD_LOGIC; clk : in STD_LOGIC; Q : out STD_LOGIC); end dff; architecture Behavioral of dff is begin process(D,clk) begin if(clk'event and clk='1')then Q<=D; end if; end process; end Behavioral;

RTL SCHEMATIC DIAGRAM FOR D FLIPFLOP :

OUTPUT WAVEFORM FOR D FLIPFLOP :

T FLIP FLOP:
PROGRAM : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity tff is Port ( t,clk : in STD_LOGIC; q,qb : inout STD_LOGIC); end tff; architecture Behavioral of tff is begin process(t,clk) begin if(clk'event and clk='1')then if(q\=0 and qb\=0) then q<=0; else q<=(not q); end if; end if; end process; end Behavioral;

RTL SCHEMATIC DIAGRAM FOR T FLIPFLOP :

OUTPUT WAVEFORM FOR T FLIPFLOP:

8.COUNTER
AIM: To design and simulate UP-DOWN counter using VHDL.

APPARATUS REQUIRED: PC with windows XP XILINX 9.2i software

PROCEDURE: Open the Xilinx 9.2i software Close if any other project is opened Open a new file from file menu and specify the project name Choose the language and simulator to be used In new source wizard select VHDL module, then in the next window assign I/O pins and select finish, now the design summary will be displayed Enter the code to be executed, save it and synthesis the entered code If the program is in structural model we have to add component in sources, do right click and add source. To simulate the output the test bench waveform is chosen from the new source. Before giving input select behavioral simulation in sources, now give the input in simulation window and save it. Now simulate the wave form and verify the output.

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity upc is Port ( clk : in STD_LOGIC; updown : in STD_LOGIC; clr : in STD_LOGIC; q : out STD_LOGIC_VECTOR (3 downto 0)); end upc; architecture Behavioral of upc is signal tem : std_logic_vector( 3 downto 0); begin process(clr,clk) begin if(clr='1')then tem <="0000"; elsif(clk'event and clk='1') then if(updown='1') then tem <= tem+1; else tem <= tem-1; end if; end if; end process; q <= tem; end Behavioral;

RLT SCHEMATIC DIAGRAM :

OUTPUTWAVEFORM:

9.SHIFT REGITERS
AIM: To design and simulate SISO,SIPO ,PISO and PIPO using VHDL

APPARATUS REQUIRED: PC with windows XP XILINX 9.2i software

PROCEDURE: Open the Xilinx 9.2i software Close if any other project is opened Open a new file from file menu and specify the project name Choose the language and simulator to be used In new source wizard select VHDL module, then in the next window assign I/O pins and select finish, now the design summary will be displayed Enter the code to be executed, save it and synthesis the entered code If the program is in structural model we have to add component in sources, do right click and add source. To simulate the output the test bench waveform is chosen from the new source. Before giving input select behavioral simulation in sources, now give the input in simulation window and save it. Now simulate the wave form and verify the output.

SERIAL IN SERIAL OUT:

PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity siso is Port ( clk : in STD_LOGIC; re : in STD_LOGIC; s : in STD_LOGIC; q : out STD_LOGIC); end siso; architecture Behavioral of siso is signal reg:STD_LOGIC_VECTOR(4 DOWNTO 1); begin process(re,clk) begin if(clk'event and clk ='1')then if(re ='1')then reg <= "0000"; q <= '0'; else reg <= s & reg(4 downto 2); q <= reg(4); end if; end if; end process; end Behavioral;

RTL SCHEMATIC DIAGRAM FOR SERIAL IN SERIAL OUT:

OUTPUT WAVEFORM:

SERIAL IN PARALLEL OUT: PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity SIPO is Port ( data,clk,reset : in STD_LOGIC; q : out STD_LOGIC_VECTOR (4 downto 1)); end SIPO; architecture Behavioral of SIPO is signal reg: STD_LOGIC_VECTOR(4 DOWNTO 1); signal count:std_logic_vector(3 downto 1); begin process(clk,reset) begin if(clk'event and clk='1')then if(reset='1')then reg<="0000"; q<="0000"; count<="000"; else reg<=data & reg(4 downto 2); count<=count+1; q<=reg; if(count="100")then count<="000"; end if; end if; end if; end process; end Behavioral;

RTL SCHEMATIC DIAGRAM FOR SERIAL IN PARALLEL OUT:

OUTPUT WAVEFORM FOR SERIAL IN PARALLEL OUT:

PARALLEL IN SERIAL OUT: PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity pis017 is Port ( input : in STD_LOGIC_VECTOR (3 downto 0); clk,reset,input_accept : in STD_LOGIC; q : out STD_LOGIC); end pis017; architecture Behavioral of pis017 is signal reg:std_logic_vector(3 downto 0); signal count:std_logic_vector(2 downto 0); begin process(clk,reset) begin if(reset='1')then count<="000"; reg<="0000"; elsif(clk'event and clk='1')then if(input_accept='1')then reg<=input; else q<=reg(0); reg<='0' & reg(3 downto 1); count<=count+1; end if; if(count="100")then count<="000"; reg<="0000"; end if; end if; end process; end Behavioral;

RTL SCHEMATIC DIAGRAM FOR PARALLEL IN SERIAL OUT:

OUTPUT WAVEFORM FOR PARALLEL IN SERIAL OUT:

PARALLEL IN PARALLEL OUT: PROGRAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity ppiippoo is Port ( clk,reset : in STD_LOGIC; input : in STD_LOGIC_VECTOR (4 downto 1); output : out STD_LOGIC_VECTOR (4 downto 1)); end ppiippoo; architecture Behavioral of ppiippoo is signal reg:STD_LOGIC_VECTOR(4 downto 1); begin process(clk,reset) begin if(clk'event and clk='1')then if(reset='1')then reg<="0000"; output<="0000"; else reg<=input; output<=reg; end if; end if; end process; end Behavioral;

RTL SCHEMATIC DIAGRAM FOR PARALLEL IN PARALLEL OUT:

OUTPUT WAVEFORM FOR PARALLEL IN PARALLEL OUT:

10.FREQUENCY DIVIDER
AIM: To design and simulate frequency divider using VHDL.

APPARATUS REQUIRED: PC with windows XP XILINX 9.2i software

PROCEDURE: Open the Xilinx 9.2i software Close if any other project is opened Open a new file from file menu and specify the project name Choose the language and simulator to be used In new source wizard select VHDL module, then in the next window assign I/O pins and select finish, now the design summary will be displayed Enter the code to be executed, save it and synthesis the entered code If the program is in structural model we have to add component in sources, do right click and add source. To simulate the output the test bench waveform is chosen from the new source. Before giving input select behavioral simulation in sources, now give the input in simulation window and save it. Now simulate the wave form and verify the output.

PROGRAM :

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity tfli is Port ( t : in STD_LOGIC; clr : in STD_LOGIC; clk : in STD_LOGIC; q : inout STD_LOGIC); end tfli; architecture Behavioral of tfli is begin process (t,clk,clr) begin if(clr='1')then if(clk' event and clk = '1')then if(t='0')then q <= q; else q <= (not q); end if; end if; else q <= '0'; end if; end process; end Behavioral;

RTL SCHEMATIC DIAGRAM FOR FREQUENCY DIVIDER:

OUTPUT WAVEFORM FOR FREQUENCY DIVIDER: