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Virtuoso Schematic Composer VHDL Interface. VHDL In for Design Framework II:

VHDL In for Design Framework II can convert a VHDL structural or behavioral description into one of three forms in Cadence database access (CDBA) storage format:

ÿ Schematic view.

ÿ Netlist view.

ÿ VHDL text views.

If the VHDL design is converted into schematics, the schematics can be edited with the Composer schematic editing tool. Fig3 shows the design flow using the VHDLIn.

editing tool. Fig3 shows the design flow using the VHDLIn. Fig3: Design Flow Using VHDL In.

Fig3: Design Flow Using VHDL In.

*Leapfrog: The Cadence VHDL Analyzer & Simulator.

Using the VHDLIn to convert a VHDL code (.vhd file) into the Schematics:

1. Open the UNIX Terminal window and follow the following commands:

~source /usr/local/cadence/00setup.ic

~setenv CDS_Netlisting_Mode Digital ~icfb &

2. The Cadence CIW (Command Interpreter Window) opens.

Copy the following 5 basic required reference libraries into the CDS.lib file:

basic, sample, US-8ths, std, IEEE. DEFINE basic /usr/local1/cadence/ic4.4.6/tools/dfII/etc/cdslib/basic DEFINE sample /usr/local1/cadence/ic4.4.6 /tools/dfII/samples/cdslib/sample DEFINE US_8ths /usr/local1/cadence/ic4.4.6/tools/dfII/etc/cdslib/sheets/US_8ths

DEFINE std /usr/local1/cadence/ic4.4.6/tools/leapfrog/files/std DEFINE ieee /usr/local1/cadence/ic4.4.6/tools/leapfrog/files/IEEE Alternatively, this can be done using the CIW, by selecting Tools – Library Path Editor & specifying the Reference libraries & their respective paths.

3. Now, in the CIW, select File – Import VHDL. The VHDL Import form opens (See Fig 4):

3. Now, in the CIW, select File – Import VHDL. The VHDL Import form opens (See

Fig 4: VHDL Import form view.


Locate the directory for the Structural VHDL source files you want to import – Double

click on a directory in the Files List Box.

5. Select and add each structural VHDL source file (.vhd files) you want to import from

the File Name List Box to the Import Files List Box.

6. Press Tab to go to the Target Library Name field.

7. In the Target Library Name field, enter the target library name (vhdl_design, for eg.,)

that you want to import the source files into. Press Tab to finish.

If you specify a target library name that does not exist, a dialog box opens, asking you if you want to create the new library. If you click “Yes”, the New Library form opens. Enter the library name and the directory where you want the library located. Select “Don't need a techfile”, and click OK. The new Target library gets created. 8. Set the “Import Structural Architectures” to Schematics, as the requirement is to convert the Structural VHDL model to the Schematic.

9. In the Reference Libraries field, add sample, std, and IEEE to the list – basic &

US_8ths are already present.

10. Although you are generating a schematic in this example, you do not have to use the Schematic Generation Options form. You are only using the default settings for schematic generation to import this example design. However, the form remembers the last schematic generation options used. So if you have recently performed schematic generation, click on the Schematic Generation Options bar to open that form and click Defaults to reset all the options, then click OK.

11. Click Apply.

The VHDL Import process gets started. At the end of the import process, we can either view the log-file (if the process is successful), or the error-file (if it is unsuccessful) as a “Vhdlin” summary file. The target library will contain the results: Design Cellviews – Structural views (entity cellview file -Composer Schematic).

Viewing the Design's Cellviews:

Once the import process has completed successfully, you can examine the cellviews in the target library (such as the structure cellview) to check the results of importing to a schematic.

1. In the CIW, select Tools - Library Manager.

The Library Manager window opens (See Fig5).

Manager . The Library Manager window opens (See Fig5). Fig 5: Cadence Library Manager View 2.

Fig 5: Cadence Library Manager View

2. In the Library list box, click the Target library name, which contains the VHDLIn


The Cell list box displays the cell, for which we had imported the VHDL model to get the Schematic.

3. In the Cell list box, click the cell name.

The View list box displays three cellview names for the full adder design: entity, structure, and symbol. In the View list box, click the structure cellview file name. The Composer schematic editor opens, displaying the contents of the structure cellview, which is the Schematic for the circuit.

Generating the SPICE netlist for the obtained Schematic:

1. Rename the “Structure” cellview as “Schematic” as the Netlister does not recognize

the name “Structure”.

2. From Schematic editor window click on menu Tools->Simulation->Other.

3. Now, from the Menu on top of the Virtuoso Schematic window, Click on “Simulation”

– Initialize. 4. In the pop up form specify your run directory and click OK.

5. Initialize Environment form pops up. Select simulator name "hspice" from the cyclic

field and click OK.

6. Again, from Schematic window select menu Simulation->"Netlist & Simulate".

7.On the pop up form select Run Action "netlist". Click OK.

8.When process is complete, the Netlist is saved in the run directory.

9. In order to generate the Hierarchical netlist, repeat the same process, selecting the

“Use Hierarchical Netlister” on the Menu – Simulation in the Schematic Editor window.