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CS-CMOS: A Low-Noise Logic Family for Mixed Signal SoCs

Ajay Taparia, Member, IEEE, Bhaskar Banerjee, Member, IEEE, and T. R. Viswanathan, Life Fellow, IEEE
AbstractManaging the switching-noise in mixed-signal systems fabricated on a single chip is becoming increasingly challenging. This needs substantial overheads in both area and power. Existing logic families that minimize switching-noise generation, such as current-steering logic (CSL), current-balanced logic (CBL) etc. require considerably more power than traditional CMOS implementations. We present a new logic family called the current-steering CMOS (CS-CMOS) obtained by a simple modication keeping the core CMOS structure in tact to preserve its most attractive features. This family not only reduces the switching noise by a factor of ten but also delivers ve times higher speed than CSL and CBL for the same power consumption. Experimental results comparing 15-stage ring-oscillators congured in the CSL and CS-CMOS families and fabricated in a 0.18 m process show that their energy-delay-products are 6.5 fJ*ns and 1.52 fJ*ns respectively. The usefulness of this new logic family is further demonstrated by synthesizing a cell library of CS-CMOS gates and by using it to simulate benchmark circuits, a decimation lter and a frequency divider. Index TermsCurrent-balanced logic (CBL), current-steering CMOS (CS-CMOS), current mode logic, current steering logic, mixed signal system-on-chip (SoC), power supply noise.

Fig. 1. CS-CMOS inverter.

I. INTRODUCTION

LSI systems-on-chip (SoCs) use CMOS digital-logic circuits because they consume very low power, have high packing density and are easy to design [1], [2]. Most of the power consumed by CMOS gates is due to displacement currents [3] drawn during state-transitions for charging and discharging wire and device capacitances. These increase linearly with the operating frequency and ow through the power supply wires, ground lines, parasitic inductances and capacitances causing ringing and voltage drop. This is the dominant source of substrate noise [4]. Injection of this noise into sensitive analog circuits can cause serious impairments in their performance. Typical examples are increased jitter in voltage-controlled oscillators and reduction in the dynamic range of analog-to-digital converters, etc. [4][6].

The problem of switching noise is dealt in three parts: noise generation, its propagation through the substrate, and injection into analog circuits [4]. The focus here is to minimize the generation of switching noise and keeping the impulse current local to where it is generated [7]. Among the existing logic families that use this approach are current steering logic (CSL) [3] and current balanced logic (CBL) [8]. Both of these families reduce noise because they draw a constant-current from the supply. But the power consumed is at least 10 times higher than the equivalent CMOS implementation [3], [8]. Differential currentmode logic is useful at higher frequencies because of its reduced output voltage swing and power dissipation [9]. A variation of this logic that allows it to be used as a single-ended family is presented in [10]. Its use is limited because for operating at very low currents it needs a large resistance. In Section II a new logic family called the current-steering CMOS logic (CS-CMOS) is proposed for mixed-signal applications [7]. The transfer characteristic of the CS-CMOS inverter is discussed in detail. Its low noise properties are compared with those of CSL and CBL families through simulations of ISCAS85 benchmarks circuits, a frequency divider and a decimation lter. In Section III, measured results comparing CSL and CS-CMOS ring oscillators are presented. II. CS-CMOS LOGIC A. Static Transfer Characteristics

Manuscript received February 19, 2010; revised August 01, 2010; accepted September 30, 2010. Date of publication November 29, 2010; date of current version October 28, 2011. This work was supported in part by Agere Systems Inc., Texas Instruments Inc., and Intersil Inc. and Silicon Laboratories. A. Taparia is with Maxim Integrated Products, Sunnyvale, CA 94086 USA (e-mail: taparia@ieee.org). B. Banerjee is with the Erik Jonsson School of Engineering, University of Texas at Dallas, TX 78759 USA (e-mail: bhaskar.banerjee@utdallas.edu). T. R. Viswanathan is with the Electrical Engineering Department, University of Texas, Austin, TX 75080 USA (e-mail: tviswanathan@ece.utexas.edu). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TVLSI.2010.2089812

CS-CMOS is obtained by a simple current-steering modication to the standard CMOS family. As in a CMOS inverter, a pair of complimentary transistors connected in series forms the core of the proposed CS-CMOS inverter, as shown in Fig. 1. Since CMOS gates do not draw any appreciable current in their static states, constant-current operation requires additional paths for the d-c bias current to ow. A pair of complimentary transistors is added in parallel for this purpose. A P-channel transistor sources a constant-current to each gate.

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TABLE I DEVICE DIMENSIONS FOR CS-CMOS, CSL AND CBL

When is HIGH is OFF and is ON. The output node voltage is LOW turning ON and ows in . Note that minimum output LOW voltage for CS-CMOS is same as in CMOS. This is not so for the other single-ended ratioed logic families such as CSL and CBL. When is low the output node is HIGH, conducts and is steered into it. Assuming the square-law model for the transistors, maximum output voltage can be computed as where (1)

Fig. 2. DC voltage transfer characteristics of the CS-CMOS inverter.

In the above equation represents the carrier mobility, is the oxide capacitance per unit-area, represents the width and , the length of the transistor. To have an appreciable overdrive voltage for a given current, minimum-width devices are chosen for and . Such a choice causes minimal loading and hence does not appreciably affect the speed of the inverter. The node with the capacitor in Fig. 1 acts like a local power supply for the CMOS inverter . If , the inverter operates like a regular CMOS circuit in which there is an input voltage range for which both and will conduct simultaneously. When this happens a part of ows through this path between the node and ground. For , as increases from LOW to HIGH, will shut OFF before turns ON and for decreasing will shut OFF before turns ON. The ideal choice is to make . If the threshold voltages of are chosen to be equal to those of , this criterion cannot be met. This is because the magnitude of is the gate-source voltage of or given by (1). But if the threshold voltages of are chosen to be smaller than those of a reduction in hysteresis can be achieved. and are chosen such that Thus the threshold voltages for . For such a choice of threshold voltages, and become medium- devices and and will be normaldevices. In the 0.18 m process, the medium- (also called low- ) is 270 mV and the normalis around 520 mV. In most digitally-intensive mixed-signal systems, the use of multiple s is common and thus would add no extra cost [11] and gates built using medium- are used in performance-critical blocks to meet the delay constraints. Gates built using normal- devices are used in non-critical blocks to lower the overall leakage power. Based on these considerations, a set of device dimensions and a bias current are chosen as shown in Table I. These are used to investigate the DC transfer-characteristics of the inverter shown

in Fig. 2. Consider the output pull-up transition. Initially, when is HIGH, is LOW and carries the bias current . As decreases starts conducting. Now forms a current-biased p-channel differential- pair with acting as an active- load. Let the incremental d-c transconductance of the pair be and the output-conductance due to and in parallel, . Routine small-signal analysis, gives where (2) Here the lower-case symbols represent incremental quantities. Equation (2) indicates the presence of positive feedback in the CS-CMOS inverter. When we consider as an active load of the differential pair, it is easy to identify the circuit as a Schmidt-trigger containing positive feedback via the output of the inverter and the node . Initially as is HIGH, is small as is OFF. Furthermore is large since operates in its triode region. Hence the incremental gain is . As decreases, begins to conduct and decreases causing the gain to increase. leads to regeneration and switching. Thus the presence of positive feedback causes high gain during the transitions (see Fig. 2). Such a high gain does not happen in the other logic families having no feedback. Now consider the output pull-down transition. Initially, when is LOW, is ON. When it is in triode mode, the node is shorted to and the bias current ows through . in this state is the gate-source voltage given by (1) of which is diode-connected by . As increases, progressively conducts more current causing the output voltage to decrease. Until conducts there is shunt negative feedback in the circuit. When conducts the bias current is shared between all the three branches namely and . As rises further, falls, the current in decreases and that in increases until shuts OFF completely. During this process the Schmidt-trigger action makes the positive feedback greater than the negative feedback causing switching in the output transition. These switching transitions can be observed in the dc characteristics shown in Fig. 2. The positive feedback present in a CS-CMOS inverter can be useful in short-

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Fig. 3. CSL and CBL inverters.

is the load capacitance consisting of the wire and dewhere vice capacitances at the output node. For an output swing of 0.5 would require to V and a droop of 100 mV at the node be 5 times larger than the load capacitance . Restricting the number of fan-outs of a gate (typically 4) can keep the size of sufciently large and yet keep the size of the CS-CMOS gate manageable. For both CSL and CBL gates (see Fig. 3) the pull-up rise-time and delay are controlled by the bias curin CS-CMOS prorent, but the voltage across the capacitor vides a quadratic current similar to that in standard CMOS. In other words, the CS-CMOS inverter is essentially as fast as a CMOS inverter with the node acting as a local supply voltage and keeps the transient current local. The following well-known equations for the propagation delay [3] apply for CS-CMOS gates as well. Assuming a step input [3], we dene average propagation delay (4) (5) A key reason for the widespread use of digital CMOS is its very low power consumption. However, low noise implementations like CSL and CBL consume an order of magnitude higher power [1], [3], [8], [9], and [11]. CS-CMOS attempts to bridge which provides most of this gap by using the capacitor the charge during the pull-up operation. This boosts the performance of CS-CMOS substantially. The charge lost by CD during the pull-up is replenished by the bias current . The required bias current can thus be estimated as (6) Propagation delay versus average current consumed per gate for CS-CMOS, CSL and CBL inverters is shown in Fig. 4. These are from simulations of 15-stage ring oscillators operating from a 1 V supply. The device sizes are shown in Table I. For CSL and CS-CMOS inverters the bias current is adjusted . For CBL inverters the current by changing the voltage is adjusted by varying the supply voltage. It can be observed that the CS-CMOS inverters can achieve less than 1 ns delay for bias currents greater than 1 A. From Fig. 4 it can be seen that the propagation delay achieved by CS-CMOS is about a factor of four and ten better than CSL and CBL respectively. The output pull-up operation in CSL whereas the performance of and CBL is slew-limited by CS-CMOS is close to CMOS due to . For smaller the and in CBL are large devices, contributing to devices large capacitance at the output node. For much higher bias currents, however, CBL can be advantageous, as the devices will be smaller. From (4) and (5), note that the propagation delay of CS-CMOS (and CSL) is independent of the supply voltage whereas the delay of a CMOS and CBL will vary strongly with supply voltage [3]. The hysteresis of the CS-CMOS inverter changes at process and it is the corners. The propagation delay is a function of worst for slow NMOS and fast PMOS. The calibration techniques proposed in [3] can mitigate the variations due to process

Fig. 4. Propagation delay for CSL, CBL, and CS-CMOS inverters at various process corners.

channel technologies as a means of boosting the gain at the logical threshold. The hysteresis of the CS-CMOS inverter strongly depends on the threshold voltages of . In the worst process corner (with skewed devices slow NMOS, fast PMOS) the hysteresis is about 30 mV as compared to few mVs (see Fig. 2) under typical conditions. This variation in hysteresis directly contributes to increase in propagation delay. The variation of hysteresis due to bias current is negligibly small. Techniques to mitigate this variation in delay will be addressed in the next section. The choice of mediumdevices sets the switching threshold to about . Such a choice is desirable as it results in approximately equal values for noise margins around the LOW and HIGH states. The CS-CMOS gate can provide an open-drain current-output (scaled ) if an additional N-channel transistor is added in parallel with which conducts when the output of the gate is HIGH. B. Dynamic Characteristics The speed of low noise logic families [3], [8] is limited by the bias current . In CS-CMOS the additional capacitor added at the node (see Fig. 2) acts as a decoupling capacitor. It supplies most of the charge required to pull up the load-capacitance. Although the current supplied from the power supply makes it operate virtually like a regis xed, the capacitor ular CMOS circuit. The size of the for CS-CMOS gates is at the power chosen as follows. For an allowable change during the pull-up transistion, the value of supply node required can be estimated as (3)

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Fig. 6. Figure of merit for CS-CMOS, CSL, and CBL inverters driving a fanout of 4. Fig. 5. Energy Delay Product for CBL, CSL, and CS-CMOS inverters at various process corners.

TABLE II FIGURE OF MERIT FOR LOGIC FAMILIES

Fig. 7. Parasitic capacitances in a CS-CMOS inverter used to estimate the fraction of current owing into the power supply.

and temperature. Fig. 4 shows plots for various process corners, with supply voltage calibrated to obtain the required bias current. Because of current biasing both CSL and CS-CMOS logic are insensitive to supply variations. The energy delay product (EDP) dened by (7) is plotted for all the three families in Fig. 5. Unlike in CMOS logic, where the power dissipation is activity-dependent, the xed bias current makes the power dissipation in CSL, CBL and CS-CMOS independent of the activity. Thus to achieve high power efciency CS-CMOS, CBL and CSL should be used in applications having a higher level of switching activity. In Fig. 5, EDP is plotted as a function of bias current at various process corners. The trend is similar to that of propagation delay. The EDP of the CS-CMOS inverter is about factor 10 and 100 less than CSL and CBL respectively. A gure of merit FOM which considers other important parameters like area and noise margin can also be used to compare these logic families (8) The goal is to minimize the gure of merit for a logic family. The estimated values of FOM for the three logic families, when consuming a 1 W of power from a 1 V power supply, is shown in Table II. It can be seen that CS-CMOS performs about 10 times better than CSL. When operating at much higher currents

than the value used in constructing Table II, CBL and CSL families have a better gure of merit (see Fig. 6). This is due to their smaller area than CS-CMOS. Fig. 6 clearly shows that A per gate and CSL, CS-CMOS is superior to CBL for for A per gate. C. Current Supply Spikes Displacement current pulses owing through the inductances of ground wires causes noise spikes known as ground bounce [4]. Noise is also injected into the substrate from the source and drain nodes of the MOS devices during transitions. This is known as capacitive noise coupling to the substrate. Yet another noise source is due to impact ionization. CSL, CBL and CS-CMOS gates have minimal displacement currents in the power-supply line because of the constant-current operation. Thus capacitive coupling into the power supply/substrate is the dominant source of noise injection for these logic families [4]. The parasitic capacitances associated with the CS-CMOS inverter are shown in Fig. 7. These are the CCS (the drain-well capacitance of the PMOS transistor ) and the capacitor . When a step input is applied to the inverter a displacement current is supplied from the node to pull up the output node. A fraction of this current is supplied from power supply through the parasitic capacitance but most of it is delivered by . This fraction is estimated as (9) This fraction can be reduced either by increasing the value of or by decreasing the value of . As seen previously, the value of is chosen based on the load capacitance. depends on the size of the transistor

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TABLE III PROPAGATION DELAY FOR ISCAS85 BENCHMARK CIRCUITS

Fig. 8. PeakPeak current spikes owing into the power supply due to CBL, CSL, and CS-CMOS ring oscillators.

. This can be reduced using standard layout techniques. The drain-well capacitance of is about 1 fF whereas the capacitor used is at least 10 fF. Thus a 20 dB attenuation of supply spikes can be achieved by having a capacitor ratio of 10. In the future as feature size shrinks reduces and the device size required to deliver becomes smaller. Hence, for short-channel technologies better noise attenuation is expected. The fraction of current owing through the supply for a CSL and CBL gates can be estimated [4] to be (10) where is the total load capacitance at the output of a CSL/CBL gate. As CSL and CBL gates do not have the decoupling capacitance , the capacitor ratio required will be in CS-CMOS thus provides an larger. The capacitance extra degree of freedom in choosing the desired attenuation. To compare the noise performance of the families, 15-stage ring oscillators were designed and operated at various bias currents. The device sizes used are listed in Table I. The decoupling capacitor of 10 fF and 20 fF are chosen for the simulation of the CS-CMOS ring oscillator. The results are presented in Fig. 8. As the supply and ground bounce depend on the peak magnitudes of the supply current spikes, smaller spikes indicate better noise performance. As expected from (9) and (10), reduces the magnitude of the power supply spikes at the expense of larger chip-area. CBL gates have poor noise performance at lower bias currents because longer channel lengths are required for , thus having a higher parasitic capacitance . D. CS-CMOS Gates All the previous discussions were based on inverters. To evaluate the real performance improvement in systems using complex gates, a cell library is created for both the CSL and CS-CMOS families. Synthesizing CS-CMOS logic is very similar to the current practice used for CMOS logic except for the three additional transistors. As CS-CMOS has a lower swing the number of vertical stack of transistors in both pull-up and pull-down networks has to be restricted to two. The transmission gates are avoided. Apart from sizing the CMOS core

is also increased by having a larger to achieve different drive-capabilities. Choosing the value of requires the knowledge of the operating frequency and the output load (6). To handle the output load, CS-CMOS requires an appropriate . Restricting the number of fan-outs from a gate to 4 keeps the size of the gate manageable. The value of required is estimated using (3). The CS-CMOS cell library has the following building blocks: Inverters, 2- and 3-input NAND gates, 2-input NORs, 3- and 4-input AndOrInvert and OrAndInvert gates, XOR gates and ip-ops. In the cell library each type of gate is designed to have at least a fan-out of four. The true single-phase clock (TSPC) register [12] is transformed into its current-steering equivalent and is used as the CS-CMOS ip-op. The area overhead of a CS-CMOS is not very signicant for complex gates having a large number of fan-outs. An equivalent library of gates is created for the CSL family as well. The ratio of the device sizes (see Fig. 3) is chosen to be 4. As CSL is also a low swing family, transmission gates and stacking of devices are avoided. The absence of pull-up network in the CSL family makes multi-input NOR gates attractive. The CSL cell library has the following building blocks: 2-input NAND, NOR (2-, 3-, and 4-input), AndOrInvert (3 and 4-input), OrAndInvert (3- and 4-input), XOR and ip-ops. CSL ip-ops are built by cascading two RS latches [3]. Each of the gates is designed for at least a fan-out of 4. The equivalent gates in the 2 families are designed to have equal bias current . These gates are characterized using the tool Liberty NCX (Synopsys Inc.) and synthesized using Design-Compiler (Synopsys Inc.). Designs of ISCAS85 [13] benchmarks are compared. Both implementations consume similar amounts of power. All the outputs are equally loaded with a 10 fF load. The results are tabulated in Table III showing the reduction of delay for CS-CMOS in the fth column. E. Decimation Filter Digital lters, frequency dividers etc. are needed in sensitive analog circuits like delta-sigma data converters, frequency synthesizers etc. Their contribution to power-supply and substrate noise reduce dynamic range, SFDR etc when implemented using CMOS logic [4], [6], and [13]. A decimation lter used in a delta-sigma ADC is chosen to test the performance of both CS-CMOS and CSL families.

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Fig. 9. Decimation lter used for comparing CS-CMOS and CSL implementations. TABLE IV PROPAGATION DELAYS FOR THE FILTER AND FREQ. DIVIDER

Fig. 11. Measured propagation delay for various bias currents.

Fig. 10. CSL and CS-CMOS inverters implemented in 15stage ring oscillators.

The decimation lter computes the average of the input data and provides an output at a lower rate . In the implementation shown in Fig. 9 the output rate is reduced by by a factor of two in each stage. Each stage computes the average of the previous and current input [15]. Of the multiple stages, the rst two stages are implemented using the current steering logic to reduce their noise contribution. The input words are in 2 bits offset-binary, while the output after the second stage is 4 bits wide in 2s complement format at half the input rate. The decimation lter is implemented for both CSL and CS-CMOS families, similar to the ISCAS85 benchmarks, using commercial synthesis tools. For the same power consumed (290 W, 1 V supply), CS-CMOS provides ve times shorter delays as shown in Table IV. F. Frequency Divider Frequency dividers implemented using current steering logic can avoid unwanted spurs in the output of a frequency synis designed to compare the thesizer. A frequency divider performance of the families. Such a divider consists of three ip-ops. Comparisons are made based on similar power consumed by both of the implementations. The results are presented in Table IV. The delay in the table is the minimum clock period fed into the frequency divider. It can be seen that CS-CMOS can operate at ve times higher frequency for similar power consumption. III. EXPERIMENTAL RESULTS A test chip was fabricated in a commercial 0.18 m CMOS process. The test structures were CSL and CS-CMOS 15stage

Fig. 12. Comparison of energy delay products of CSL and CS-CMOS gates using measured results.

Fig. 13. Measured propagation delay for variations in supply voltage.

ring oscillators. The transistors widths used in the inverters are shown in Fig. 10. Each inverter is loaded with additional CMOS inverters to access the signals off-chip. The die photo showing the CS-CMOS ring oscillator is shown in Fig. 14. The measured results are shown in Figs. 1113. The supply voltage was set to 1 V. Both logic families are compared for the

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threshold by introducing positive feedback. This can be useful in compensating for the gain-loss when channel lengths less that 30 nm are employed. In addition, the circuit can provide an open-drain current-output with an additional transistor. ACKNOWLEDGMENT The authors would like to thank K. Leung and S. Hara of Silicon Labs for their help in fabricating the test chip. The authors would also like to thank Dr. V. Acharya and Dr. P. Balsara for their valuable comments and suggestions. REFERENCES same current consumed per gate. In Fig. 11, propagation delays are compared. CS-CMOS has a factor of 4 less delay especially at lower currents. The improvement is less at higher bias curis xed to 10 fF. The rents primarily because the capacitor measured delay was higher than those observed in simulation results presented in Fig. 4, due to the extra load capacitance of the . output drivers (see Fig. 14). Larger load requires a larger For a of 20 fF, the propagation delay of CS-CMOS would have been a factor 4 better than CSL at the higher bias currents (see Fig. 11). Calculating energy delay product based on the measured propagation delay (see Fig. 12) show that the CS-CMOS consumes much lower power than the CSL especially at lower bias would improve energy-delay product currents. Using larger as well. variation As CS-CMOS and CSL families utilize a xed in supply do not affect their performance as much as in CMOS implementations [3]. Fig. 13 shows the variation of the propagation delays with supply voltage. The supply current varies with channel length modulation of the current source device. As the propagation delay is linearly dependent on bias current for both the families, a small variation was observed in measurements as well. Using larger channel length devices for the current sources would reduce this variation but will need higher voltage headroom. The area-efcient CSL inverters along with the load occupy 1271 m of area while the CS-CMOS equivalent needs 2790 m . IV. CONCLUSION We present a new low-noise logic family called CS-CMOS for noise reduction in mixed-signal integrated-systems containing both DSP as well as sensitive analog circuits such as phase-lock loops and data converters in a single chip of silicon. The new family is obtained by a simple current-steering modication to the standard CMOS logic preserving most of the attractive features of CMOS. The well-known constant-current operation enables a substantial reduction of switching noise. Extensive simulations and measurements demonstrate the speed and power advantages of this family over previously proposed logic families namely CSL and CBL. Each gate uses three additional transistors and a capacitor. However, the circuit conguration improves switching speed around the logical
[1] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, Low power CMOS digital design, IEEE J. Solid-State Circuits, vol. 27, no. 4, pp. 473484, Apr. 1992. [2] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd ed. Upper Saddle River, NJ: Prentice-Hall, 2003. [3] H.-T. Ng and D. J. Allstot, CMOS current steering logic for low voltage mixed-signal circuits, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 5, no. 3, pp. 301308, Sep. 1997. [4] Substrate Noise Coupling in Mixed Signal ICs, S. Donnay and G. Gielen, Eds. Dordrecht: Kluwer, 2003. [5] K. Iniewski, Wireless Technologies: Circuits, Systems and Devices. Boca Raton, FL: CRC Press, 2008, ch. 20. [6] D. Leenaerts and P. de Vreede, Inuence of substrate noise on RF performance, in Proc. Eur. Solid-State Circuits Conf., Sep. 2000, pp. 300304. [7] A. Taparia and T. R. Viswanathan, Low-power short-channel singleended current-steered CMOS logic-gate for mixed-signal systems, in IEEE Int. Symp. Circuits Syst., Seattle, WA, 2008. [8] E. Albuquerque et al., A new low-noise logic family for mixed-signal integrated circuits, IEEE Trans. Circuits Syst. I Fundam. Theory Appl., vol. 46, no. 12, pp. 14981500, Dec. 1999. [9] M. Yamashina and H. Yamada, An MOS current mode logic (MCML) circuit for low-power sub-GHz processors, IEICE Trans. Electron., vol. E75-C, no. 10, pp. 11811187, Oct. 1992. [10] M. Alioto, L. Pancioni, S. Rocchi, and V. Vignoli, Power-delay-areanoise margin tradeoffs in positive-feedback MOS current-mode logic, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 9, pp. 19161928, Sep. 2007. [11] T. Karnik, Y. Ye, J. Tschanz, L. Wei, S. Burns, V. Govindarajulu, V. De, and S. Borkar, Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors, in Design Autom. Conf., 2002, pp. 486491. [12] J. Yuan and C. Svensson, High-speed CMOS circuit technique, IEEE J. Solid-State Circuits, vol. 24, no. 1, pp. 6270, Feb. 1989. [13] D Bryan, The ISCAS85 benchmark circuits and netlist format, North Carolina State University, Raleigh, NC, 1985. [14] S. Kiaei, D. J. Allstot, K. Hansen, and N. K. Verghese, Noise considerations for mixedsignal RF IC transceivers, ACM J. Wireless Networks, vol. 4, pp. 4153, Jan. 1998. [15] R. J. Baker, CMOS Mixed-Signal Circuit Design. New Delhi, India: Wiley, 2008.

Fig. 14. Die photograph of the 15stage CS-CMOS ring oscillator.

Ajay Taparia (S06M10) received the B.Tech. and M.Tech. degrees in electrical engineering from Indian Institute of Technology, Madras, India, in 2005; and the Ph.D. degree in electrical engineering from the University of Texas at Dallas; in 2010. He is a Member of Technical Staff at Maxim Integrated Products, Sunnyvale, CA. His research interests include low noise solutions for SoCs, low power analog design and switched capacitor circuits. Previously he has worked at Silicon Labs, Austin, TX and Texas Instruments, Inc., India.

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Bhaskar Banerjee (S01M06) received the B.Tech. degree in electronics and electrical communication engineering (with honors) from Indian Institute of Technology, Kharagpur, India, in 2001; and the M.S. and Ph.D. degrees in electrical and computer engineering from Georgia Institute of Technology, Atlanta, in 2003 and 2006, respectively. He is an Assistant Professor in the Department of Electrical Engineering at the University of Texas at Dallas, and is a member of the SRC Texas Analog Center of Excellence (TxACE). His research interests include radio frequency (RF), microwave and millimeter-wave circuits using CMOS for high-speed and low power wireless communications and biomedical application. Previously he has worked at IBM Thomas J. Watson Research Center, Yorktown Heights, NY, National Semiconductor Corporation, and Texas Instruments Asia Development Center, India.

T. R. Viswanathan (S62M64SM76F97 LF03) received the B.Sc. degree in physics from the University of Madras, India, in 1956, the D.I.I.Sc. degree in electrical communication engineering from the Indian Institute of Science in 1959, and the M.Sc. and Ph.D. degrees in electrical engineering from the University of Saskatchewan, Canada, in 1960 and 1964, respectively. He was a Professor of electrical engineering at the Indian Institute of Technology, Kanpur; India; the University of Michigan, Dearborn; Carnegie-Mellon University, Pittsburgh, PA; and the University of Waterloo, ON, Canada. From 1985 to 1995, he was Technical Manager at AT&T Bell Laboratories and during 1995 to 2001, Director of R&D at Texas Instruments, Inc., Dallas. He was Adjunct Professor at the University of Pennsylvania, Visiting Professor at the University of California at Davis and Research Professor at University of Texas at Dallas. Currently he is a Research Professor at the University of Texas at Austin. Dr. Viswanathan was a member of the Administrative Committee of the IEEE Solid-State Circuits Society, ISSCC Executive Committee, and the Board of Governors of the IEEE Circuits and Systems Society. He was an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. He was a recipient of the CAS Darlington Award and the Kilby Award.