Detailed Programme

16th International Symposium on VLSI Design and Test (VDAT 2012)

Bengal Engineering and Science University, Shibpur Campus July 1-4, 2012

Day-1 (1st July 2012)

8.30-9.30 9.30-11.00

Registration
Tutorial 1: (IT Seminar Hall) PDN analysis and Design Challenges in large SOCs in Advance Technology Node Speaker: Biswajit Patra, Qualcomm, Bangalore Chair: P.K. Basu, University of Calcutta, India Tutorial 2: (Gate Way) Techniques and Challenges for Security of Hardware Chips Speakers: Susmita Sur-Kolay and Debasri Saha, ISI Calcutta, India Chair: Partha Pratim Das, IIT Kharagpur, India Tutorial 3: (Civil Seminar Hall) VLSI: Idea to Silicon: Challenges in Analog/Mixed Signal Speakers: Pradip Mandal (IIT Kharagpur), Prajit Nandi (Sankalp), Mrinal Das (Sankalp) Chair: Chandan K. Sarkar, Jadavpur University, India

11.00-11.30 11.30-13.00 Tutorial 1 (contd.)

Tea Break
Tutorial 2 (contd.) Tutorial 3 (contd.)

13.00-14.00 14.00-15.30 Tutorial 4: (Civil Seminar Room) Ultra Low Voltage Design Speaker: Bharadwaj Amrutur, ECE Dept., IISc., Banaglore Chair: Susanta Sen, University of Calcutta, India

Lunch Break
Tutorial 5: (IT Seminar Room) Designing Secure SoCs Speakers: Arindam Saha and Srivaths Ravi, TI India, Bangalore, India Chair : Rajat S. Chakraborty, IIT Kharagpur, India Tutorial 6: (Gate Way) Advanced validation methodologies for a complex nanometer silicon processor to get to a first pass silicon success Speakers: Hare Krishna Verma and Mayank Singhal Intel India Chair: Debesh K. Das, Jadavpur University, India

15.30-16.00 16.00-17.30 Tutorial 4 (contd.)

Tea Break
Tutorial 5 (contd.) Tutorial 6 (contd.)

Day-2 (2nd July 2012)

8.30-9.00 9.00-10.00

Registration
VLSI Education Lect-1 Speaker: Vishwani D. Agrawal, James J. Danaher Professor of Electrical and Computer Engineering, Auburn University, USA Chair: Bhargab B. Bhattacharya, Indian Statistical Institute, Kolkata, India

10.00-11.00

VLSI Education Lect-2 Speaker: R. N. Biswas, Director, University Partnerships & Knowledge Enhancement Technology R & D (Formerly Director of CEERI Pilani) Chair: Susanta Sen, University of Calcutta, India

11.00-11.30 11.30-13.00

Tea Break
VLSI Education Lect-3 ASSISTECH: an Experiment in Engaging Undergraduates in Socially relevant Research Speaker: M. Balakrishnan, Indian Institute of Technology Delhi, India Chair: Partha Pratim Das, Indian Institute of Technology Kharagpur, India

13.00-14.00 14.00-15.30

Lunch Break PhD Forum Jury Members: a) Bhargab B. Bhattacharya, Indian Statistical Institute, Kolkata, India
b) Susmita Sur-Kolay, Indian Statistical Institute, Kolkata, India c) Vishwani D. Agrawal, Auburn University, USA

15.30-16.00 16.00-17.30

Tea Break PhD Forum Jury Members: a) Bhargab B. Bhattacharya, Indian Statistical Institute, Kolkata, India
b) Susmita Sur-Kolay, Indian Statistical Institute, Kolkata, India c) Vishwani D. Agrawal, Auburn University, USA

Day-3 (3rd July 2012)

8.00-9.00

Registration Inauguration
Keynote -1 Low Power Digital Video Compression: Trends and Challenges Speaker: Mahesh Mehendale, TI Fellow, Texas Instruments, India Chair: Susmita Sur-Kolay, Indian Statistical Institute, Kolkata, India Keynote 2 Testing and Design-for-Testability Solutions for 3D Integrated Circuits Speaker: Krishnendu Chakrabarty, Duke University, USA Chair: Vishwani D. Agrawal, Auburn University, USA

9.00-9.30

9.30-11.30

11.30-11.45

Tea Break
Session A1 (Gate Way) LOW POWER - I Chair: Anuradha Srinivasan, Intel India Biswajit Maity and Pradip Mandal: Design of push-pull dynamic leaker circuit for a low power embedded voltage regulator Priyanka Choudhury and Sambhu Nath Pradhan: Power Modeling of Power Gated FSM and its Low Power Realization by Simultaneous Partitioning and State Encoding using Genetic Algorithm. Anu Gupta and Subhrojyoti Sarkar: A High Frequency and Low Power Analog Multiplier in Current Domain (Short Paper) Session B1 (IT Seminar Hall) ANALOG VLSI DESIGN - I Chair: Susanta Sen, Calcutta University, India Rahul Shrestha and Roy Paily: Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding Nagendra Gunti, Brajesh Kumar Kaushik, Anand Bulusu and Manoj Kumar Majumder: Low Complexity Encoder for Crosstalk Reduction in RLC Modeled Interconnects (Short paper) Ashutosh Nandi, Sudeb Dasgupta and Ashok Saxena: Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET (Short Paper) Session C1 (Civil Seminar Hall) TEST and VERIFICATION - I Chair: Rolf Drechsler, DKFI Bremen and Univ of Bremen, Germany Sruthi P Radhakrishnan and Nirmala Devi M: A Modified Scheme for Simultaneous Reduction of Test Data Volume and Testing Power Surajit Kumar Roy, Dona Roy, Chandan Giri and Hafizur Rahaman: Post-bond Stack Testing for 3D Stacked IC Soumyadip Bandyopadhyay, Kunal Banerjee, Dipankar Sarkar and Chittaranjan Mandal: Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker

11.45-13.05

13.05-14.00 14.00-15.00

Lunch Break
Keynote -3 Convergence of Bio-Nano-Information Technologies in the More than Moore Era Speaker: V. Ramgopal Rao, Indian Institute of Technology Bombay, India Chair: Bhargab B. Bhattacharya, Indian Statistical Institute, Kolkata, India

15.00-15.30

Tea Break

15.30-16.50

Session A2 (Gate Way) DESIGN TECHNIQUES - I Chair: Krishnendu Chakrabarty, Duke University, USA Prabir Saha, Arindam Banerjee, Anup Dandapat and Partha Bhattacharyya: Design of High Speed Vedic Multiplier for Decimal Number System Mamata Dalui and Biplab K Sikdar: An Efficient Test Design for CMPs Cache Coherence Realizing MESI Protocol Debapriya Basu Roy and Debdeep Mukhopadhyay: An Efficient High Speed Implementation of Flexible Characteristic2 Multipliers on FPGAs

Session B2 (IT Seminar Hall) ALGORITHMS & APPLICATIONS I Chair: Pradip Mandal, IIT Kharagpur, India Subrata Das, Parthasarathi Dasgupta and Samar SenSarma: Arithmetic algorithms for ternary number system Dushyant Juneja, Sougata Kar, Procheta Chatterjee and Siddhartha Sen: SOI MEMS Based Over-sampling Accelerometer Design with 56 Output Goutam Rana, Samir Kumar Lahiri and Chirasree Roy Chaudhuri: Design Optimization of a wide band MEMS resonator for Efficient Energy Harvesting

Session C2 (Civil Seminar Hall) LOW POWER II Chair: Sudeb Das Gupta, IIT Roorkee, India Chandrabhan Kushwah and Santosh Vishhvakarma: Ultra-Low Power Sub-Threshold SRAM Cell Design to Improve Read Static Noise Margin Arun Dobriyal, Rahul G., Pallab Dasgupta and Chittaranjan Mandal: Workload Driven Power Domain Partitioning Rituparna Das Gupta, Dipankar Saha, Sayan Chatterjee, Chandan Kumar Sarkar and Jagannath Samanta: Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit.

16.50-18.00

Poster Presentation Session - A3

Chairs: Ansuman Banerjee, Indian Statistical Institute, Kolkata, India K. K. Mahapatra, National Institute of Technology, Rourkela, India Bibhash Sen, Manojit Dutta, Divyam Saran and Biplab K Sikdar: An Efficient Multiplexer in Quantum-dot Cellular Automata Suman Chatterjee, Vikram Singh Saun and Anand Arunachalam: Integrated Placement and Optimization flow for Structured and Regular logic Kalyani K and Rajaram S: A Novel Symbol Estimation Algorithm for LTE Standard Naushad Alam, Bulusu Anand and Sudeb Dasgupta: Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance Biswajit Patra, Santan Chattopadhyay and Amlan Chakrabarti: A Novel Approach To Optimize Supply Voltage Drops By Voltage-Drop Aware Placement in 45nm and Below Technology Node P Saravanan, P Chandrasekar, Livya Chandran, Nikilla Sriram and Dr.P. Kalpana: Design and Implementation of Efficient Vedic Multiplier using Reversible Logic Sauvagya Sahoo and Kamalakanta Mahapatra: Design of Combinational and Sequential Circuits Using Novel Feedthrough Logic Arpan Mondal, Santosh Ghosh, Abhijit Das and Dipanwita Roy Chowdhury: Efficient FPGA Implementation of Montgomery Multiplier using DSP Blocks Naveen Kaushik, Brajesh Kumar Kaushik, Davinder Kaur and Manoj Kumar Majumder: Independent Gate SRAM based on Asymmetric Gate to Source/Drain Overlap-Underlap device FinFET Sudip Ghosh, Somsubhra Talapatra, Debasish Mondal, Navonil Chatterjee, Hafizur Rahaman and Santi P. Maity: VLSI Architecture for Spatial Domain Spread Spectrum Image Watermarking using Gray-Scale Watermark Soumyajit Poddar, Prasun Ghosal, Priyajit Mukherjee, Suman Samui and Hafizur Rahaman: A Photonic Network on Chip with Adaptive CDMA links Partha Sarathi Gupta, Sayan Kanungo, Hafizur Rahaman and Partha Sarathi Dasgupta: Analysis and Study of an Ultra-Thin-Body-Silicon-On- Insulator-Tunnel FET Transistor Prasun Ghosal and Tuhin Subhra Das: A New Extended XY Routing Algorithm for On-chip Communication on Diametrical 2D Mesh NoC

19:00-22:30

Banquet Speech + Banquet Dinner Venue: The Park Kolkata, 17 Park Street, Kolkata 700016
Whats Cool for the future of Ultra-Low-Power Wireless Chipsets? Speaker: Venugopal Puvvada, Sr. Director, Qualcomm, India Chair: Jayanta Lahiri, ARM, India

Day-4 (4rd July 2012)

8.00-9.00 9.00-10.00

Registration
Keynote 4 Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology Speaker: Rolf Drechsler, DFKI Bremen and University of Bremen, Germany Chair: Debesh K. Das, Jadavpur University, India Session A4 (Gate Way) Session B4 (IT Seminar Hall) ALGORITHMS & APPLICATIONS II Chair: Parthasarathi Dasgupta, IIM Calcutta, India Ayantika Chatterjee and Indranil Sengupta: High-Speed Unified Elliptic Curve Cryptosystem on FPGAs using Binary Huff Curves Mahendra Sakare, Shalabh Gupta and Mohit Singh: A 4 20 Gb/s 29-1 PRBS Generator for Testing a HighSpeed DAC in 90nm CMOS Technology (short paper) Hafizur Rahaman, Jimson Mathew, A. M Jabir and Dhiraj. K Pradhan: VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2m) using Dual Bases. Santanu Halder, Debotosh Bhattacherjee, Mita Nasipuri and Dipak Kumar Basu: A Fast FPGA Based Architecture for Sobel Edge Detection (Short paper) EMERGING TECHNOLOGIES Chair: Chandan Kumar Sarkar, Jadavpur University, India Sudhindu Bikash Mandal, Amlan Chakrabarti and Susmita SurKolay: A Synthesis Method for Quaternary Quantum Logic Circuits Lafifa Jamal, Md. Masbaul Alam, M. A. Mottalib and Hafiz Md. Hasan Babu: On the Compact Designs of Low Power Reversible Decoders and Sequential Circuits Debaprasad Das and Hafizur Rahaman: Delay Uncertainty in Single- and Multi-wall Carbon Nanotube Interconnects

10.00-11.20

Session C4 (Civil Seminar Hall) NOC & PHYSICAL DESIGN Chair: Santanu Chattopadhyay, IIT Kharagpur, India Bapi Kar, Susmita Sur-Kolay, Sridhar H Rangarajan and Chittaranjan Mandal: A Faster Hierarchical Balanced bipartitioner for VLSI Floor-plans using Monotone Staircase Cuts Sanga Chaki and Chandan Giri: Test Data Compression for NoC based SoCs using Binary Arithmetic Operations (Short paper) Bibhas Ghoshal, Subhadip Kundu, Indranil Sengupta and Santanu Chattopadhyay: Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip (Short Paper)

11.20-11.50

Tea Break

11.50-13.10

Session A5 (Gate Way) ALGORITHMS & APPLICATIONS III Chair: Vineet Sahula, NIT Jaipur, India Sanjay Burman, Ayan Palchaudhuri, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay and Pranav Singh: Effect of Malicious Hardware Logic on Circuit Reliability Arun Kumarappan and Pv Ramakrishna: Speech Processor Design for Cochlear Implants Rekha Govindaraj and Santanu Chattopadhyay: An efficient technique for longest prefix matching in network routers

Session B5 (IT Seminar Hall) TEST and VERIFICATION II Chair: Chittaranjan Mandal, IIT Kharagpur, India Jayagowri R and Gurumurthy K. S: Implementation of Gating Technique with Modified Scan Flip-flop for Low Power Testing of VLSI Chips (Short Paper) Kiran Kumar Abburi, Siva Subrahmanya Evani, Sajeev Thomas and Anup Aprem: Reusable and Scalable Verification Environment for Memory Controllers. Invited Talk Overcoming Test Challenges Speakers: Nilabha Dev, Vivek Chickermane, Shaleen Babu, Cadence Design Systems

13.10-14.00 14.00-15.00 Power Problems in VLSI Circuit Testing

Lunch Break
Keynote-4

Speaker: Vishwani D. Agrawal, Auburn University, USA Chair: Susmita Sur-Kolay, Indian Statistical Institute, Kolkata, India 15.00-15.30 15.30-16.50 Session A6 (Gate Way) ANALOG VLSI DESIGN II Chair: Anindya S. Dhar, IIT Kharagpur, India Manas Kumar Hati and Tarun Kanti Bhattacharyya: A High Speed, Low Jitter and Fast Acquisition CMOS Phase Frequency Detector for Charge Pump PLL (Short Paper) Jaynarayan T Tudu, Deepak Malani and Virendra Singh: ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits Manodipan Sahoo and Bharadwaj Amrutur: Comparison of OpAmp-based and Comparator-based Switched Capacitor Filter

Tea Break
Session B6 (IT Seminar Hall) DESIGN TECHNIQUES - II Chair: Sridhar Rangarajan, IBM, India Atin Mukherjee and Anindya Sundar Dhar: Design of a Fault-tolerant Conditional Sum Adder (Short Paper) Mohammed Shayan, Virendra Singh, Adit Singh and Masahiro Fujita: SEU Tolerant Robust Latch Design Debaprasad Das, Avisek Sinha Roy and Hafizur Rahaman: Design of Content Addressable Memory Architecture using Carbon Nanotube Field Effect Transistors

17:00-17:30

Valedictory Function