Tunable high resistance voltage-controlled pseudo-resistor with wide input voltage swing capability

M.-T. Shiue, K.-W. Yao and C.-S.A. Gong

A tunable pseudo-resistor featuring a wide input voltage range and ultra-high resistance is proposed. It is composed of serial-connected PMOS devices operating in the subthreshold region. An auto-tuning circuit involved makes the pseudo-resistor robust against process variations and common-mode voltage shifting. Operation and theoretical analysis are detailed. Simulation results in a 0.18 mm technology demonstrate the advantages of the proposed pseudo-resistor.

Introduction: An active resistor implemented in CMOS technology often operates in the triode region to make its resistance value as low as possible for realising an ideal switch. Some systems for biomedical and audio analogue front-end applications, by contrast, require ultrahigh resistance to create low-frequency poles ltering out the out-ofband noise. Nevertheless, implementing such high resistance values is not cost-effective no matter whether in off-chip commercial components or on-chip customised devices. Passive devices are one solution for onchip implementation, but they are extremely area-consuming. Alternatively, series-connected long-length transistors can be used, but they still cause the implementation overhead to be considerably increased by some extent. A ne solution that implements ultra-high resistance in a diode-connected pseudo-resistor has recently been demonstrated [1]. Although this kind of implementation reaches desired resistance values, it is subject to common-mode voltage shifting and consequently causes the resistance to drop severely, owing to its asymmetrical V-R characteristics. Gate-voltage-controlled pseudo-resistors with symmetrical V-R characteristics, on the other hand, have been proposed to overcome the drawback, but the limited input voltage ranges conne their applications [2, 3]. In particular, for the design proposed in [3], the gate-controlled voltage generated by the source follower does not track the variation in the voltage span across the pseudo-resistor (also known as common-mode voltage shifting) monotonically, making it potentially poor in stabilising the cutoff frequencies of the abovementioned applications. In this Letter, a tunable pseudo-resistor, capable of providing ultra-high and steady resistance over an extended input voltage range, is presented. Analysis and circuit design: CMOS pseudo-resistors take advantage of the current properties of the devices operating at the subthreshold region to achieve high equivalent resistance. The current property is clearly described by the EKV model. The I-V characteristics of a subthreshold PMOS device is expressed as follows [4]: ISD = Is e(VBG VT 0 )/nUT (eVBS /UT eVBD /UT ) (1)

(ii) is the same as the Vaf one depicted in Fig. 1. Fig. 2b plots the simulated I-V curves of the two cases. Fig. 2 can be used to explain the operation of the proposed circuit under positive span voltage Vab. From the curves, it can be easily understood that the total resistance Rtot of the proposed resistor under Va . Vb approximates to RM3 + Rm4 , resulting in Vab Vfb. By symmetry, Rtot RMI + RM2 and Vab Vfa can be deduced when Vb . Va. By sizing the transistors M1 to M4 properly such that M1 M4 and M2 M3 , Rtot can be kept nearly constant in spite of the changes in the polarities of Va and Vb. Compared to the designs in [2] and [3], the most signicant feature of the proposed pseudo-resistor is the addition of M2 and M3. If M2 and M3 are removed from our design while M1 and M4 are symmetrically connected with Vf , the input stage, together with its V-R characteristics, seen by Va and Vb will be the left half part depicted in Fig. 3a. To compensate for the roll-off ill-effect, M2 and M3 , with the structure and V-R characteristics depicted in the right half part, are added, thereby stabilising the resistance of the pseudo-resistor to some extent in its input voltage range. We use the simulation curves in Fig. 3b, even clearer than those in Fig. 3a, to explain about the advantage. By symmetry, we can only take a look at the path of Vaf. For varying Vab , assuming that the design is biased at a xed DV of 0.1 V, the source-body PN junction of M1 turns on and conducts strong current when Vab , 20.6 V, resulting in considerably decreased resistance. Fortunately, the total resistance of M1 and M2 is kept nearly constant by M2 , which can be demonstrated from the increase in VSD2. Rtot can be expressed as follows:

Fig. 1 Circuit schematic of proposed pseudo-resistor

where Is 2nmCox (W/Leff ) UT 2 (n is the subthreshold slope, m is the mobility, Cox is the gate oxide capacitance per unit area, W is width of the transistor, and Leff is the effective length of the transistor), and VT0 is the threshold voltage of the transistor. Previous studies have shown that the resistance of a pseudo-resistor can be adjusted by biasing its gate terminal [2, 3]. Unfortunately, the channel current of a PMOS device with its body connected to drain does not depend on the source-gate and source-drain voltages any more when the source-drain voltage is higher than the source-body junction voltage, due to the leakage current, higher than the channel one, induced by the activated parasitic BJTs. The leakage current, increasing with the source-drain voltage, results in signicant decrease in the equivalent resistance of the pseudo-resistor. Fig. 1 shows the proposed pseudo-resistor, which consists of four series-connected PMOS devices M1 to M4 and an auto-tuning circuit. The auto-tuning circuit, composed of an operational amplier, passive capacitors, and active resistors Ma1 to Ma8 , keeps constant Vgf whose value is obtained by subtracting the oating voltage (Vf ) from the gate voltage (Vg). As a result, the auto-tuning mechanism eliminates interference caused by the common-mode voltage shifting, obtaining symmetrical V-R characteristics. The half circuits shown in Fig. 2a describe how the resistance of the four series-connected transistors M1 to M4 are determined. DV represents Vfg of Fig. 1. The path in which current ows from Vf to Vb can be equivalent to that shown in case (i) except M3 and M4 should be, respectively, renamed as M2 and M1. The Vcd path of case

Fig. 2 Half circuits of proposed resistor, and I-V characteristics of half circuits
a Half circuits of proposed resistor b I-V characteristics of half circuits

Rtot = =

4 n=1

1 GSDn

ISD (n 1)eVSD1 /UT + 1 Nr + V /U eVSD1 /UT 1 UT e SD2 T 1 Nr 1 (1 n)eVSD4 /UT + VSD3 /UT 1e 1 eVSD4 /UT (2)

where Nr (W/L)2,3/(W/L)1,4. VCtrl is intended to determine resistance according to application. It can be provided by means of a DAC, affording a user fully programmable facility. Results: A 0.18 mm standard CMOS process was used to verify the design where (W/L)1,4 (1/0.18) mm, (W/L)2,3 (10/0.18) mm, (W/L)a1 8 (0.5/5) mm, and C 182 fF. A0 is a differential amplier with a 10.7 nA tail current achieving a unit gain bandwidth of

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1.27 MHz. Comparison of the pseudo-resistor is shown in Fig. 4, demonstrating tuning capabilities from several megaohms to hundreds of gigaohms by xing Vb at 0 V, sweeping Va from 20.9 to 0.9 V, and adjusting VCtrl. Note that the transistor sizes of the designs in [2] and [3] are identical with W/L1,4 in order to make fair comparison. From Fig. 4, our design also shows a wider input voltage range than those of the counterparts in [2] and [3]. Power consumption of the proposed design operating at an 1.8 V supply voltage is only 19.28 nW.

Conclusion: A novel pseudo-resistor achieving symmetrical V-R characteristics and truly constant resistance over an extended input voltage range is presented. The design philosophy is detailed and the results are given as proof of concept. It is well suited for applications requiring extremely low cutoff frequency. # The Institution of Engineering and Technology 2011 17 November 2010 doi: 10.1049/el.2010.3286 One or more of the Figures in this Letter are available in colour online. M.-T. Shiue and K.-W. Yao (Department of Electrical Engineering, National Central University, No. 300, Jhongda Road, Jhongli City, Taoyuan County 32001, Taiwan) E-mail: kwyao@ee.ncu.edu.tw C.-S.A. Gong (Industrial Technology Research Institute, Taiwan) References
1 Harrison, R.R., and Charles, C.: A low-power low-noise CMOS amplier for neural recording applications, IEEE J. Solid-State Circuits, 2003, 38, pp. 958 965 2 Zou, X., Xu, X., Yao, L., and Lian, Y.: A 1-V 450-nW fully integrated programmable biomedical sensor interface chip, IEEE J. Solid-State Circuits, 2009, 44, pp. 10671077 3 Tajalli, A., Leblebici, Y., and Brauer, E.J.: Implementing ultra-highvalue oating tunable CMOS resistors, Electron. Lett., 2008, 44, (5), pp. 349 350 4 Enz, C., and Vittoz, E.: Charge-based MOS transistor modeling: the EKV model for low-power and RF IC design (Wiley, New York, USA, 2006)

Fig. 3 Illustration of mechanism on how Rtot can be kept nearly constant, and VSD against Vab
a Mechanism of how Rtot can be kept nearly constant b VSD against Vab

Fig. 4 Rtot against Vab

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