Application Note

Design Considerations for the ZiLOG Universal Infrared Remote

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ZiLOG Worldwide Headquarters 532 Race Street San Jose, CA 95126-3432 Telephone: 408.558.8500 Fax: 408.558.8300 www.zilog.com

Application Note Design Considerations for the ZiLOG Universal Infrared Remote

This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters
532 Race Street San Jose, CA 95126-3432 Telephone: 408.558.8500 Fax: 408.558.8300 www.zilog.com

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Information Integrity
The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Any applicable source code illustrated in the document was either written by an authorized ZiLOG employee or licensed consultant. Permission to use these codes in any form, besides the intended application, must be approved through a license agreement between both parties. ZiLOG will not be responsible for any code(s) used beyond the intended application. Contact the local ZiLOG Sales Office to obtain necessary license agreements.

Document Disclaimer
2003 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights.

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Table of Contents
Hardware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Battery Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Low-Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 VBO/VRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 UIR Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Key Matrix Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Internal Pull-Up Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Output Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Oscillation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Software Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 T8 and T16 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Port 0/1 Open Drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Warm/Cold Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Limitations from Design and Prototype to Production . . . . . . . . . . . . . . . . . . . . 13 Design to the Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Port 3 Pull-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Undefined Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Appendix A Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Appendix B Key Scanning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Appendix C Low-Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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List of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Low-Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vcc Versus Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal IR Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Push-Pull Output for Key Scanning . . . . . . . . . . . . . . . . . . . . . . . . . . Open-Drain Output for Key Scanning . . . . . . . . . . . . . . . . . . . . . . . . . Scan Pulse Using Open-Drain Output and Pull-Up Input . . . . . . . . . 4 5 6 7 8 9

List of Tables
Table 1. ZiLOG Infrared Controller Packages . . . . . . . . . . . . . . . . . . . . . . . . . 1

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Design Considerations for the ZiLOG Universal Infrared Remote

The Z86L7X/8X/9X family is a ZiLOG low-cost high-performance lnfrared Remote Controller (IRC). Table 1 shows the different ROM sizes and packages for various applications. It also has many special features such as:

Low-voltage operation (2.0 to 3.6 V at 8 MHz) Two enhanced counter/timers 8-bit counter/timer for infrared (IR) carrier generation 16-bit counter/timer for data modulation

Watch-dog timer (WDT) Automatic power-on reset (POR) Two analog comparators with output option Five priority interrupts Three external Two assigned to counter/timers

Direct drive for visible LED and high drive for IR LEDs Stop mode for longer battery life ROM sizes from 4K to 64K 16 I/O lines (20-pin family for small IR remotes) 23 I/O lines (28-pin family for standard IR remotes) 31 I/O lines (40-pin family for IR keyboards)

Table 1. ZiLOG Infrared Controller ROM Size/Package 4K 8K 16K 24K 20 Pin Z86L825 Z86L826 Z86L827 28 Pin Z86L82 Z86L85 Z86L88 Z86L81 40 Pin Z86L972 Z86L973 Z86L87/ Z86L974 Z86L89

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Table 1. ZiLOG Infrared Controller (Continued) ROM Size/Package 32K 64K 20 Pin 28 Pin Z86L86 Z86L98 40 Pin Z86L73 Z86L987

The ZiLOG IRC has a typical STOP mode current consumption of less than 2 mA. The powerful T8 and T16 timers provide a best tool to generate accurate IR signal with modulated signal with carrier frequency. As a leading universal IR (UIR) controller manufacturer, ZiLOG also provides one of the best turnkey solutions for universal IR development. ZiLOGs IR database is updated quarterly and has been proven in field tests. Moreover, ZiLOG provides a complete Z8 reference design to speed the development of new IR remote designs. Customers do not need to build their own IR library. Our UIR reference design provides everything required for project development. This application note is for those engineers who would like to develop a new IR remote based on the ZiLOG IR controller and IR database. The application note goes through the hardware and firmware design and explains how to get the best performance from the ZiLOG IRC.

Hardware Design
The ZiLOG IRC Z86L7X/8X/9X offers different packages and ROM sizes for low power MCU design. Each has the unique one 8-bit timer and one 16-bit timer. They make up a perfect companion for the IR signal with carrier and modulated signal. Such hardware timers can produce accurate IR signals with resolutions of hundreds of nanoseconds without consuming the MCU bandwidth.

Timers
The T8 and T16 timers are customized for transmitting Infrared signals. T8 can generate carrier frequency with resolution up to Crystal Oscillation/2 (that is, 250 nS width for 8 MHz oscillation). T16 can generate the mark space length up to 128 mS for 8 MHz oscillation. T8 and T16 can also be cascaded in Ping-Pong mode to generate very short base band (flash) signal. The output of T8 and T16 can be logically AND, OR, NAND, NOR. It provides a flexible implementation on the IR signal output at P36. The T8, T16 timers can be output separately at P34, P35 respectively. If user only needs the Mark Space signal for RF transmission, the P35 (T16 output) signal can be used directly. Carrier can also be obtained separately from P34.

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T8 and T16 can also be used as general-purpose timers. The bit 5 of CTR0 tells the timeout of the T8 and bit 5 of CTR2 tells the timeout of T16. If the timer is enabled, an IRQ can also be generated.

Battery Operation
In battery-operated devices such as remote control, the battery consumption is a major concern. ZiLOG IRC offers very low power consumption in STOP mode (typically is 2 mA). Remote control is left idle most of the time until user presses a key. The microcontroller (MCU) will wake up from STOP mode and execute firmware to check the key and send IR signal. After everything is done, it will go back to STOP mode to preserve power. ZiLOG IRC provides more than 16 combinations of Stop Mode Recovery (SMR) sources through the SMR and SMR2 registers. We shall go through the detail of the SMR sources selection in the key matrix design. ZiLOG IRC also offers HALT mode in which no instruction is being executed. Only timer is counting in such mode. Interrupt can wait up the MCU from HALT mode. HALT mode is often used in counting time for key de-bouncing, LED display, and timer. Both STOP and HALT instruction are only used after NOP instruction. Z8 uses pipeline architecture. NOP is required to clear the pipeline instruction before it goes to STOP or HALT. Besides the STOP and HALT mode power saving operation, ZiLOG IRC can work down to 2V, which extend the battery life greatly. The normal 2 cells (AA or AAA size) battery voltage is 3 V. It takes year for it to go down to 2 V. In order to preserve the power during STOP mode, Watchdog, Comparators, LowVoltage Detection, and ADC (if applicable) need to be disabled. The IC might draw more current if any of the above peripherals is enabled during STOP/HALT mode.

Low-Voltage Detection
Low-voltage detection is to detect the battery voltage and give an early warning before the battery goes down to below the reset voltage. ZiLOG IRC can either flash LED or send out an IR signal to set top box for low battery voltage warning. Z86L825/Z86L826/Z86L827/Z86L82/Z86L85/Z86L88 do not have internal lowvoltage detection. LVD can be done easily with the built-in comparator. 2 resistors are used to produce the proportion voltage to Vcc. 1 resistor and 1 diode are used for a 0.7V reference voltage. The LVD starts with P34 output a Low signal to activate the potential divider and the 0.7 V reference voltage. After small delay, the P31 (after the comparator) is checked. If P31 = 0, then Vcc is normal, else Vcc is too low. By calculating the resistor value, we can easily set the low-voltage threshold. Please see Appendix C Low-Voltage Detection on page 21 for the detailed firmware implementation. The 10K and 24K resistors will provide a ratio of 10 / (10 + 24) = 0.29. If V diode = 0.7 V (fully ON), it will give the low-voltage detection at

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2.38 V. Users can change the potential divider in order to set a different detection level.

Figure 1. Low-Voltage Detection

ALL IR MCUs with ROM/OTP size 24K/32K/64K have a built-in low-voltage detection circuit. When Vcc goes close to the reset voltage (or Vbo) and the LVD is enabled (Expanded Register Bank %0D, register %0C Bit 0 = 1), the low-voltage detection flag (Expanded Register Bank %0D, register %0C Bit 1) will be set. IRQ5 will be set when LVD is enabled. If the interrupt is enabled, the IRQ5 interrupt service subroutine will be served. The LVD flag will be valid after enabling the detection for 20 mS (design estimation, not tested in production). LVD does not work at STOP mode. It must be disabled during STOP mode in order to reduce current.

VBO/VRAM
When the battery is replaced, we want to keep the RAM data inside so that the user does not need to program the remote control again after replacement. In order to do it, we need to understand how the MCU behaviors at this low-voltage area. Proper hardware and firmware design are needed. Usually, a 100 mF capacitor is used for holding up the RAM data. Vbo is the reset voltage. When Vcc goes below Vbo, the ZiLOG IRC will reset itself. Bit 7 of SMR register will be cleared to indicate a Power On Reset when the power resumes. Vbo is typically about 1.6. Vram is the voltage to hold the validity of the RAM content. It depends on the fabrication process and is below 1 V. As Vcc goes down, the MCU goes into

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Low-Voltage Standby mode (a kind of RESET stage) when Vcc < Vlv (Vbo). At that time, P0, P1, P2 are put into input mode. P34-P37 will become output LOW. Make sure none of the external peripheral will draw current from this stage. The MCU consumes very little current at the reset stage. The RAM data will be retained when Vcc is above the Vram. In some applications, RAM data are valid after hours. That is much more time for end user to replace the battery without losing the programmed data. With proper firmware implementation, we can retain the RAM content for very long time.

Vcc Vcc falls after battery is removed 3V

Vlv

Vram Time
Figure 2. Vcc Versus Time

Figure 2 shows laboratory measurements (in year 2002) on the Z86L88 samples and is for reference only. (Parameters might change in different revisions, but ZiLOG tests the MCU according to Customer Procurement Specification.) Z86L88 might lose its RAM content when Vcc < 0.5 V. When battery is removed, the Vcc will drop below the Vlv (typical about 1.6 V) very quickly. Then the chip goes into Low-Voltage Standby mode. The Vcc continues to drop till around 0.7 V. Then the decline rate is much slower. At that time, there is only small leakage current at the chip which is in the nA range. It should take more than 10 minutes before the Vcc drops below 0.5 V. The user will have enough time to replace the battery without losing the programmed data.

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UIR Circuit
The circuit of most universal IR remote control application is very simple. It basically involves a key scanning for the key input and Infrared signal transmission. Some customers would like to have LED display, back light LED, jumper setting for different model at the same ROM, EEPROM storage, low battery detection, and so on. Z86L7X/8X can implement everything easily.

Figure 3. Universal IR Design

Key Matrix Design

For key scanning, we need an open-drain configuration at the output. Figure shows why open drain is required. In a push-pull configuration, the output of Port 01 has FET A and FET B. If 1 is output at P01, FET A will be ON, and FET B will be OFF. To do the key scanning, we need to output 1 and 0 at different port. For example, if P01 = 1 and P00 =0, if the user presses K1 and K2 simultaneously, there will be a short circuit from Vcc to Ground though FET A and FET D. The input /output pins will have a Electrical Over Stress (EOS) and might be burnt. Therefore, we must use the open drain configuration as shown at Figure .

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Figure 4. Push-Pull Output for Key Scanning

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P01 P01

P20 K1

P21 K3

FET B

P00

P00

K2

K4

FET D

Figure 5. Open-Drain Output for Key Scanning

Port 0 is therefore necessary be open-drain output. The open-drain output of P01 is floating as the FET B is turned OFF, the logic will depend on what is connected to the line. Thus the input port must have a pull up connected. The Z86L7X/8X do offer mask option built-in pull up at Ports 0, 1, 2, and 3. That will save the system and labor cost. Precaution: The ports 0, 1, and 2 are all connected to an CMOS input buffer no matter whether it is configured as input or output. If it is configured as open drain output, outputting a HIGH will put the pin into floating CMOS input. That might cause extra high leakage current of more than 100 mA. In the hardware design, we also need to concern about the STOP Mode Recovery. Port 2 provides 8 input for SMR. Thus we can have 8 open drain outputs from Port 0 and 8 SMR enable input at port 2. We have then totally 64 keys, which is always enough for UIR application. In case that the designer needs more pin, we can also use one of the P31, 32, and 33 as additional SMR input pin. It adds up 8 x 9 = 72 keys. We can also use the ground pin as the 9th output pin. However, not another key row is allowed if the ground row is already pressed. So we can support totally 9x9=81 keys in 28 pin package. For 40-pin package, we can use both Port 0 and 1 as output with port 2 as input. It already adds to 128 keys. Again, if

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Port 3 and the ground pin are used, the total max key will be 17x9=153 keys. That satisfies all common applications including wireless keyboard.

Internal Pull-Up Variation

In Z86L7X/8X/9X, the pull up at the input port is not a pure resistor. It is a transistor-based pull-up. Therefore, the equivalent resistance depends on the Vcc and temperature. At room temperature and Vcc=3 V, it has about 270 kOhm. The equivalent resistance increases as the Vcc decreases. It can be up to 670 kOhm when Vcc drops to 2.0 V. The stray capacitance of the port depends on the PCB design. In some customer boards, it might have 50 pF. The RC time constant will become 670 kOhm x 50 pF = 34 microsecond. It is therefore recommended to put at least 100 mS delay in the key scan routine. Without the delay, the MCU might read the previous key on a different scan row as the row signal does not have enough time to rise to High yet.
P20

Rise Time depends on the RC for open-drain. There is enough delay for the port to settle. P21

Figure 6. Scan Pulse Using Open-Drain Output and Pull-Up Input

Another key scanning algorithm is to pre-charge the input port every time before the key scanning start. With the pre-charge, the input pin does not depend on the previous logic state. It also does not rely on the weak pull up resistance. When port 2 is configured as output with push pull, it can drive the port to high in less than a microsecond. This will make sure that all the input ports are High at the beginning. To precharge the Port 2 input, we first output Port 0 with %FF. It will make sure no short circuit for High and Low from Port 0 and 2. Then port 2 is configured as output with

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push pull and outputs the %FF to the port. Then port 2 is configured back to input port to read the key scanning. Port 2 is pre-charged before each row of scanning. Appendix B Key Scanning on page 18 tells the detail of the key scanning.

Output Drive
P37, P36, P00, and P01 are equipped with high current driving capability. It can sink in 10 mA with typical Output Low Voltage (Vol) 0.2 V. It can even drive more current if Vol is allowed to go up more. These pins are ideal to drive LED in series with a resistor.

Watchdog
The watchdog is used to monitor the firmware and make sure that the firmware is on the right program flow. In the program flow, watchdog is refreshed frequently and the watchdog timer will never expire. But if the MCU leaves the program flow and hangs somewhere, the watchdog timer will timeout and generate a RESET on the MCU. Once the watchdog is enabled, it cant be disabled. If watchdog is enabled in the ICEBOX, the only way to disable it is to power cycle on the ICEBOX. The watchdog can be programmed to be ON or OFF during HALT and STOP mode by the WDTMR register. The MCU consumes more current when watchdog is ON. HALT mode is often used when sending infrared signal which has long idle delay time. If the watchdog is enabled during the HALT mode, the user needs to make sure that ALL infrared signals are shorter than the watchdog timeout period. As a new infrared signal might require a longer idle time, it is advised to disable the watchdog in HALT mode for infrared remote application. The watchdog is normally running at internal RC oscillation. The RC varies with temperature and voltage. Therefore, user needs to make sure that the watchdog is refreshed before the minimum watchdog timeout period. Please also pay extra attention that the watchdog timeout periods are different in ROM and OTP. Please refer to both specification for comparison.

Oscillation
ZiLOG IR MCU supports crystal, resonator and oscillator. Bit 5 of SMR register allows user to select the STOP mode recovery delay. If it is not selected, the MCU will execute instruction immediately after it comes back from RESET (Power of RESET or STOP mode recovery). A stable free running oscillator is required in this mode. If the oscillation is not stable, the MCU might be hanged up when it runs into racing condition with high clock frequency.

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STOP mode recovery delay needs to be selected (bit 5 of SMR = 1) if resonator or crystal is used as clock source. The delay is generated from internal RC circuit and is around 5 mS. It varies with voltage and temperature.

PCB Layout
Remote control generates infrared signal by driving a high current through the infrared diode. That high current path can generate high EMI or noise to the MCU. It is recommended that the layout separate the high current path (from battery, to infrared diode and to ground) from the MCU power path and oscillation circuit. The typical 100-mF capacitor must also be physically close to the infrared diode to further minimize the noise.

Software Design
Power Up
The ZiLOG 28-pin package IC does not have an external /RESET pin. All pins are dedicated for input/output (I/O) except the power Vcc, Ground, and the Crystal In/ Out Oscillation. It provides maximum I/O pin for user to control different interface. Z8 does have a built-in Power-On Reset (POR) circuit that will reset the chip properly after power up. When the Vcc goes beyond the Vbo (brown-out voltage), the chip will come out from reset. After the POR delay (about 5 mS), Z8 will execute the first instruction at location %0C. The POR delay is for the Vcc and the oscillation to get stable before executing the Z8 instruction.

Initialization
After the power up, the Z8 needs to initialize itself. There is a proper initialization procedure that should be followed. In POR, some control registers have undefined value inside. It might be different for different fabrication process or die revision. Therefore, we must initialize all control registers and also general-purpose registers. Appendix A Power-Up Initialization on page 15 is an example of a proper initialization routine. This is discussed below.

Disable Interrupt
Set the DI to disable all interrupt upon POR. It prevents any interrupt coming during initialization. As we have not initialized the stack pointer, any interrupt or subroutine call might result in a random return address or RAM corruption. DI must be the first instruction to execute.

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Output Port
If an I/O is initialized as an output port, for example, Port 2, first load the output data to the port and also configure it as push pull before it is configured as output. If we configure it as output without knowing what is inside the output buffer, there might be a Low signal before it outputs High. Such a glitch is not desired. As a principle of I/O configuration, we always put the data at the port before configuring as output.

Stack Pointer
The stack pointer and the interrupt control registers are then initialized. Only T16 interrupt is enabled as we need it to wait up the Z8 from the power saving HALT mode while in delay loop or transmitting IR signal. Users can have different selections if they use different interrupts.

T8 and T16 Timers

T8 and T16 timers are used in transmitting mode most of the time. We also disable them at the power up. T8 is used for generating the carrier frequency with resolution from sclk to sclk/8. T16 is used to generate the Mark/Space signal. Their outputs are logically AND together to produced the modulated signal. The first output clock of T8 might not be in a full length carrier as T8 is a free running timer that might not synchronize with T16. However, the following clocks will be exactly as it is programmed. It wont affect the validity of the signal in the IR transmission.

Port 0/1 Open Drain

The PCON register provides an option of configuring port 0 and port 1 open drain. In key scanning, open drain output is necessary to prevent short circuit for multiple key press. All IR MCUs have an open-drain option at port 0 and 1 (port 1 is only available for 40 pin or above package). Port 1 output will be open drain if D1=0. Port 0 output will be open drain if D2=0.

Warm/Cold Start
We have already discussed the difference between Vbo and Vram in the hardware design section. RAM validity check is preferred then Vbo reset check (by bit 7 or SMR). If the RAM data is valid, we will take it as a warm start. If the RAM content doesnt match, it will be a cold start. Warm start means that the MCU does have a continuous power supply and the RESET is not from the change of Vcc. It can be from watchdog or STOP mode recovery. As watchdog is not used in most IR application, warm start must be from

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the SMR. Our concern is more on the validity of the RAM content rather than the source of reset. Before the MCU goes to STOP mode, we first load a special value %5A at address %10. Then store the complement of the whole useful bank %10 (%10 to %1F) at bank %D0 (%D0 to %DF). Upon reset, we check the whether %5A is in address %10 and whether bank %D0 is the complement of bank %10. By doing that, we can be very sure on the validity of the RAM content. Usually, the device number (for example, TV, VCR, Audio, Receiver, LD, CD, SAT, or Cable), code number (for different models), and useful status can be stored in the bank %10.

Limitations from Design and Prototype to Production

The Z86L9800ZEM fully emulates all firmware in the IR family. However, there are some hardware limitations and variations in parameter to the ROM part. The ICEBOX operates at a stable high voltage of 3-4 V (other components for debugging and PC communication needs high voltage). It cant go down to 2 V as like as the ROM part. As a result, some functions or parameters cant be emulated on the ICEBOX:

Low-Voltage Detection Watchdog timer (WDT timeout period increase with decrease in voltage) Internal pull up resistance (pull-up resistance increases with decrease in voltage) Power On Reset Delay

After emulating with the ICEBOX, users can further proves the design with OneTime Programmable (OTP) MCU. OTP has a wider voltage range. Z86D86/D73 operates in 2.3 V to 3.6 V. The typical Vbo (by laboratory measurement only, not tested) is about 2.1 V at room temperature which is higher than the ROM. As a result, it will have variation to the ROM at very low voltage (below 2 V).

Design to the Specification

Both ROM and OTP are tested according to their specification. Designing with the specification is safe guarded. Designing from the OTP experiment might sometimes have issues. For example, the minimum WDT timeout is specified at 20 mS. Certain OTP sample might be 50 mS while a certain ROM part has only 40 mS. If the WDT is only refreshed at 45 mS, the OTP will have no problem, but the ROM part will generate a RESET to the MCU.

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Port 3 Pull-Up
The ROM part offers mask option on the port 3 internal pull-up while OTP does not. The user needs to add external pull-up resistors in the OTP prototype.

Undefined Registers
Upon power up, if a register bit is undefined, the state might vary from production lot to production lot, and with different time of power up. The content is just not defined. It is recommended that user program all used control registers and general purpose registers to make sure that the firmware will run consistently.

Conclusion
ZiLOG provides an ICEBOX for emulation and OTP for verification and prototype before the mask ROM MCU. However, there are differences among them. In ICEBOX, all control register and general purpose registers are initialized by the ICE chip firmware. It will provide the same value every time it powers up. OTP is closer to the mask ROM. However, there might be still different power up value in those undefined registers and the general purpose registers. Same as different die revisions of the same IC. Therefore a proper initialization is a must to eliminate the difference. We check the RAM content instead of the RESET signal of SMR bit 7. The RAM content is much more important then whether the MCU was reset. If there is Electrostatic Discharge (ESD) or Electromagnetic Interference (EMI), the Vcc might be interfered and drops below the reset voltage. The MCU can be reset but it will still work properly whenever the RAM content is still valid. The programmed data is still inside. Using this method, the universal remote control design will have a much better performance for ESD or EMI. The interference will not become noticeable. The ZiLOG Z86L7x/8x/9x and Z86D73/D86 provide an internal pull-up transistor. It reduces the system and labor cost of having external pull-up resistor. In Z86L9800ZEM (ICEBOX), it provides a jumper option of 680 kOhm pull-up resistor at those pin. However, in the real world, the equivalent resistance of the pull-up transistor depends on the Vcc and the temperature. It might also shift in different fabrication process or die revision. A good key scanning subroutine is needed to eliminate this difference. With the pre-charge of the input port method, the key scan will not depend on the resistance. It will further enhance the firmware. With these careful design rules, design with ZiLOG MCU will become more easy and robust. Note: All Z86L7X/8X/9X parameters are typical values. Please refer to the product specification for details. Parameters might vary with different temperature or Vcc.

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Appendix A Power-Up Initialization

;*********************************************************** ;* Copyright 2003 ZiLOG Inc. ;* ;* Infrared Universal Remote Control ;* ;* ZiLOG Inc. ;* 532 Race Street ;* San Jose, CA 95126-3432 ;* USA ;* Tel: 408-558-8500 ;* Fax: 408-558-8300 ;* ;*Assembler & Linker : ZDS ;*Topic : Main loop ;*MCU : Z86L7X/8X/9X, Z86D73/D86 vector request = RESET vector irq0=IRQ_0 vector irq1=IRQ_1 vector irq2=IRQ_2 vector irq3=IRQ_3 vector irq4=IRQ_4 vector irq5=IRQ_5 _SPL .EQU r15 _SPH .EQU r14 _IMR .EQU r11 _IRQ .EQU r10 _IPR .EQU r9 _P01M .EQU r8 _P3M .EQU r7 _P2M .EQU r6 _smr .EQU r13 _sir .EQU r11 _pcon .EQU r0 ctr2 .EQU r2 ctr1 .EQU r1 ctr0 .EQU r0 RESET:
DI ;------; ; ld ld ;Prevent interrupt in initialization Initialize ports port is loaded with known value before it is configured as output. p0,#%FF ;p0 output FFh p1,#%FF ;p1 not used and output High

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ld srp ld LD LD

;required for 40-pin package Z8 p2,@%FF #%F0 ;Point to control registers. _P01M,#00000100b ;p0,p1 are all output _P3M,#00000001b ;p2 push pull, p3 as in/out port _P2M.#00000000b ;initialize p2 as output to precharge P2.

; ;------- Initialize the stack CLR _SPH ;Clear stack High

;unless in ROMless mode, SPH can be used as general-purpose register

LD _SPL,#%F0 ;Reset stack LOW ;------- Initialize interrupt CLR _IRQ ;clear any leftover interrupts LD IMR,#00001000b ;allow T16 interrupt IRQ3 LD _IPR,00101011b ;T16 IRQ3 has the highest priority ;------- Initialize timer/counter LD RP,#%0D ;Reg groupD, for timer/counters LD ctr0,#00100000b ;T8 disabled, modulo N, Reset Flag LD ctr2,#00100000b ;T16 disabled, modulo N, Reset Flag LD ctr1,#01000011b ;Transmit mode
;------- Initialize Stop-Mode Recovery source LD RP,#%0F ;Reg group F, for Stop-Mode Recovery LD _smr,#00100000b ;POR delay ON LD _smr2,#01001000b ;recover on NAND P20.P27, level low LD r0,#1111101b ;set p0 open drain in PCON

;----------------------------------------------------------;------ Test for warm/cold reset ;----------------------------------------------------------; RAM data will be maintained as VCC > 1 V typically srp #%E0 cp %10,#%5A jr nz, Not_Warm ld r0,#%#%10 ;address of the RAM data to be tested ld r1,#%D0 ;address of the complement of RAM data ;to be tested ld r2,#%16 ;16 bytes of RAM for test RAM_check_loop: ld r3,@r0 com r3 cp r3,@r1 jr nz,Not_Warm inc r0 inc r1 djnz r2,RAM_check_loop ;----------------------------------------------------------------Warm_start: CALLEXECUTING_PROGRAM GOTO_STOP:

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ld p2m,#%FF ;set p2 input ld p0,#0 ;set p0 output 0 ld %10,#%5A ;#5A is a signature test for RAM sr #%E0 ld r0,#%10 ;RAM data to be tested ld r1,#%D0 ;complement of RAM data to be tested ld r2,#16;16 bytes of RAM for test RAM_write_loop: ld r3,#r0 com r3 ld @r1,r3 inc r1 djnz r2,RAM_Write_loop NOP STOP ;wait for another key press ;----------------------------------------------------------------Not_Warm: ;Clear all RAM data after POR srp #%00 ld r5,#%EF init_RAM clr @r5 dec r5 cp r5,#5 jr ugt,init_RAM CALL INITIALIZE_OTHER JR GOTO_STOP ;----------------------------------------------------------------EXECUTING_PROGRAM: ; The normal routine will be key scanning and decoding. ; The UIR needs to send IR signal if it is a valid key call Key_Scan call Low_Voltage_Detection RET INITIALIZE_OTHER: ; Other general-purpose registers initial data needs to be ; initialized also. RET ;----------------------------------------------------------------IRQ_0: IRQ_1: IRQ_2: IRQ_3: IRQ_4: IRQ_5: CLR IRQ ;clear the interrupt RET ;just return

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Appendix B Key Scanning

;----------------------------------------------------------;* Copyright 2003 ZiLOG Inc. ;* ;* Infrared Universal Remote Control ;* ;* ZiLOG Inc. ;* 532 Race Street ;* San Jose, CA 95126-3432 ;* USA ;* Tel: 408-558-8500 ;* Fax: 408-558-8300 ;* ;*Assembler & Linker : ZDS ;*Topic : Key Scan Subroutine ;*MCU : Z86L7X/8X/9X, Z86D73/D86
;* Function:Scan the key pad and return key code in the ;* KEY_SCANCODE KEY_BUFFER & KEY_BUFFER+1 also registers. ;* If there are more than two keys pressed, they are ;* ignored ;* key ;* Input: press ;* Column output - - P0 ;* Row input - - P2 ;* Output: KEY_SCANCODE - - - - the scan code ;* Upper nibble is the Row (Port 2); ;* Lower nibble is the Column (Port 0). ;* KEY_BUFFER & KEY_BUFFER+1 - - - ;* KEY_SCANCODE AND THE 2ND KEY ;* Carry - - - - Set if there is a valid key press ;* CLEAR if no key or more than two keys ;* num_key - - - - contains the number of key pressed ;----------------------------------------------------------------column row column_num row_num num_key tempreg p2_counter KEY_SCANCODE KEY_BUFFER KEY_BUFFER+1 Key_Scan: PUSH LD push .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU .EQU r15 r14 r13 r12 r11 r10 r9 5 6 7 ;column to scan ;input row value ;column number ;row number ;number of keys detected

RP RP,#%50 p0

;Save the calling routines RP

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push CLR ld ld ld LD

p3 num_key KEY_SCANCODE, #%ff KEY_BUFFER,#%ff KEY_SCANCODE+1, #%ff column, #%7F

;flag for number of keys detected ;reset KEY_SCANCODE register ;reset KEY_BUFFER register ;reset KEY_SCANCODE+1 register ;all high except column 7 ;low scan pulse is on P07

;------ start with first column ld column_num,#7 next_column: call setup_p2 ;precharge Port 2 to High LD p0, column ;make scan column low ;----------------------------------------------------------------;Delay is used to let Port 0 output port settle down ;from noise or voltage coupling ; Delay loop - - 12 cycles x 36 = 432 cycles ; = 432 x 0.25 us (@ MHz) ; = 108 microseconds ;---------------------------------------------------------p0_delay .EQU 36 ;row register is used temporarily ld row, #p0 delay ;for timing key_delay ; 12 cycles instruction: wait djnz row,key_delay: ; for port to settle ;----------------------------------------------------------------LD row,p2 ;read in part of the rows ;------- check keys in this column COM row ;p2 is normal High, when a key is pressed, that row ;will be low ;after complement, there will be "1" on that row JR z,next_col_prep ;no key this column ;convert row to row number and add the column number COM row CLR row_num ;row number = 0 next_row: RCF RRC row ;rotate the row input right by 1 bit JR C,nokey_row ;no key this row cp num_key,#2 ;accept two keys max jr uge,no_key ;more than two keys, ignore all ;------ calculate the keycode & store, ; row number x 16 + column number + 1 PUSH row_num ;save a copy SWAP row_num ;move the row number to the high ;nibble OR row_num,column_num ;put in the column number (low nibble) ;Port 2 in upper nibble, Port 0 in lower nibble LD KEY_SCANCODE ;row_num;the scancode KEY_BUFFER (num_key) LD , row_num ;Store in buffer INC num_key ;increment number of keys detected POP row_num ;recover row_num

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nokey_now INC row_num ;go to next row CP row_num,#8 JR LT,next_row ;if there are more rows to check ;------ finished with one column, see if there are more next_col_prep: RR column ;next column output sub column_num,#1 jr nc,next_column ;next column number end: RCF and num_key,num_key jr z,no_key SCF no_key: pop p3 pop p0 POP RP RET ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Port 2 must have pull-up and not connect to zero while not in use. ;-----------------------------------------------------------------------; P3m = %01 already: Port 2 is push pull while output ; p0 will have new value, and old data will be gone ; ----------------------------------------------------------------------setup_p2: ld p0,#%FF ;output high at Port 0 ld p2,#%FF ;output high at Port 2 ld p2m,#0 ;set p2 as output delay_port push p2_counter ;10 cycles ld p2_counter,#3 ;10 cycles key_delay0 djnz p2_counter,key_delay0 pop p2_counter ;10 cycles ld p2m,#%ff ;set p2 as input ret

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Appendix C Low-Voltage Detection

;*********************************************************** ;* Copyright 2003 ZiLOG Inc. ;* ;* Infrared Universal Remote Control ;* ;* ZiLOG Inc. ;* 532 Race Street ;* San Jose, CA 95126-3432 ;* USA ;* Tel: 408-558-8500 ;* Fax: 408-558-8300 ;* ;*Assembler & Linker : ZDS ;*Topic : Low Voltage Detection ;*MCU : Z86L7X/8X/9X, Z86D73/D86 ;* ;*P34 : output 0 to start the LVD ;*P31 : =1 if low voltage detected ;* : =0 if low voltage not detected ;* ;*Input : P31 ;*Output : STATUS register bit 0 = 1 if low voltage ;* =0 if voltage is normal ;* ;*********************************************************** .LOW_BATTERY .equ 00000001b STATUS .equ %10 Low_Voltage_Detection: ld p3m,#%03 ;P3 in analog mode. and p3,#11101111b ;set P34 low to start the LVD call Delay10ms tm p3,#00000010b jr z, battery_OK battery_low: OR STATUS,#.LOW_BATTERY jr end_check_battery_low battery_OK: AND STATUS,# ^C.LOW_BATTERY end_check_battery_low: OR p3,#00010000B ld p3m,#1;P3 in digital mode. ret

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;*********************************************************** ;10 ms delay subroutine is shared by other subroutine call ;Delay 10 ms in the Halt mode ;wait for interrupt from T16 timer ;***********************************************************
Delay10ms: PUSH RP Ld rp,#%0D ;set P to register groupD and bank0 ;-------- Enable T16 for interrupt LD ctr2,#01111010b LD tc16h,#high(5000) ;the maximum count LD tc161,#low(5000) ;about 10 ms LD ctr2,#01111010b ;start and enable T16 interrupt POP RP EI NOP HALT DI RET

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