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Advances in I packaging, interconnect and assembly. C SAGE Maurice BPA Technology & Management Abinger House Church Street GB-DORKINC RHb IDF UNITED KINGDOM

Without innovative packaging and interconnection technologies, the revolutionary advances taking place in integrated circuits will be lost. The rapid growth of the integrated circuit industry has intended to hide the fact that not only do all the other components comprise a much larger market value, but packaging and interconnection has now become one of the major barriers to improving both system cost and performance. This paper looks at the driving forces in electronics and how these will significantly impact the current and widely used technologies of I C packaging, PCBs and Hybrids. Even now these three areas are

reaching their technical and cost limits in advanced systems, and new technologies are urgently needed. One major new technology is the multichip module, a hybrid for wafer scale integration. The opportunity to purchase wafers and select good die could make this technology a less expensive assembly approach than SMT. The ability to mix I C technologies and exercise more efficient thermal management makes this development a major stepping stone towards wafer-scale integration. Its impact on the PCB and thick film hybrid industries will be a major feature of the paper.

Major advances in I C technology urgently require complementary advances in packaging and interconnection. PCBs and thick film hybrids are finding it increasingly difficult to achieve the density of interconnection required, not only for higher pin-count integrated circuits but also for faster speed, controlled impedance lines and thermal management. The ability to integrate more active and passive components on silicon is allowing the industry to build increasingly advanced cost effective products that will rapidly expand the current markets and open up new ones. For some applications V L S I may mean only one or two major I C s with relatively low signal interconnections between them, ie 5 0 to 1 5 0 , so they can be individually mounted in advanced, but conventional packages, eg PGAs, PLCCs, interconnected with limited numbers of other components on dense PCBs, multilayer ceramic or thick film substrates. However, for the vast majority of advanced digital applications, where the use of V L S I has the greatest advantage from a

performance and cost point of view, the number of interconnects required is much higher, ie 1 5 0 - 3 5 0 now, 350-500 by 1 9 9 0 . This complexity and density of the off-chip connections, increased by requirements for distributed ground and power I C pins, faster speeds and higher power densities are difficult if not impossible for the conventional I C package and the interconnect substrate technologies. The current interconnection and I C packaqinq khnoloqies developed over the past twenty four years cannot meet the demands of the 'VLSI era'.
The Density Problem

the density of interconnection continues to increase on integrated circuits (feature sizes are expected to reach 0.3 micron during the nineties) the ability of PCB and thick film hybrid technology to complement this trend becomes increasingly difficult. The problems are particularly evident in escalating costs and restricted performance. Figure 1 shows the increasing cost of PCBs against density while Figure 2 illustrates the feature size 'gap' that is opening up between integrated circuits and PCB technologies.
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Figure 1 PRICE/CIRCUIT DENSITY OF PCBS TOTAL OF USA, JAPAN AND WESTERN EUROPE
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This gap is being filled by a number of new technologies of which the Multichip Module (MCM) is the most significant. Over the past few years there has been a great deal of speculation about the introduction of Wafer-Scale Integration (WSI), why not straight to this technology? Wafer-Scale Inteqration

When?

Few subjects in electronic technology have attracted such widespread interest as wafer-scale integration. The idea of putting complete electronic systems on a wafer has great appeal. The advantages of wSI are significant and hold out the following:

proposed as a good application for WSI but discrete memory chips on PCBs or hybrids are currently much more economic. Random logic for application specific systems, using standard VLSI processes, would appear to be the best use for WSI. This is providing fault and failure tolerance problems are solved together with massive testability. However, additional concerns could still be the poor cross wafer transmission line characteristics, power dissipation and pin-count. Undoubtedly these problems will be solved but not in the short term, particularly while feature size reduction in VLSI is still possible. The functional density of VLSI has been achieved more by reducing the feature size than by increases in chip size. Figure 3 illustrates that between 1977 and 1983 the DRAM went from 16K to 256K bits but the chip size only went up from 20 to 40mm2 ie doubling in 6 years. It is expected that feature size will decrease to around 0.3 microns and on current projections that will be around the mid to late nineties. By this time the failure and fault tolerance problems could well be resolved as well as the major test routines.

. . .

Lower cost/function due to higher levels of integration made possible by fault tolerance Higher performance through smaller interconnection lengths and signal delays Higher reliability made possible by the aluminium on silicon interconnection and failure tolerance

However these advantages are not yet' commercially feasible. Memory has been

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THE MULTICHIP MODULE

The ability to mix chip technologies. Bulky IC packaging may be avoided by selecting good die from wafers. Die protection. The assembly approach may well be less costly, smaller and lighter, than SMT using packaged ICs. Repairability Opportunities for free market suppliers. However the range of skills necessary for operating in this business should not be underestimated; see Figure 4 .

While development work proceeds on waferscale integration the multichip module will make a significant worldwide penetration into the electronics industry. In many respects the multichip module is a hybrid for wafer-scale integration. Many multichip modules will make use of inteqrated circuit technoloqy for track generation, with feature sizes of 5 micron, utilising thin film processes with low dielectric constant materials such as polyimide. These technologies will be built on substrates such as silicon, multilayer ceramic, aluminium nitride, silicon carbide and can themselves include power and ground planes. Instead of forcing PCB and thick film technology to higher densities, integrated circuit manufacturing processes will be utilised to bridge the feature size gap * It is already apparent that in their least sophisticated form these substrates can provide track densities of around 3-400 inches/square inch for costs which are at least two orders lower per square inch than equivalent PCB or available multilayer ceramics. Advantages offered by multichip modules include: Fine line feature sizes combined with low dielectric constant materials, providing a substrate for high performance chip to chip interconnection.

Less Expensive than SMT The majority of multichip modules are expected to use protected die, selected from bought-in or own-manufactured wafers. It is anticipated that the final multichip module assembly could be less expensive than SMT,ie packaged ICs. Certainly the size of multichip modules will be a lot smaller than their SMT equivalent. Market Demand for Multichip Module The demand for complementary interconnection and packaging to meeting the needs of advancing integrated circuits is growing fast and has significant implications for the whole industry. The market for multichip modules is forecast at $Cbn for the substrate and its interconnection by 1 9 9 5 .

Fisure 4
MULTICHIP MODULE INPUT SKILLS

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Physical and Electronic

Thin Film Multilayer

Heat Management

IC Packaging

Materia 1 s

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Construction Assembly
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Test