74HC240; 74HCT240

Octal buffer/line driver; 3-state; inverting

Rev. 03 2 August 2007 Product data sheet

1. General description
The 74HC240; 74HCT240 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC240; 74HCT240 is a dual octal inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a high impedance OFF-state. The 74HC240; 74HCT240 is similar to the 74HC244; 74HCT244 but has inverting outputs.

2. Features
s s s s Inverting 3-state outputs Multiple package options Complies with JEDEC standard no. 7 A ESD protection: x HBM JESD22-A114-D exceeds 2000 V x MM JESD22-A115-A exceeds 200 V s Specied from 40 C to +85 C and from 40 C to +125 C

3. Ordering information
Table 1. Ordering information Package Temperature range Name 74HC240 74HC240N 74HC240D 74HC240DB 74HC240PW 74HC240BQ 40 C to +125 C 40 C to +125 C 40 C to +125 C 40 C to +125 C 40 C to +125 C DIP20 SO20 SSOP20 TSSOP20 plastic dual in-line package; 20 leads (300 mil) plastic small outline package; 20 leads; body width 7.5 mm plastic shrink small outline package; 20 leads; body width 5.3 mm SOT146-1 SOT163-1 SOT339-1 Description Version Type number

plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm

DHVQFN20 plastic dual-in-line compatible thermal enhanced SOT764-1 very thin quad at package; no leads; 20 terminals; body 2.5 4.5 0.85 mm DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1

74HCT240 74HCT240N 40 C to +125 C

NXP Semiconductors

74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting

Table 1.

Ordering information continued Package Temperature range Name Description plastic small outline package; 20 leads; body width 7.5 mm plastic shrink small outline package; 20 leads; body width 5.3 mm Version SOT163-1 SOT339-1 40 C to +125 C 40 C to +125 C 40 C to +125 C 40 C to +125 C SO20 SSOP20 TSSOP20

Type number 74HCT240D 74HCT240DB 74HCT240PW 74HCT240BQ

plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm

DHVQFN20 plastic dual-in-line compatible thermal enhanced SOT764-1 very thin quad at package; no leads; 20 terminals; body 2.5 4.5 0.85 mm

4. Functional diagram

1A0

1Y0

18

1A1

1Y1

16

1A2

1Y2

14

8 EN 18 16 14 12 15 17 1

1A3

1Y3

12

2 2 17 4 15 6 13 8 11 1 19 1A0 2A0 1A1 2A1 1A2 2A2 1A3 2A3 1OE 2OE
mgu779

1OE

1Y0 18 2Y0 3 1Y1 16 2Y1 5

4 6 8

2A0

2Y0

2A1

2Y1

19 1Y2 14 2Y2 7 11 1Y3 12 2Y3 9 13 15 17

EN 9 7 5 3
mgu778

13

2A2

2Y2

11

2A3

2Y3

19

2OE

mgu780

Fig 1. Logic symbol

Fig 2. IEC logic symbol

Fig 3. Functional diagram

74HC_HCT240_3

NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 2 August 2007

2 of 18

NXP Semiconductors

74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting

5. Pinning information
5.1 Pinning
74HC240 74HCT240
1OE 2 3 4 5 6 7 8 9 GND 10 2A3 11 GND(1) 1 terminal 1 index area 20 VCC 19 2OE 18 1Y0 17 2A0 16 1Y1 15 2A1 14 1Y2 13 2A2 12 1Y3

74HC240 74HCT240
1OE 1A0 2Y0 1A1 2Y1 1A2 2Y2 1A3 2Y3 1 2 3 4 5 6 7 8 9 20 VCC 19 2OE 18 1Y0 17 2A0 16 1Y1 15 2A1 14 1Y2 13 2A2 12 1Y3 11 2A3
001aag233

1A0 2Y0 1A1 2Y1 1A2 2Y2 1A3 2Y3

GND 10

001aag234

Transparent top view

(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input

Fig 4. Pin conguration DIP20, SO20, (T)SSOP20

Fig 5. Pin conguration DHVQFN20

5.2 Pin description

Table 2. Symbol 1OE 1A0 2Y0 1A1 2Y1 1A2 2Y2 1A3 2Y3 GND 2A3 1Y3 2A2 1Y2 2A1 1Y1
74HC_HCT240_3

Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description output enable input (active LOW) data input bus output data input bus output data input bus output data input bus output ground (0 V) data input bus output data input bus output data input bus output
NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 2 August 2007

3 of 18

NXP Semiconductors

74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting

Table 2. Symbol 2A0 1Y0 2OE VCC

Pin description continued Pin 17 18 19 20 Description data input bus output output enable input (active LOW) supply voltage

6. Functional description
Table 3. Input nOE L L H
[1] H = HIGH voltage level; L = LOW voltage level; X = dont care; Z = high-impedance OFF-state.

Function table[1] Output nAn L H X nYn H L Z

7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg Ptot Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation DIP20 package SO20, SSOP20, TSSOP20 and DHVQFN20 packages
[1] For DIP20 packages: above 70 C, Ptot derates linearly with 12 mW/K. For SO20 packages: above 70 C, Ptot derates linearly with 8 mW/K. For SSOP20 and TSSOP20 packages: above 60 C, Ptot derates linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 C, Ptot derates linearly with 4.5 mW/K.
[1]

Conditions VI < 0.5 V or VI > VCC + 0.5 V VO < 0.5 V or VO > VCC + 0.5 V 0.5 V < VO < VCC + 0.5 V

Min 0.5 70 65 -

Max +7 20 20 35 70 +150 750 500

Unit V mA mA mA mA mA C mW mW

74HC_HCT240_3

NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 2 August 2007

4 of 18

NXP Semiconductors

74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting

8. Recommended operating conditions

Table 5. Symbol 74HC240 VCC VI VO t/V supply voltage input voltage output voltage input transition rise and fall rate VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Tamb 74HCT240 VCC VI VO t/V Tamb supply voltage input voltage output voltage input transition rise and fall rate VCC = 4.5 V ambient temperature 4.5 0 0 40 5.0 1.67 5.5 VCC VCC 139 +125 V V V ns/V C ambient temperature 2.0 0 0 40 5.0 1.67 6.0 VCC VCC 625 139 83 +125 V V V ns/V ns/V ns/V C Recommended operating conditions Parameter Conditions Min Typ Max Unit

9. Static characteristics
Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 74HC240 VIH HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level VI = VIH or VIL output voltage IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 6.0 mA; VCC = 4.5 V IO = 7.8 mA; VCC = 6.0 V 1.5 3.15 4.2 1.9 4.4 5.9 1.2 2.4 3.2 0.8 2.1 2.8 2.0 4.5 6.0 0.5 1.35 1.8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 V V V V V V V V V V V Conditions Min 25 C Typ Max 40 C to +85 C 40 C to +125 C Unit Min Max Min Max

3.98 4.32 5.48 5.81

74HC_HCT240_3

NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 2 August 2007

5 of 18

NXP Semiconductors

74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting

Table 6. Static characteristics continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL Conditions Min LOW-level VI = VIH or VIL output voltage IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 6.0 mA; VCC = 4.5 V IO = 7.8 mA; VCC = 6.0 V II IOZ input leakage current OFF-state output current VI = VCC or GND; VCC = 6.0 V per input pin; VI = VIH or VIL; VO = VCC or GND; other inputs at VCC or GND; VCC = 6.0 V; IO = 0 A 25 C Typ 0 0 0 0.15 0.16 Max 0.1 0.1 0.1 0.26 0.26 0.1 0.5 40 C to +85 C 40 C to +125 C Unit Min Max 0.1 0.1 0.1 0.33 0.33 1.0 5.0 Min Max 0.1 0.1 0.1 0.4 0.4 1.0 10 V V V V V A A

ICC CI

supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V input capacitance HIGH-level input voltage LOW-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V

3.5

8.0 -

80 -

160 -

A pF

74HCT240 VIH VIL VOH 2.0 1.6 1.2 0.8 2.0 0.8 2.0 0.8 V V

HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 20 A IO = 6 mA LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 20 A IO = 6.0 mA input leakage current OFF-state output current VI = VCC or GND; VCC = 5.5 V per input pin; VI = VIH or VIL; VO = VCC or GND; other inputs at VCC or GND; VCC = 5.5 V; IO = 0 A

4.4

4.5

0.1 0.26 0.1 0.5

4.4 3.84 -

0.1 0.33 1.0 5.0

4.4 3.7 -

0.1 0.4 1.0 10

V V V V A A

3.98 4.32 0 0.16 -

VOL

II IOZ

ICC ICC

supply current VI = VCC or GND; VCC = 5.5 V; IO = 0 A additional per input pin; supply current VI = VCC 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A nAn or inputs nOE input

8.0

80

160

150 70 3.5

540 252 -

675 315 -

735 343 -

A A pF

CI

input capacitance

74HC_HCT240_3

NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 2 August 2007

6 of 18

NXP Semiconductors

74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting

10. Dynamic characteristics

Table 7. Dynamic characteristics GND = 0 V; for load circuit see Figure 8. Symbol Parameter Conditions Min 74HC240 tpd propagation delay nAn to nYn; see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V ten enable time nOE to nYn; see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tdis disable time nOE to nYn or see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tt transition time see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CPD power dissipation capacitance per transceiver; VI = GND to VCC
[5] [4] [3] [2] [1]

25 C Typ Max

40 C to +125 C Unit Max (85 C) Max (125 C)

30 11 9 9 39 14 11 41 15 12 14 5 4 30

100 20 17 150 30 26 150 30 26 60 12 10 -

125 25 21 190 38 33 190 38 33 75 15 13 -

150 30 26 225 45 38 225 45 38 90 18 15 -

ns ns ns ns ns ns ns ns ns ns ns ns ns pF

74HC_HCT240_3

NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 2 August 2007

7 of 18

NXP Semiconductors

74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting

Table 7. Dynamic characteristics continued GND = 0 V; for load circuit see Figure 8. Symbol Parameter Conditions Min 74HCT240 tpd propagation delay nAn to nYn; see Figure 6 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF ten tdis tt CPD enable time disable time transition time power dissipation capacitance nOE to nYn; VCC = 4.5 V; see Figure 7 nOE to nYn; VCC = 4.5 V; see Figure 7 VCC = 4.5 V; see Figure 6 per transceiver; VI = GND to VCC 1.5 V
[2] [1]

25 C Typ Max

40 C to +125 C Unit Max (85 C) Max (125 C)

11 9 13 13 5 30

20 30 25 12 -

25 38 31 15 -

30 45 38 18 -

ns ns ns ns ns pF

[3]

[4] [5]

[1] [2] [3] [4] [5]

tpd is the same as tPHL and tPLH. ten is the same as tPZH and tPZL. tdis is the same as tPHZ and tPLZ. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs.

11. Waveforms
VI nAn input GND tPHL VOH nYn output VOL
mgu781

VM

VM

tPLH

VM

VM

Measurement points are given in Table 8. VOL and VOH are typical voltage output drop that occur with the output load.

Fig 6. Input (nAn) to output (nYn) propagation delays and output transition times

74HC_HCT240_3

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Product data sheet

Rev. 03 2 August 2007

8 of 18

NXP Semiconductors

74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting

VI nOE input GND t PLZ VCC nYn output LOW-to-OFF OFF-to-LOW VOL t PHZ VOH nYn output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled
001aae014

VM

t PZL

VM VX t PZH VY VM

Measurement points are given in Table 8. VOL and VOH are typical voltage output drop that occur with the output load.

Fig 7. 3-state enable and disable times Table 8. Type 74HC240 74HCT240 Measurement points Input VM 0.5 VCC 1.3 V Output VM 0.5 VCC 1.3 V VX 0.1 VCC 0.1 VCC VY 0.9 VCC 0.9 VCC

74HC_HCT240_3

NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 2 August 2007

9 of 18

NXP Semiconductors

74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting

VI negative pulse 0V

tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM

VI positive pulse 0V

VCC

VCC

PULSE GENERATOR

VI

VO

RL

S1

DUT
RT CL

open

001aad983

Test data is given in Table 9. Denitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch.

Fig 8. Load circuitry for measuring switching times Table 9. Type 74HC240 74HCT240 Test data Input VI VCC 3V tr, tf 6 ns 6 ns Load CL 15 pF, 50 pF 15 pF, 50 pF RL 1 k 1 k S1 position tPHL, tPLH open open tPZH, tPHZ GND GND tPZL, tPLZ VCC VCC

74HC_HCT240_3

NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 2 August 2007

10 of 18

NXP Semiconductors

74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting

12. Package outline

DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1

D seating plane

ME

A2

A1

c Z e b1 b 20 11 MH w M (e 1)

pin 1 index E

10

5 scale

10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D
(1)

(1)

e 2.54 0.1

e1 7.62 0.3

L 3.60 3.05 0.14 0.12

ME 8.25 7.80 0.32 0.31

MH 10.0 8.3 0.39 0.33

w 0.254 0.01

Z (1) max. 2 0.078

26.92 26.54 1.060 1.045

6.40 6.22 0.25 0.24

Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT146-1 REFERENCES IEC JEDEC MS-001 JEITA SC-603 EUROPEAN PROJECTION

ISSUE DATE 99-12-27 03-02-13

Fig 9. Package outline SOT146-1 (DIP20)

74HC_HCT240_3 NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 2 August 2007

11 of 18

NXP Semiconductors

74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting

SO20: plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

A X

c y HE v M A

Z 20 11

Q A2 A1 pin 1 index Lp L 1 e bp 10 w M detail X (A 3) A

5 scale

10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)

0.9 0.4

0.012 0.096 0.004 0.089

0.019 0.013 0.014 0.009

0.419 0.043 0.055 0.394 0.016

0.035 0.004 0.016

8 o 0

Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 JEITA EUROPEAN PROJECTION

ISSUE DATE 99-12-27 03-02-19

Fig 10. Package outline SOT163-1 (SO20)

74HC_HCT240_3 NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 2 August 2007

12 of 18

NXP Semiconductors

74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting

SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm

SOT339-1

A X

c y HE v M A

Z 20 11

Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 10 w M detail X A

2.5 scale

5 mm

DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 7.4 7.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.9 0.5 8 o 0
o

Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION

ISSUE DATE 99-12-27 03-02-19

Fig 11. Package outline SOT339-1 (SSOP20)

74HC_HCT240_3 NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 2 August 2007

13 of 18

NXP Semiconductors

74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm

SOT360-1

c y HE v M A

20

11

Q A2 pin 1 index A1 (A 3) A

Lp L

1
e bp

10
w M detail X

2.5 scale

5 mm

DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8 o 0
o

Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19

Fig 12. Package outline SOT360-1 (TSSOP20)

74HC_HCT240_3 NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 2 August 2007

14 of 18

NXP Semiconductors

74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting

DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm

A A1 E c

terminal 1 index area

detail X

terminal 1 index area e 2 L

e1 b 9 v M C A B w M C y1 C

C y

1 Eh 20

10 e 11

19 Dh 0

12 X 2.5 scale 5 mm

DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.6 4.4 Dh 3.15 2.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1

Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT764-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27

Fig 13. Package outline SOT764-1 (DHVQFN20)

74HC_HCT240_3 NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 2 August 2007

15 of 18

NXP Semiconductors

74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting

13. Abbreviations
Table 10. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic

14. Revision history

Table 11. Revision history Release date 20070802 Data sheet status Product data sheet Change notice Supersedes 74HC_HCT240_CNV_2 Document ID 74HC_HCT240_3 Modications:

The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added type number 74HC240BQ and 74HCT240BQ (DHVQFN20 package) Product specication -

74HC_HCT240_CNV_2

19970828

74HC_HCT240_3

NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 2 August 2007

16 of 18

NXP Semiconductors

74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting

15. Legal information

15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]

Product status[3] Development Qualication Production

Denition This document contains data from the objective specication for product development. This document contains data from the preliminary specication. This document contains the product specication.

Please consult the most recently issued document before initiating or completing a design. The term short data sheet is explained in section Denitions. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

15.2 Denitions
Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofce. In case of any inconsistency or conict with the short data sheet, the full data sheet shall prevail.

malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specied use without further testing or modication. Limiting values Stress above one or more limiting values (as dened in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/prole/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

15.3 Disclaimers
General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or

15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

16. Contact information

For additional information, please visit: http://www.nxp.com For sales ofce addresses, send an email to: salesaddresses@nxp.com

74HC_HCT240_3

NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 03 2 August 2007

17 of 18

NXP Semiconductors

74HC240; 74HCT240
Octal buffer/line driver; 3-state; inverting

17. Contents
1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Denitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information.

NXP B.V. 2007.

All rights reserved.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 August 2007 Document identifier: 74HC_HCT240_3