Computer Architecture

Direct Memory Access

DIRECT MEMORY ACCESS

It is a known fact that the speed of CPU is very high in comparison to that of the main memory and the storage devices. This disparity in speeds affects the data transfer rate between the storage devices and the main memory. One method to improve the data transfer speed is to cut out the CPU from the corridor between the storage devices and the main memory and allow the storage devices to take control over the memory buses. This practice is known as Direct Memory Access. It is obvious that the CPU has no control over the memory buses at the time when data transfer is being performed during DMA. Instead, it is the DMA controller that takes holds the control over the buses and manages the data transfer. Whenever the I/O devices request for DMA, the CPU passes on the control of the system bus to the requesting I/O device. However, it must be noted that an interrupt signal is not a request for grant of control over the system bus; rather it is a request to the CPU to commence execution of an interrupt interface program. Therefore, the CPU intervention is required during the initial stages of the DMA. Procedure for DMA Transfer The DMA transfer procedure involves following steps:1. The CPU executes two instructions which load the IOAR (Input-Output Address Register) and DC (Data Count) Register with initial values where the initial values are base address of the memory block for IOAR and number of words for the DC Register. 2. When the DMA controller is ready to transmit or receive data, it activates DMA Request Line to the CPU. The CPU waits for the nest DMA Break Point. It then gives control of Data and Address Bus, and activates DMA Acknowledge Line to the DMA.

3. DMA controller transfers data directly to or

from main memory, after the transfer of a word, IOAR is incremented and DC register is incremented. If DC is not decremented to zero, but the device is not ready to send or receive data, then DMA controller must return the control of the system bus to the CPU and deactivate the DMA Request Line. The CPU responds by deactivating DMA Acknowledge Line and resumes normal operation. If DC Register is decremented to zero, then also the DMA controller should return the control to the CPU. The CPU responds by halting the I/O device.

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Methods for DMA Transfer of Data Data can be transferred in several ways under DMA control. These methods are discussed below: 1. DMA Block Transfer: A sequence of data words of an arbitrary length is transferred in a single stream while DMA controller is the master of the bus, i.e. System Bus. Block DMA supports maximum I/O data transmission rates but it may require the CPU to remain inactive for relatively longer periods, and this accounts for the disadvantage of DMA block transfer. 2. Cycle Stealing Mode: This scheme allows the DMA controller to transfer data in one, two or more data words at a time after which it must return the control of the bus to the CPU. Thus, cycle stealing reduces the maximum I/O transfer rate but it also reduces interference by the DMA controller in other activities of the CPU. 3. Transparent DMA: Here, the bus cycles are stolen only when the CPU is not actually using the system bus.

Compiled by: Preetinder Singh Brar, Assistant Professor, Chitkara University, Punjab Campus Page 1

Computer Architecture

Direct Memory Access

Main Memory Address Bus (1 Line) Data Bus (2 Lines)

CPU
Address Register (AR) Instruction Register (IR) Accumulator (AC) Control Unit (CU) Data Count Register (DC) Control Unit (CU)

DMA Controller
IO Address Register (IOAR) IO Data Register (IODR)

I/O Devices

Fig: Block Diagram of DMA

Compiled by: Preetinder Singh Brar, Assistant Professor, Chitkara University, Punjab Campus Page 2