Elsevier Editorial System(tm) for Microelectronics Journal Manuscript Draft Manuscript Number: Title: I-V Characteristics of two-dimensional Nanodot-array

Single Electron Transistors Article Type: Research Paper Keywords: SET; SIMON; MISET; Orthodox theory; Coulomb oscillation Corresponding Author: Mr. hamed mehrara, Corresponding Author's Institution: First Author: Hamed Mehrara Order of Authors: Hamed Mehrara; hamed mehrara

Manuscript Click here to view linked References

I-V Characteristics of two-dimensional Nanodot-array Single Electron Transistors

Hamed Mehrara Department of Electrical Engineering, K.N.Toosi University of Technology , Seyyed Khandan Bridge, Tehran, Iran

Abstract: We present a two-dimensional nanodot-array single-electron transistor (2DA-SET) analytical current-voltage model on the basis of master equation and the orthodox theory. Electrical characteristics of these multi island singleelectron transistors composed of several island up to 5x5 nanodot array has been investigated using SIMON simulator to show the temperature dependence of the Coulomb oscillation of 2DA-SET by varying gate voltage in the temperature range from T=5 to 50K. In addition, effects of self island capacitance and inter-dot spacing variation on I-V characteristics of under study device have been inspected. Proportional increase in current value resulted from higher temperature values and different distribution of nanodot capacitance will be suppressed by the capacitance of whole nanodot-array network in arrays with multiple elements. The 2DA-SET device behaved as a single-island SET device regarding high drain voltage. This is probably because the network of islands were electrically enlarged and united into a single island owing to the high applied voltage. Finally, we compare the advantages of 2DA-SET face to single-island SET.

Keywords: SET; SIMON; MISET; Orthodox theory; Coulomb oscillation

1. Introduction
Nanodot device architecture is one of the ongoing technology in semiconductor electronics which has been achieved by continuously shrinking the minimum physical dimensions of the device and closely follows the trend predicted by Moores law states that the number of transistors per chip doubles roughly every 2 years [1]. Also recent studies in nanodot architecture such as array architecture assure them an important role for nanotechnological applications and make them most suitable for fundamental studies of disordered solids with programmable electronic properties [2]. In the other hand, CMOS fabrication facility has made it pioneer in low dimensional production even in nanoscale. But scaling of CMOS devices to the nanometer level would face limitations due to increased sub-threshold leakage, increased gate oxide leakage, transistor parameter variability and performance. These foreseen limits serve as the motivation to develop new devices and structures at the nanometer scale by conducting their architecture and arrangements [3-6]. One possible novel device is the multi-dot single-electron transistor (SET) which is expected to be a key device for future extremely large-scale integrated circuits especially in memory cells because of its

low power consumption and small size. Their main advantages in comparison to single-island singleelectron transistors with identical dimensions of islands and tunneling junctions are a higher threshold voltage of Coulomb blockade and, as a consequence, a higher operation temperature [7-11]. The models of one dimensional-array multi-island single-electron transistors on the basis of the solution of the Poisson equation, as well as on the basis of either the solution of the master equation or using the Monte Carlo method, were suggested previously [12,13]. These models are free of some disadvantages to some extent. The physics of processes in these device such as capacitances and resistances of tunneling junctions is lost accordingly and for other structures by single electron effect they need more revision. Such effects have been reported too in structures that can interpret as an array of islands and are more probable to fabricate (Fig. 1.). They form a multi tunneling junction (MTJ) exhibit enough depletion capacitances to observe single-electron effect even at room temperature [14, 15]. The major advantages of such devices come from the fact that they require a much simpler fabrication procedure than single-dot SETs and since several tunnel capacitances place in an extensive matrix format, the effective capacitance into the ground for any island becomes much smaller than the capacitance of each unit island SET so multidot devices exhibit Coulomb blockade effects at a much higher temperature even at room temperature.

Fig. 1. Schematic diagram of 2DA-SET.

This study is aimed at the analysis of the I-V characteristics of the two-dimension nanodot-array single-electron transistors, depending on the design parameters and the environmental temperature ,so at first we describe a new schematic of quadruplet-island SET (QISET) model and propose analytical equivalent circuit. Then, using SIMON simulator, the electrical characteristics of 2DA-SET devices will be investigated. Finally, we expose some advantages of 2DA-SET in comparison to single-island SETs.

2. The quadruplet island SET model The orthodox theory of single electronics which translates the quantization of charge into the quantization of the continuous spectrum of energy states associated with small metal islands, has an asymmetry in the description of the single-electron tunneling junction when excited with different sources. That is, high-ohmic and low- ohmic environments are treated differently. To a large extend this problem is due to the assumption of negligible tunneling time, a basic assumption in the orthodox theory. However, important elements such as cotunneling and tunneling into or out of quantum levels are not taken into account.

Fig. 2. Network of resistors and capacitors representing quadruplet island SET.

The quadruplet nanodot is modeled as a network of resistors and capacitors for 2x2 nanodot-array (Fig. 2). The number of electrons on each nanodot is N 11 , N 12 , N 21 and N 22 which are corresponding to node
1, 2,3 and 4 . Each dot is capacitively coupled to a gate voltage ( Vg 11 ,Vg 12 ,Vg 21 ,Vg 22 ) through a capacitor

( Cg11 ,Cg12 , Cg 21 , Cg 22 ) and to the source ( S ) or drain ( D ) contact through a tunnel barrier represented by a resistor R and a capacitor C connected in parallel. We assume the nanodots are coupled to each other by a same tunneling barrier represented by a resistor Rm and a capacitor Cm in parallel. It can suppose that the nanodots are fabricated and arranged in a periodic pattern to optimize tunneling barrier potential between neighbors. The bias voltage V is applied to the source contact with the drain contact grounded (asymmetric bias). In this section we consider the linear transport regime, i.e. V 0 , in addition random background charges and initial charges on the islands are taken zero .If crosscapacitances shared with farther nanodots and other voltage sources and stray capacitances are negligible, the quadruplet dot electrostatic energy reads:
U(N11 , N 12 , N 21 , N 22 ) = U(N11 , N 12 ) + U(N11 , N 21 ) + U(N22 , N 21 ) + U(N22 , N 12 )

(1)

One term of this energy is described by:

U(N11 , N 12 ) =

1 N 11 2

Ec11 +

1 N 12 2

Ec12 + N 11 N 12 Ec m + f(Vg11 ,Vg 12 )

(2)

f(Vg11 ,Vg 12 ) = -

1 {Cg 11Vg 11(N11 Ec11 + N 11Ec m ) + Cg12Vg 12 (N12 Ec12 + N 11Ec m )} e

1 e
2

1 1 { Cg112Vg 112 Ec11 + Cg12 2Vg 12 2 Ec12 + Cg11Vg 11Cg12Vg 12 Ec m } 2 2

(3)

Where f(Vg11 ,Vg12 ) means the impact of produced energy by Vg 11 ,Vg12 and Ec11( Ec12 ) is the charging energy of the individual dot 1(2) and Ecm stands for the electrostatic coupling energy. The coupling energy Ecm is the change in the energy of one dot when an electron is added to the other dot. These energies can be expressed in terms of the capacitances as follows:
Ec11 = e2 e2 1 1 12 21 = ( )( ) Ceff 11 Ceff 11 1 - C m 2 /(Ceff11 Ceff 12 ) 1 - C m 2 /(Ceff11 Ceff 21 )

e2 1 1 Ec m = ( )( ) 2 2 C m C m /(Ceff11 Ceff 12 ) - 1 C m /(Ceff11 Ceff 21 ) - 1

(4)

Where:

Ceff 11 = C11 + Cg11 + 2Cm

(5)

Here Ceff11(12) is the equivalent capacitances attached to dot 1(2) .Note that Ec11 can be interpreted as the charging energy of the single, uncoupled dot '1 ' multiplied by two correction factors that account for the coupling. When Cm 0 and hence Ecm 0 , by symmetric assumption of capacitors and resistors of the net Eq. (1) reduces to:
U(N11 , N 12 , N 21 , N 22 ) =
N 11 , N 12 , N 21 , N 22 = N Vg 11 ,Vg 12 ,Vg 21 ,Vg 22 = Vg,

4(-N e CgVg) 2 C
Cg11 ,Cg12 , Cg 21 , Cg 22 = Cg Ceff 11 ,Ceff 12 , Ceff 21 , Ceff 22 = C

(6)

3. Discussion and results

3.1. Simulation results using SIMON

We use this schematic circuit diagram of QISET in SIMON simulator; here we use only one polarization source Vd because we choose the source potential at zero; after that we fix some parameters like temperature, mode of simulation, drain polarization, capacitances and tunnel junction values (selected by defaults), observe the charge and the current forms at T=5K. The I d Vg characteristic for original SET, Double-Island SET so-called DISET and QISET obtained using SIMON is presented in Fig. 3. By increasing gate voltage in original SET an electron transfer into and then out of the island. It makes a the first peak shape current, in gate voltage range from Vthershold to Vthershold v period . In a DISET, that electron should pass three tunneling junction, but those only are placed at two ends of DISET model have significant barrier height for tunneling because gate voltage of the internal tunneling barrier vary together. Due to this circumstance, in voltage range from Vthershold to Vthershold v period / 2 one electron tunnel the first tunneling junction (TJ) , it passes internal barrier by a few gate energy (in voltage range [ , ]) then the last tunneling junction for Vthershold v period / 2 to Vthershold v period . A same theory it can be assumed for a QISET. The main differences are cotunneling of two electrons in each current peak and increasing coulomb oscillation region which is on account of lowering barrier height of the nearest TJ to drain due to increasing corresponding gates voltage. At T = 5K, we simulate the current of different

number of island; 3x3(3ISET), 4x4 (4ISET) and 5x5 (5ISET) array of nanodots as a function of gate voltage (Fig. 4). We note that, for QISET, there are 4 picks, two major picks and two small picks of the same supply value. For a 5ISET, there are 2 picks left and 2 pick right and a straight in the middle. We remark symmetric curves because we have chosen equal values of capacitances and tunnel junctions. For arrays with more elements, roughness of curves decreases.

Fig.3. Coulomb oscillations obtained in QISET, DISET and Original SET at T = 5K for Vd = 0.02V.

Fig.4. IdVg characteristics of 2DA-SET, respectively, for 3x3, 4x4 and 5x5 island simulated at T = 5K.

3.2. Temperature dependence Fig. 5 presents the temperature dependence of the Coulomb oscillation and Coulomb blockade, respectively, for QISET and 3x3 nanodots in the temperature range from 5 to 50K. Coulomb diamonds are clearly observed and Coulomb oscillations can be followed up to smaller than 50K. I d depends on the temperature at the peaks. It is noted that the value of internal peak increases with increasing temperature and internal picks disappear to some extent. For large temperature, our structure tends to a structure with one island.

Fig. 5. Coulomb oscillation of QISET and 3ISET as shown in the inset for different temperatures (T = 5, 25 and T = 50K).

3.3. Higher voltage effect For a high drain voltage, the 2DA-SET behaved as a single-island SET. This is probably because the islands are electrically enlarged and merged into a single island because of the high applied drain voltage. The height of tunnel barriers is lowered at a high applied Vd . Owing to the various barrier heights in the devices; the Fermi level of the electrode exceeds the height of one of the tunnel barriers at certain Vd . Thus, the device acts nearly as a single-island SET (Fig. 6). Comparing the I ds Vds characteristics in Fig. 7 at Vg = - 10, 10 and 20 mV, we remark that the current suppression region increases proportionally with the gate voltage. The increase of the number of junctions in a SET is often motivated by the necessity to increase the charging energy of the system and to reduce spontaneous cotunneling events. These events are associated with electron tunneling occurring in several junctions simultaneously. In order to make these devices more accurate, connected junctions should be increased. For this reason, we have proposed multi-island SET extend in two dimensional that have the advantages of high-temperature operation and

the suppression of cotunneling current. Their main advantages in comparison to single-island SETs with identical dimensions of islands and tunneling junctions are a higher threshold voltage of Coulomb blockade and, as a consequence, a higher operation temperature. The characteristics are less sensitive to the parasitic effect of cotunneling and to the inescapable extension of the main sizes of islands, tunneling junctions and etc.
Fig. 6. The behavior of IdVg characteristic for various drain voltages in 3ISET (T = 5K).

Fig. 7. Simulated IdVd characteristics of 3ISET (T = 5K).

3.4. Capacitance consideration Each nanodot is connected to gate voltage capacitively so that by a little variation in its voltage, period of current oscillation will be changed. Also it can alter blockade region. Variation in inter-dot spacing that declares tunneling condition makes some changes in tunneling in and out of internal barriers. At the network of island region, Fermi level of interior dots varies together but fringe islands carry higher barrier
Vg capacitance will be suppressed by the capacitance potential. In addition, different distribution of nanodot[v]

of whole nanodot-array network in arrays with multiple elements. Electrostatic energy as well as Eq.6 is at least 4N times more than a single-island SET which means much energy to charge. Fig. 8. shows energy spectrum of a unbiased QISET in transition to gate and drain biasing. Network of islands varies coherently versus gate voltage therefore its main influence on I-V is because of outer tunneling junctions.
Fig. 8. The energy spectrum of Quadruplet Island is quantized and splitted due to single-electron tunneling phenomenon.

4. Conclusion It seems difficult to realize stable electrical characteristics for Single-electron devices and it is reasonable to assume that regular nanodot array can form over the whole area of the substrate with distributed nanodot particles much more easily than a single chain of islands. Using SIMON simulator, we investigate the electrical characteristics of SETs based on two dimensional nanodot-array and show the temperature dependence of the Coulomb oscillation of the 2DA-SET as a function of gate voltage
V g in the temperature range from T = 5 to 50K. the I /V characteristics of different arrays, strongly

indicate that single electron transport through the nanodot arrays is dominated by the charging energy of the whole homogeneous interior nanodots so they affect the electrical transport properties of the device and transport mechanism is governed by next neighbor tunneling. Valley current tends to increase as

temperature increases. For a high drain voltage, the 2DA-SET behaved as a single-island device. This is probably because the internal islands that contribute in electron transport were electrically enlarged and merged into a single island as a result of high applied drain voltage.

Acknowledgements The authors would like to acknowledge the many valuable suggestions made by M. Malekmohammad, PhD student of Malek Ashtar University of Technology.

References

[1] A. Venkataratnam, A. Goel, Microelectronics Journal, 39 (2008) 1461-1468. [2] I. Beloborodov, A. Lopatin, V. Vinokur, K. Efetov, Reviews of Modern Physics, 79 (2007) 469-518. [3] R. Sachser, F. Porrati, M. Huth, Physical Review B, 80 (2009). [4] F. Porrati, R. Sachser, M. Strauss, I. Andrusenko, T. Gorelik, U. Kolb, L. Bayarjargal, B. Winkler, M. Huth, Nanotechnology, 21 (2010) 375302. [5] M. Jo, T. Kaizawa, M. Arita, A. Fujiwara, K. Yamazaki, Y. Ono, H. Inokawa, Y. Takahashi, J.-B. Choi, Materials Science in Semiconductor Processing, 11 (2008) 175-178. [6] Q. Wang, Y. Chen, S. Long, J. Niu, C. Wang, R. Jia, B. Chen, M. Liu, T. Ye, Microelectronic Engineering, 84 (2007) 1647-1651. [7] M. Hirasawa, S. Katsumoto, A. Endo, Y. Iye, Physica B: Condensed Matter, 249-251 (1998) 252-256. [8] J. Kauppinen, Microelectronic Engineering, 41-42 (1998) 503-506. [9] R. Augke, W. Eberhardt, S. Strahle, F. Prins, D. Kern, Microelectronic Engineering, 46 (1999) 141-144. [10] S. Bednarek, B. Szafran, J. Adamowski, Microelectronic Engineering, 51-52 (2000) 99-109. [11] A. Boubaker, M. Troudi, N. Sghaier, A. Souifi, N. Baboux, A. Kalboussi, Microelectronics Journal, 40 (2009) 543-546. [12] I.I. Abramov, S.A. Ignatenko, E.G. Novik, Semiconductors, 37 (2003) 1201-1204. [13] I.I. Abramov, S.A. Ignatenko, E.G. Novik, Semiconductors, 37 (2003) 564-568. [14] F. Raissi, M.S. Abrishamian, T. Emadi, IEEE Transactions on Electron Devices, 51 (2004) 339-344. [15] A. Dutta, S.P. Lee, Y. Hayafune, S. Hatatani, S. Oda, Japanese Journal of Applied Physics, 39 (2000) 264-267.

Cover Letter

I-V Characteristics of two-dimensional Nanodot-array Single Electron Transistors

Hamed Mehrara Department of Electrical Engineering, K.N.Toosi University of Technology , Seyyed Khandan Bridge, Tehran, Iran

Corresponding author

Hamed Mehrara

Email addresses:
HM:h.mehraraa@gmail.com

Article type: Research paper

Number of Manuscript pages: 9 pages Number of Figures: 8

Figure(1) Click here to download high resolution image

Figure(2) Click here to download high resolution image

Figure(3) Click here to download high resolution image

Figure(4) Click here to download high resolution image

Figure(5) Click here to download high resolution image

Figure(6) Click here to download high resolution image

Figure(6) Click here to download high resolution image

Figure(7) Click here to download high resolution image