High Speed Communication Circuits and Systems Lecture 7 Noise Modeling in Amplifiers

Michael H. Perrott
February 25, 2004 Copyright 2004 by Michael H. Perrott All rights reserved.

M.H. Perrott

Notation for Mean, Variance, and Correlation

Consider random variables x and y with probability density functions fx(x) and fy(y) and joint probability function fxy(x,y)

- Expected value (mean) of x is -

Note: we will often abuse notation and denote as a random variable (i.e., noise) rather than its mean The variance of x (assuming it has zero mean) is

- A useful statistic is
If the above is zero, x and y are said to be uncorrelated
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Relationship Between Variance and Spectral Density

Two-Sided Spectrum Sx(f)
A 2A

One-Sided Spectrum Sx(f)

-f2 -f1 0

f1

f2

f1

f2

Two-sided spectrum

- Since spectrum is symmetric

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One-sided spectrum defined over positive frequencies

- Magnitude defined as twice that of its corresponding

two-sided spectrum

In the next few lectures, we assume a one-sided spectrum for all noise analysis

The Impact of Filtering on Spectral Density

Sx(f)
A

|H(f)|2
B AB

Sy(f)

f y(t) H(f)

x(t)

For the random signal passing through a linear, time-invariant system with transfer function H(f)

- We see that if x(t) is amplified by gain A, we have

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Noise in Resistors

Can be described in terms of either voltage or current

R R en in

k is Boltzmanns constant

T is temperature (in Kelvins)

- Usually assume room temperature of 27 degrees Celsius

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Noise In Inductors and Capacitors

Ideal capacitors and inductors have no noise!

C L

In practice, however, they will have parasitic resistance

- Induces noise - Parameterized by adding resistances in parallel/series

with inductor/capacitor Include parasitic resistor noise sources

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Noise in CMOS Transistors (Assumed in Saturation)

ID

Transistor Noise Sources Drain Noise (Thermal and 1/f)

G S

Gate Noise (Induced and Routing Parasitic)

Modeling of noise in transistors must include several noise sources

- Drain noise Thermal and 1/f influenced by transistor size and bias - Gate noise

Induced from channel influenced by transistor size and bias Caused by routing resistance to gate (including resistance of polysilicon gate) Can be made negligible with proper layout such as fingering of devices
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Drain Noise Thermal (Assume Device in Saturation)

ind VGS G VD>V S D

Thermally agitated carriers in the channel cause a randomly varying current

ind
f

is called excess noise factor = 2/3 in long channel = 2 to 3 (or higher!) in short channel NMOS (less in PMOS) gdo will be discussed shortly

4kTgdo f

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Drain Noise 1/f (Assume Device in Saturation)

ind VGS G VD>V S D

Traps at channel/oxide interface randomly capture/release carriers

ind
f

drain 1/f noise

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- To minimize: want large area (high WL)

Parameterized by Kf and n 4kTgdo Provided by fab (note n 1) Currently: Kf of PMOS << Kf of NMOS due to buried channel

drain thermal noise

f
1/f noise corner frequency

Induced Gate Noise (Assume Device in Saturation)

ing VGS G VD>V S D indg

Fluctuating channel potential couples capacitively into the gate terminal, causing a noise gate current

ing
f slope = 20 dB/decade

- is gate noise coefficient Typically assumed to be 2 - Correlated to drain noise!

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4kTgdo f
5 ft

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Useful References on MOSFET Noise

Thermal Noise

- B. Wang et. al., MOSFET Thermal Noise Modeling for

Analog Integrated Circuits, JSSC, July 1994

Gate Noise

- Jung-Suk Goo, High Frequency Noise in CMOS Low -

Noise Amplifiers, PhD Thesis, Stanford University, August 2001 http://www-tcad.stanford.edu/tcad/pubs/theses/goo.pdf Jung-Suk Goo et. al., The Equivalence of van der Ziel and BSIM4 Models in Modeling the Induced Gate Noise of MOSFETS, IEDM 2000, 35.2.1-35.2.4 Todd Sepke, Investigation of Noise Sources in Scaled CMOS Field-Effect Transistors, MS Thesis, MIT, June 2002 http://www-mtl.mit.edu/research/sodini/sodinitheses.html
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Drain-Source Conductance: gdo

gdo is defined as channel resistance with Vds=0

- Transistor in triode, so that

- Equals g

for long channel devices

Key parameters for 0.18 NMOS devices

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Plot of gm and gd versus Vgs for 0.18 NMOS Device

4

Transconductances gm and gdo versus Gate Voltage Vgs

Vgs
M1 1.8 W = L 0.18

Transconductance (milliAmps/Volts)

Id

3.5 3

gd0=nCoxW/L(Vgs-VT)
2.5 2 1.5 1 0.5 0 0.4

gm (simulated in Hspice)

0.6

0.8

1 1.2 1.4 Gate Voltage Vgs (Volts)

1.6

1.8

For Vgs bias voltages around 1.2 V:

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Plot of gm and gd versus Idens for 0.18 NMOS Device

Transconductances g m and g do versus Current Density
4

Vgs
M1 1.8 W = L 0.18

Transconductance (milliAmps/Volts)

Id

3.5 3 2.5

gd0=nCoxW/L(Vgs-VT)
2 1.5 1 0.5 0

gm (simulated in Hspice)

100

200

300

400

500

600

700

Current Density (microAmps/micron)

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Noise Sources in a CMOS Amplifier

RD enD RG enG Rgpar engpar Cgd ing ID RG RD Vout Csb vs Vin RS Rdeg endeg 1 gg vgs Cgs gmvgs -gmbvs ro ind Cdb

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Remove Model Components for Simplicity

RD enD RG enG Rgpar engpar Cgd ing ID RG RD Vout Csb vs Vin RS Rdeg endeg 1 gg vgs Cgs gmvgs -gmbvs ro ind Cdb

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Key Noise Sources for Noise Analysis

RD enD RG enG

ing ID RG RD Vout

vgs

Cgs

gmvgs

ind

endeg vs Vin RS Rdeg

Transistor gate noise

Transistor drain noise

Thermal noise
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1/f noise
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Apply Thevenin Techniques to Simplify Noise Analysis

iout

D G
Zg Zgs ing vgs Cgs gmvgs

ind

S
Zdeg

iout

D G
Zg Zgs vgs Cgs gmvgs

indg

S
Zdeg

Assumption: noise independent of load resistor on drain

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Calculation of Equivalent Output Noise for Each Case

iout

D G
Zg Zgs ing vgs Cgs gmvgs

ind

S
Zdeg

iout

D G
Zg Zgs vgs Cgs gmvgs

indg

S
Zdeg

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Calculation of Zgs
iout

D G itest
Zg Zgs vtest vgs Cgs gmvgs

S
v1 Z deg

Write KCL equations

After much algebra:

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Calculation of
iout

D G
Zg Zgs vgs Cgs gmvgs itest

S
v1 Zdeg

Determine Vgs to find iout in terms of itest

After much algebra:

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Calculation of Output Current Noise Variance (Power)

iout

D
Iout

G D S
Zg Zgs vgs Cgs gmvgs indg

G
Zg

Zdeg

S
Zdeg

To find noise variance:

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Variance (i.e., Power) Calc. for Output Current Noise

Noise variance calculation

Define correlation coefficient c between ing and ind

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Parameterized Expression for Output Noise Variance

Key equation from last slide

Solve for noise ratio

Define parameters Zgsw and d

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Small Signal Model for Noise Calculations

iout

D
Iout

G D S
Zg Zgs vgs Cgs gmvgs indg

G
Zg

Zdeg

S
Zdeg

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Example: Output Current Noise with Zs = Rs, Zdeg = 0

Source iout Rs ens

Vin

Zgs

vgs

Cgs

gmvgs

indg

Step 1: Determine key noise parameters

- For 0.18 CMOS, we will assume the following

Step 2: calculate and Zgsw

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Calculation of Output Current Noise (continued)

Step 3: Plug values into the previously derived expression

Drain Noise Multiplying Factor

- For w << 1/(R C

s

gs):

Gate noise contribution

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Calculation of Output Current Noise (continued)

Step 3: Plug values into the previously derived expression

Drain Noise Multiplying Factor

- For w >> 1/(R C

s

gs):

Gate noise contribution

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Plot of Drain Noise Multiplying Factor (0.18 NMOS)

Drain Noise Multiplying Factor Versus Frequency for 0.18 NMOS Device
1

f << 1/(2RsCgs)
0.95

Drain Noise Gain Factor

0.9

0.85

0.8

f >> 1/(2RsCgs)
0.75 1/100 1/10 1 10 100

Normalized Frequency --- f/(2RsCgs) (Hz)

Conclusion: gate noise has little effect on common source amp when source impedance is purely resistive!
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Broadband Amplifier Design Considerations for Noise

indg
f drain 1/f noise gate noise contribution with purely resistive source impedance
2

4kTgdo

drain thermal noise

f
1/f noise corner frequency 1 2RsCgs

Drain thermal noise is the chief issue of concern when designing amplifiers with > 1 GHz bandwidth

- 1/f noise corner is usually less than 1 MHz - Gate noise contribution only has influence at high
frequencies

Noise performance specification is usually given in terms of input referred voltage noise
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Narrowband Amplifier Noise Requirements

indg
f drain 1/f noise gate noise contribution with purely resistive source impedance
2

4kTgdo

drain thermal noise

f
1/f noise corner frequency Narrowband amplifier frequency range 1 2RsCgs

Here we focus on a narrowband of operation

filtered out

- Dont care about noise outside that band since it will be - Using reactive elements in the source dramatically
impacts the influence of gate noise
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Gate noise is a significant issue here

Specification usually given in terms of Noise Figure

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The Impact of Gate Noise with Zs = Rs+sLg

Source iout Rs ens Lg

Vin

Zgs

vgs

Cgs

gmvgs

indg

Step 1: Determine key noise parameters

- For 0.18 CMOS, again assume the following

Step 2: Note that =1 , calculate Zgsw

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Evaluate Zgsw At Resonance

Source iout Rs ens Lg

Vin

Zgs

vgs

Cgs

gmvgs

indg

Set Lg such that it resonates with Cgs at the center frequency (wo) of the narrow band of interest

Calculate Zgsw at frequency wo

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The Impact of Gate Noise with Zs = Rs+sLg (Cont.)

Key noise expression derived earlier

Substitute in for Zgsw

Gate noise contribution

Gate noise contribution is a function of Q!

- Rises monotonically with Q

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At What Value of Q Does Gate Noise Exceed Drain Noise?

2 indg

Narrowband amplifier frequency range

4kTgdo

drain thermal noise gate noise contribution wo/2

Q2
f

Determine crossover point for Q value

- Critical Q value for crossover is primarily set by process

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Calculation of the Signal Spectrum at the Output

Source iout Rs ens Lg

Vin

Zgs

vgs

Cgs

gmvgs

indg

First calculate relationship between vin and iout

At resonance:

Spectral density of signal at output at resonant frequency

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Impact of Q on SNR (Ignoring Rs Noise)

2 indg

Narrowband amplifier frequency range

signal spectrum 4kTgdo drain thermal noise gate noise contribution wo/2

Q2

Q2
f

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SNR (assume constant spectra, ignore noise from Rs):

For small Q such that gate noise < drain noise

- SNR - SNR

out

improves dramatically as Q is increased improves very little as Q is increased

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For large Q such that gate noise > drain noise

out

Noise Factor and Noise Figure

enRs Equivalent output referred current noise (assumed to be independent of Zout and ZL)

Rs

vin Zin

vx

Linear,Time Invariant Circuit (Noiseless)

inout Zout ZL

iout

Definitions

Calculation of SNRin and SNRout

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Calculate Noise Factor (Part 1)

Source iout Rs ens Lg

Vin

Zgs

vgs

Cgs

gmvgs

indg

First calculate SNRout (must include Rs noise for this)

-R

noise calculation (same as for Vin)

- SNR

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out:

Then calculate SNRin:

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Calculate Noise Factor (Part 2)

Noise Factor calculation:

From previous analysis

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Calculate Noise Factor (Part 3)

Modify denominator using expressions for Q and wt

Resulting expression for noise factor:

- Noise factor primarily depends on Q, w /w , and process specs

o t

Noise Factor scaling coefficient

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Minimum Noise Factor

Noise Factor scaling coefficient

We see that the noise factor will be minimized for some value of Q

- Could solve analytically by differentiating with respect

to Q and solving for peak value (i.e. where deriv. = 0)

In Tom Lees book (pp 272-277), the minimum noise factor for the MOS common source amplifier (i.e. no degeneration) is found to be:

Noise Factor scaling coefficient

How do these compare?

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Plot of Minimum Noise Factor and Noise Factor Vs. Q

Noise Factor Scaling Coefficient Versus Q for 0.18 NMOS Device
8 7

Noise Factor Scaling Coefficient

6 5 4 3 2 1 0

c = -j0 c = -j0.55 c = -j1

Achievable values as a function of Q under the constraint that 1 = wo LgCgs c = -j0 c = -j0.55 Minimum across all values of Q and 1 LgCgs
4 5 6 7

Note: curves meet if we approximate Q2+1 Q2

c = -j1

10
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Q
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Achieving Minimum Noise Factor

For common source amplifier without degeneration

- Minimum noise factor can only be achieved at -

resonance if gate noise is uncorrelated to drain noise (i.e., if c = 0) well see this next lecture We typically must operate slightly away from resonance in practice to achieve minimum noise factor since c will be nonzero

How do we determine the optimum source impedance to minimize noise figure in classical analysis?

- Next lecture!

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