UNIT-2

Gate Dielectrics

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2.1 Gate dielectrics

2.2 Poly-Si high-k dielectrics

2.3 Thermal matching

2.4 Effect of lattice mismatch in device fabrication

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Contents

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2.5 Challenges in MOSFETs for sub 15nm gate technology

2.6 3D interconnects

2.7 Photoresist technologies for the nanoscale

2.8 Metrology and defect inspection

2.9 Costing and yield

2.10 Assembly and packaging

2.1 Gate Dielectrics

A gate dielectric is a dielectric used between the gate and substrate of a field-effect transistor. Importance: Electrically clean interface to the substrate (low density of quantum states for electrons) High capacitance, to increase the FET transconductance High thickness, to avoid dielectric breakdown and leakage by quantum tunneling. Introduction: For silicon-substrate FETs, the gate dielectric is almost always silicon dioxide. The only dielectric material, other than silicon oxide, which can be made from Si letting the silicon nitridate was silicon nitride (Si3N4). It was known as a ceramic material which could be formed by reaction of silicon with nitrogen or ammonia at very high temperatures. The interface properties of oxidized silicon are superior to those of any other silicondielectric interface.

Combining the good characteristics of silicon nitride with those of oxidized silicon was possible by first oxidizing the silicon and depositing a nitride film on top of the oxide layer.

Common Dielectric Films and Dielectric constant

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2.1.1 Thermal silicon Oxide (SiO2)

2.1.2 Plasma Nitride Oxide (SiON)

1. 2. 3. Silicon oxynitride films have been used due to following reasons: Higher barrier properties to impurity penetration, such as Boron, Hot-carrier resistance,

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Radiation damage resistance, Improved high field electron channel mobility Dielectric constant modification Higher barrier properties to impurity penetration. Incorporation of nitrogen atoms in ultra-thin gate dielectrics with an equivalent oxide thickness (EOT) less than 3 nm is used to reduce gate leakage and boron diffusion from boron-doped pC poly-Si gate electrode to the channel region and to enhance reliability of MOS devices without sacrificing performance.

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 1. 2. 3.

2.1.2.1 Ammonium based oxynitrides: Annealing of silicon dioxide in NH3 usually results: A peak of nitrogen at the siliconsilicon oxynitride (SiSiON) interface, A small amount of nitrogen in the bulk and A nitrogen rich surface region. The nitrogen at the surface has been relate to the exchange of O and N atoms during nitridation.

Nitridation proceeds through the diffusion of a nitrogenous species towards the SiSiON interface

The formation of oxynitrides using NH3 also introduces hydrogen into the film, which generate dielectric reliability problems.

Post-nitridation anneals in O2 (reoxidation) have traditionally been the most popular and modify the film.

Increasing reoxidation temperature the hydrogen concentration decreases more rapidly. reduction of hydrogen is mainly due to a diffusion mechanism rather than chemical reaction.

2.1.2.2 Nitrous and Nitric Oxide-Based Oxynitrides:

The formation of silicon oxynitride using N2O and/or NO results in a build-up of interfacial nitrogen and bulk nitrogen throughout the film.

The nitrogen concentration and its distribution is very sensitive to process parameters such as:

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Temperature,

Time, Pressure, Processing variations (e.g., annealing of a preoxide or oxynitridation of silicon) Tool considerations (furnace or RTP, associated gas-phase kinetics and thermodynamics, etc.) The interfacial nitrogen concentration found in N2O nitrided oxides is typically less than NH3 and NO nitrided oxides.

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Product introduction by 2020, we focus on enhanced MOS transistors with gates 10 nm long.

1. Transition to metal gate

2. Transition to high-k (high-dielectric-constant) gate dielectric 3. Transition to fully depleted silicon-on-insulator (FD SOI) 4. Transition to multiple-gate (MuG) transistors

To scale SiON to below 1.0 nm with low leakage, it is necessary to increase the nitrogen concentration.

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bonding constraint theory suggests that Si3N4 cannot be directly substituted for SiO2 at the Si substrate.

The average number of bonds (Nav~3) represents a criteria for low defect. The average coordination at the SiSi3N4 interface has an over-constrained bonding configuration (Nav~3.5) with a significantly higher defect concentration. If ultra-thin SiO2 layer (~0.5 nm) is formed between the Si substrate and Si3N4, the average bonding coordination is reduced down to 3.0. The siliconsilicon dioxide interfaces leading to significantly improved electrical performance.
Bond Order or Average number of bonds=(number of bonding electron-number of antibonding electron)/2

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Why SiO2 Sub-1.0 nm SiON

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2.2 Poly-Si high-k dielectrics

The term high- dielectric refers to a material with a high dielectric constant (K) (as compared to silicon dioxide) used in semiconductor manufacturing processes which replaces the silicon dioxide gate dielectric. Si3N4 has a higher dielectric constant than SiO2. (around 6.5, dependent on the deposition conditions, compared to 3.9 for SiO2 4.2)

Metal-nitride-oxide-silicon composites have the advantage of an increased

capacitance value compared to metal-oxide-silicon structures with the same dielectric physical thickness..

Why High-k: The oxide film between the nitride and the silicon surface needed to have a thickness of at least about 100Angstrom (10 nm), to prevent a peculiar instability effect

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from occurring.

This effect was found to be due to tunneling of electrical charge between the silicon substrate and electron traps in the nitride, occurring when the electric field was high enough. The gate oxide in a MOSFET can be considered as a parallel plate capacitor.

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2.2.1 Why High-k

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where S is a capacitor plate area, d is a distance between capacitor plates (equal to capacitor oxide material thickness), k is a relative dielectric constant, and 0 is the electrical permittivity of vacuum. Using a material with high dielectric constant k would allow an increase of oxide thickness while avoiding the problem of oxide current leakage and maintaining the same capacitance per unit area required for a high density of MOSFET devices on the chip surface.

2.2.2 High-k Materials (for Gate dielectric)

Currently, the most promising high-k gate oxide materials are hafnium dioxide (HfO2), zirconium dioxide (ZrO2), alumina (Al2O3), hafnium silicate (HfSiO4), and zirconium silicate

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(ZrSiO4).

Above materials are thermodynamically stable in contact with Si.

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2.2.3 HfO2-Based High-k Dielectric Gate (Properties)

(Hafnium dioxide or hafnia)

The nitrided silicates specifically hafnium silicon oxynitride (HfSiON) are physically and electrically stable enough to be considered.

Because: Hafnium oxide (HfO2) has a dielectric constant ranging from about 18 to 22, and HfSiON has been reported to have a dielectric constant of up to 24.

Hafnium-based gate dielectric compounds also have high band offsets,

ECB1.5eV and EVB 3 eV that make them especially useful for MOS devices.\ HfO2 has many undesirable properties, such as low crystallization temperature. Low channel mobility. A high charge trap density

MOS devices using HfSiON gate dielectrics have shown the highest channel mobility

The aluminates also have high band offsets and might be better suited, if only the band offset and band gap were the critical parameters. However, it has been found that

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aluminum-based dielectrics have a lower crystallization temperature than the nitrided silicates, and reduced mobility as a result of aluminum diffusion into the channel

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Aluminates

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2.2.4 Deposition of Hafnium

Hafnium-based gate dielectrics have been deposited mostly by physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). PVD has been successfully used to perform the initial pioneering deposition of hafnium silicon oxide (HfSiO) and hafnium silicon oxynitride (HfSiON) Atomic layer deposition has been successfully used to deposit HfO2 using hafnium tetrachloride (HfCl4)

ALD has also been used to deposit HfSiO using metal organic precursors such as tetrakis ethylmethylamido silicon (TEMASi) and tetrakis ethylmethylamido hafnium (TEMAHf) and tetrakis methylamido silicon (TDMAS).

These precursors have been selected after significant investigations that were targeted at minimizing SiO2 interfacial growth during deposition

nitridation is necessary in order to reduce the leakage of SiO2 and to block boron. HfSiONs with more than a few percent nitrogen are produced by post-deposition processes using either ammonia or plasma nitridation.

2.2.5 Physical Properties of HfO2 and HfSiON

One of the key properties of SiO2 and SiON is their amorphous nature even after annealing at temperatures well above the conventional CMOS processing temperatures.

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Hafnium oxide (HfO2) and HfSiO, on the other hand have much lower crystallization temperatures.

Hafnium silicon oxide, crystallize at temperatures lower than the maximum CMOS processing temperature shows phase separation as it is annealed at these temperatures. addition of nitrogen to HfSiO to form HfSiON stabilizes the structure such that the material remains amorphous up to about 11008C Crystalline gate dielectrics, especially polycrystalline films will most likely have point defects and grain boundaries that are expected to place significant limitations on the reliability of the gate dielectric. As already mentioned above, the addition of nitrogen to HfSiO to form HfSiON stabilizes the structure such that the material remains amorphous up to about 11008C

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2.2.6 Electrical Properties

High-k gate dielectrics have demonstrated to have much lower gate leakage than SiO2 and SiON for the same thickness. HfSiON materials do not degrade the channel mobility for electron and holes. plasma nitridation tends to yield higher mobility and better nitrogen profile control in HfSiON.

high electron and hole mobilities of HfSiON with an EOT of about 0.8 nm.

Thermal expansion is the tendency of matter to change in volume in response to a change in temperature. When a substance is heated, its particles begin moving more and thus usually maintain a greater average separation. Silicon 2.6x10-6m. SiO2 5x10-7m. Si3N4 106m.

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2.3 Thermal Mismatch

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2.4 Effects of lattice mismatch in device fabrication

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2.5 Electronic Below 15nm (Challenges for sub 15nm gate technology)

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As the bulk MOSFETs enter the sub-100-nm range, their further scaling runs into several problems, including short-channel effects and gate oxide leakage.

The recent experimental demonstrations of several bulk transistors with gate length below 20 nm, performance of these prototypes is far from perfect.

Below 20 nm will require:

The use of advanced FETs, primarily double-gate MOSFETs with thin, undoped siliconon-insulator (SOI) channel connecting highly doped source and drain.

two gates allow a very effective control of the electrostatic potential of the channel

But the fabrication of double-gate transis- tors is certainly more complex than that of the usual bulk MOSFETs,

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Below 20 nm will require the use of advanced FETs, primarily double-gate MOSFETs with thin, undoped silicon-on-insulator (SOI) channel connecting highly doped source and drain. The main reasons in favor of this choice is as follows: Such device is a close approximation to what may be called the "ultimate MOSFET", because two gates allow a very effective control of the electrostatic potential of the channel, and hence the carrier transport. (Similar devices with single-gate [15, 16] loose to double-gate devices in scalability, though are certainly preferable to bulk MOSFETs.)

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Solution

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For relatively long devices (L = 10 nm) the characteristics are close to ideal: at positive gate voltage the current rapidly saturates at a level considerably larger than the industrial standard. As the gate length L is reduced below approximately 5 nm (channel length Lc, below 8 nm), transistor performance starts to degrade.

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2.6 3D Interconnects

a three-dimensional integrated circuit (3D IC, 3D-IC, or 3-D IC) is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit are interconnect with copper wires.

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2.7 Photoresist technologies for the nanoscale

A photoresist is a light-sensitive material used in several industrial processes, such as photolithography. Positive-tone photoresist systems are those, where the relief image formed at the wafer level is the same as the one in the mask. A positive resist is a type of photoresist in which the portion of the photoresist that is exposed to light becomes soluble to the photoresist developer. The portion of the photoresist that is unexposed remains insoluble to the photoresist developer. A negative resist is a type of photoresist in which the portion of the photoresist that is exposed to light becomes insoluble to the photoresist developer. The unexposed portion of the photoresist is dissolved by the photoresist developer. In negative-tone systems, the relief image is the complement or opposite of the mask or reticle Poly(methyl methacrylate) (PMMA), Poly(methyl glutarimide) (PMGI) Phenol formaldehyde resin (DNQ/Novolac), SU-8

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Photoresist technology, the processes whereby a mask pattern is transferred into another material.

The mask is in most cases a polymer resist which has been patterned by a lithographic technique, such as photons, charged particle beams, or nanoimprinting stamps.

The polymer nanopatterns have no other functions except serving as a mask in subsequent pattern transfer processes.

There are many ways of transferring a polymer resist pattern into a substrate

These processing techniques can be grouped into either additive processes or subtractive processes that is,

adding a new material through, or removing material from, the openings of polymer resist mask.

four most commonly used pattern transfer processes are:

(a) lift-off process by which another material is deposited through a resist pattern opening. (b) Additive process which adds a material by electroplating inside the resist pattern opening. (c) A subtractive process by which a thin film deposited on a substrate is patterned by etching through the resist mask opening (d) The resist pattern is transferred directly into a substrate by etching through the resist mask openings.

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Limitation at nanoscale
Ideally, a mask pattern should be faithfully transferred into another material without any distortions. When dealing with sub-100 nm pattern transfer, this is a difficult task, because each pattern transfer technique has its own capabilities and limitations. Some of the pattern transfer techniques are inherently not able to replicate the dimension of mask patterns.

We will discuss only those having the capability of transferring polymer resist patterns in sub-100 nm dimension.

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Methodology

The concept of patterning high-resolution metallic structures is obtain by using by lift-off process Sub-20 nm metal lines were made by the technique using patterned poly(methyl methacrylate)PMMA resis. Step 1 A polymer resist layer is patterned first by optical or e-beam lithography. Step 2 Metallic thin film is then deposited onto the patterned resist layer. Step 3 A wet chemical solution, normally acetone, dissolves the resist layer, which also lifts off the metallic thin film on top of the resist layer from the substrate Only the metallic film deposited through the resist pattern opening onto the substrate remains. The resolution capability of lift-off process is in principle the same as the resist patterning process, whether the patterning is done by optical lithography, e-beam lithography, or nanoimprinting lithography.

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2.7.1 Pattern transfer by lift-off

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2.7.1 Defects Inspection

Thin-film deposition point of view, the only limitation on the ultimate resolution of lift-off patterns is the grain size of deposited thin films. Acontinuous line pattern may be broken if the grain size is comparable to the linewidth.

2.7.2 Pattern Transfer by Plating

The additive pattern transfer process involves depositing thin films into the opening of a polymer resist mask. there are many different thin-film deposition techniques, not all of them are suitable for additive pattern transfer. A thin film can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), molecule beam epitaxy (MBE), oxidation, spin or spray coating and plating.

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2.7.3 Damascene Process

2.7.4 Pattern Transfer by Plating

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2.8 Yield Model

yield model has referred to the mathematical representation of the effect of randomly distributed defects on the percentage of the integrated circuits (or die) on a wafer that are good. Means that they pass all parametric and functional tests that are specified for the product.

The role of packaging in semiconductor electronic applications is to protect and preserve the performance of the semiconductor device from electrical, hygro-thermo-mechanical,

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and chemical corruption or impairment. The package may appear to be just a tiny black plastic box, gray stonelike slab, or a bright metal container that is used to hold the chip, Types of Packaging: The nonhermetic plastic package, also called plastic encapsulated microelectronics (PEM) especially in military circles, became mainstream products with the DIP that is still used today. The DIP that helped make packaging a high-volume low-cost. The fully hermetic package was first developed over a century ago and has served both the electronics and optoelectronics industries quite well.

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2.9 Packaging

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Protection: fully hermetic, vacuum-sealed enclosures since low gas pressure was essential to operation of the electronic and optoelectronic systems.

Chemical reactions will cause changes that are usually undesirable. Some metals will oxidize and corrode.

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Solid-state devices can undergo change in the presence of air gases, especially oxygen and water vapor.

Connectivity: (Electrical) The package provides the first-level (device to package) interconnect structure and must enable second-level (package to circuit board) electrical connections. Electronic devices require power, ground, and signal transmission paths. Metal packages require insulating or nonconductive seals. Glass and ceramic eyelets are used for metal packages and this requires high-temperature processing. (Radiant Energy) optoelectronic devices all require that their packages allow light either to enter, to exit, or both. Such devices include emitters, like light emitting diodes (LEDs), lasers, and various photodetectors including more sophisticated imaging devices, like chargecoupled devices (CCDs).

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2.9.1 Function of Packaging

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The traditional packaging technology that has supported device protection and performance requirements has involved such structures as the dual in-line package (DIP) and the quad flat package (QFP).

The DIP uses pins to connect the packaged chip to the electronic system and these pins are inserted into a printed circuit board (PCB) or socket during assembly.

The leads of the QFP, on the other hand, are solder mounted onto the surface of the PCB rather than being inserted into the board as is the DIP.

The commercial industry has moved towards the ball grid array (BGA) format to support higher lead count packages because QFP is not suitable for larger interconnects.

2.9.2 System in a package: 3D Packaging

Combining the attributes of BGA formats and expanding the concept vertically with multiple chips has spawned the more recent concept of system in a package (SIP). Multiple chips are assembled in a vertical mode, either in separate packages such as package on package assemblies or in terms of multiple stacked dies in a package. The advantages here are improved board space, integrated functionality in close proximity, possible add on technologies, improved time to market, and lower cost.

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2.9.3 Electronics Packaging Challenges

The need for better packaging design tools and processes can be most usefully discussed in terms of the needs of electronic systems for increased functionality, higher performance, and reliable behavior. These needs are discussed in terms of challenges that must be met.

2.9.3.1 Transition of Packaging Formats (Traditional Packages to Area Array Interconnect) (from DIP to QFP to BGA): The traditional packaging technology that has supported device protection and performance requirements has involved such structures as the dual in-line package (DIP) and the quad flat package (QFP). the chip is electrically connected to the package via wire bonding. The DIP uses pins to connect the packaged chip to the electronic system and these pins are inserted into a printed circuit board (PCB) or socket during assembly. The leads of the QFP, on the other hand, are solder mounted onto the surface of the PCB rather than being inserted into the board as is the DIP. At about 250 leads, however, the increasing difficulty in manufacturing the QFP format The commercial industry has moved towards the ball grid array (BGA) format to support higher lead count packages. This format tends to be limited by the peripheral chip pads, because of increment in transistors, chip complexity increases. So we use Area array interconnect.

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DIP

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2.9.3.2 System in a package: Combining the attributes of BGA formats and expanding the concept vertically with multiple chips has spawned the more recent concept of system in a package (SIP).

Multiple chips are assembled in a vertical mode, either in separate packages such as package on package assemblies or in terms of multiple stacked dies in a package.

2.9.3.3 The Challenge of Interconnect and Mechanical Reliability: The transistor density (millions of transistors/square cm) increases from 174 in 2005 to interconnects increases.

876 in 2012. These transistors must be supported with power, ground, and signal I/O. so

2.9.3.3.1 Chip-Level Interconnect Modifications: materials have migrated from the historic Al/SiO2 to Cu/low-k for the conductor and ILD materials.

The new ILDs are made of low dielectric constant (2.03.0) material.

Many of these materials have low mechanical strength and low thermal conductivity compared to SiO2 as the ILD (have minimum capacitive between metals).

The on-wafer interconnect comprises multiple lines of ultra-fine metal interconnect embedded in the low-k dielectric.

These structures support little strain and can become a significant reliability risk.

2.9.3.3.2 Underfill Polymers in Flip-Chip Processing: The coefficient of thermal expansion (CTE) of silicon is about 2.6 ppm/8C, and that of the glass fiber reinforced printed wiring board (PWB) is about 17 ppm/8C. The BGA substrate is the intermediary between the silicon and the PCB with a CTE of 6 ppm/8C for ceramic BGA, CBGA and 17 ppm/8C for organic BGA. The large CTE difference between CBGA and organic PWB limits the CBGA body size to about 32 mm. On the other hand, the large CTE difference between plastic BGA (PBGA) and the silicon chip puts a significant shear stress on the flip chip interconnect and almost any commercial application is impractical without the use of underfill.

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Underfill encapsulation between the front-side of the chip and the top side of the PBGA substrate distributes the stress over the entire chip surface, and so reduces the stress on the flip chip solder joints. The impact of this CTE mismatch is that the entire assembly flexes during thermal cycling to distribute stress away from the solder balls.

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It is important that the underfill material has good mechanical integrity and interfacial adhesion to both the chip and the substrate surfaces and the vertical direction CTE of the underfill is compatible with that of the solder joints. The cost associated with the dispensing of the underfill into the thin gap between the chip and the substrate and the curing time are other challenges. Note that as the gap is reduced there will be some height of this gap where conventional underfills will be very difficult to inject between the chip and the substrate.

2.9.3.4 The Challenge of Thermal Management: The high performance chips that will dissipate a heat load approaching 200 W in 2012, will require more actively managed thermal systems than those used commercially today.

Fluid flow heat exchangers can support very large loads. diamond heat spreaders and diamond micro-channel heat exchangers can be used to support thermal loads, an order of larger magnitude 2.9.4.1 Heat-Sink Attachment for Large and High Power Chips: the CTE difference between the chip and the PBGA substrate will cause both to bend when the encapsulated chip/package entity is cooled from the curing temperature to room temperature. The use of thermal adhesive in attaching a rigid heat sink to the backside of the chip will prevent the bending of the chip, and the shear stress to the solder joint and encapsulant may remain excessively large.

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2.9.3.4 Electrical Parameter (Resistance): Resistance represents the property of a conductor to exhibit a voltage drop between its terminals when a current is flowing. This is due to the dissipation of energy in the form of heat within the conductor.\

The value of the voltage drop can be calculated from Ohms law as V=IR. The resistance of a conductor will depend on the material (Resistivity) For dc conditions the resistance, R is calculated as R= l/A, where (resistivity), l (length); and A (area) of cross section.

Resistivity varies significantly between package types. Plastic packages may use copper conductors (=1.67 -cm) or Alloy42 as a conductor material (=38.8 -cm). Co-fired may have an effective resistivity of 25 -cm.

ceramic packages may use tungsten/glass composite materials for conductor traces, which

Current technology uses small devices so small contamination can affect chip functionality So risk analysis is needed before its packaging is known as Yield model. The term yield model has referred to the mathematical representation of the effect of randomly distributed defects on the percentage of the integrated circuits (or die) on a wafer that are good. A complete and much more useful yield model will also account for systematic yield losses. Systematic yield losses can result from process, design or test problems. The mathematical representations are typically derived from statistical distribution functions, such as the Poisson distribution or the BoseEinstein statistics. The total yield for a given product can be expressed as the product of the systematic yield and the random yield Y=YsxYr above equation used to calculate the yield limits due to various types of random defects that arise from different manufacturing process steps or process equipment. The random yield limits (or, yield losses) into components that are due to different types. Ys is often estimated, or it can be calculated by performing cluster analysis,. A complete yield model partitions the term Ys into its sub-components to create yield improvement.

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Yield Model (device test)

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Characteristics of yield models:

1. It must account for all sources of yield loss, both random and systematic. 2. The total modeled or calculated yield should agree well with the actual yield. 3. It should ideally give insight into possible causes of the yield loss. 4. It should be able to partition and quantify yield losses resulting from design, process, test, and random defects. 5. It should provide the basic methods for automated yield analysis tools. Yield modeling have advantageous because: loss.

1. It makes possible the use of existing process and test data to quantify all sources of yield 2. It can substantially improve the yield learning rate for new products.

3. It makes accurate yield forecasting possible, which aids in planning. 4. It helps to set product specifications that match process capability.

5. It can provide the primary algorithms needed to create automated yield analysis programs.

Cluster analysis or window analysis, introduced by Seeds.

This analysis is performed using actual wafer probe bin maps for finished wafers. The die are partitioned into groups or blocks of 1, 2, 3, 4(2x2), 6(3x2), 9(3x3), etc. A simple example with groupings of 1x1, 1x2, 2x2, and 2x3 is shown Cluster analysis or window analysis, introduced by Seeds. This analysis is performed using actual wafer probe bin maps for finished wafers. The die are partitioned into groups or blocks of 1, 2, 3, 4(2x2), 6(3x2), 9(3x3), etc. A simple example with groupings of 1x1, 1x2, 2x2, and 2x3 is shown The block is only considered to be a yielding block if all die within the block passed wafer probe testing

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Cluster Analysis

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Yield %: For example, if there are 600 possible candidates on the wafer, and 480 tested good, the yield of the 1x1 block is simply 480/600=80%. For the 1x2 blocks, the total possible candidates would be 300, and if 216 of these had both die pass wafer probe, the yield is 216/300=72%. The 2x2 blocks, for example, have 150 total

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candidates, and if 90 of the blocks contain all four dice that tested good, the yield is 90/150=60%. the above block yield calculations are performed on a relatively large number (~100 500 if possible)

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Random-Defect Yield Models: If the wafer has a given number of fatal defects that are spread randomly over the wafer area, then the average number per chip would be Ax D0, where A is the chip area and D0 is the total number divided by the total wafer area.

If the defects are completely random in their spatial distribution, the probability of finding a given number (k) of defects:

Where

The yield is then defined as the probability of a die having zero defects (k=0), so:

This is the Poisson yield model.

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Inter Level Dielectric; same as Inter Layer Dielectric and IMD, dielectric material used to electrically separate closely spaced interconnect lines arranged in several levels (multilevel metallization) in an advanced integrated circuit; ILD must feature low dielectric constant k (as close to 1 as possible) to minimize capacitive coupling ("cross talk") between adjacent metal lines.

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