International Conference on Intelligent Information Systems and Management (IISM2010), June10-12, 2010

Multi VDD Technique for Power Optimized High Performance Multipliers in MAC Unit
G.Sathiyabama and J. Raja
AbstractAn efficient design for obtaining low power array multiplier is proposed for the multiplier accumulatorMAC unit. The design uses two different supply voltages for full-adder units of multiplier. One full-adder unit uses a higher voltage supply (1.8V) and the other uses lower voltage (1V). While the 1.8V full-adder units are exclusively used in the most critical path of the multiplier, the 1V units are used in regions where the timing is not critical. This reduces power consumption and guarantees the best overall performance of the multiplier. To ensure that the performance of the multiplier is maintained, the slower 1V full-adder units are systematically replaced by the faster 1.8V full-adders in the violating paths to bring the timing to be within limit. Our technique is simulated using HSPICE with MOSFET model of level 3 at 0.25m & 90nm Technology and is aimed at achieving optimized power consumption on large multiplier design. IndexTermsDynamic Power, Low Power CMOS Circuits MAC Unit, Power Delay Product In this paper, a low power array multiplier design approach based on two different supply voltages is proposed. Much attention is devoted to power minimization of one-bit full-adder which is fundamental to all multipliers [3]. An effective way to simultaneously retain the performance and to reduce the power consumption is the multi supply voltage technique. The technique nevertheless has not been fully investigated to be used in designing repetitive structure such as multiplier. This paper is organized as follows: the architecture of MAC unit is described in the section II, proposed multi supply voltage technique for multiplier is presented in the section III, simulation results and discussion are in the section IV and finally conclusion is given in the section V. II. ARCHITECTURE OF THE MAC UNIT For real time digital processing, a high speed high throughput multiplier accumulator (MAC) is the key requirement of the DSP system. One of the most operation of MAC unit is array multiplication. This operation is performed by multiplier and adders. Multipliers are complex adder arrays whose function is to accumulate partial products each of which results from the logical AND between multiplicand and multiplier bit. A. Multiplier Multiplier circuit is based on add and shift algorithm. Each partial product is generated by the multiplication of the multiplicand with one multiplier bit. The partial product are shifted according to their bit orders and then added. Different kinds of multipliers are available such as array multiplier, carry save multipliers, tree multipliers etc. A faster way to implement multiplication is to resort to an approach similar to manually computing a multiplication. All partial products are generated at the same time and organized in an array. A multi operand addition is applied to compute the final product. This set of operations can be mapped directly into hardware .The resulting structure is called an array multiplier. It combines the three functions: Partial product generation, Partial product accumulation, and final addition. There is a oneto-one topological correspondence between this hardware and manual multiplication .The shifting of partial products for their proper alignment is performed by simple routing and does not require any logic. The overall structure can easily be compacted into a rectangle, resulting in a very efficient layout. Array multiplier is well known due to its regular structure.

I. INTRODUCTION

N real life embedded devices like mobile phone, notebook computers are made use of RISC processor and DSP. Mostly the digital processing requires high speed and low power multiplier accumulator (MAC) unit. The multiplication is the important operation in this unit. Specifically, speed and power efficient implementations of a multiplier are a very challenging problem. With the increase in complexity of VLSI systems and limited amount of power available in certain scenarios like cell phones and digital cameras, minimizing power consumption has clearly become a priority. Lowering power consumption not only increases reliability, but also leads to savings in package costs due to reduced heat dissipation. The main contributor to overall power dissipation in CMOS VLSI circuits is dynamic power consumption which accounts for up to 80% of the total power [1]. Dynamic power dissipation results from charging and discharging of the wire and transistor capacitive loads. The dynamic power dissipation of a CMOS circuit can be described by [2]. 2 PSWITCHING = is the switching . CL. V DD f CLK , where activity CL is the total load capacitance, VDD is the supply voltage and fCLK is the operating clock frequency. Consequently power reduction can be achieved by decreasing one of the factors of the formula. The most popular choice is to lower VDD because of its quadratic relationship with power.
G. Sathiyabama is a student of VLSI Design in Sathyabama University, Chennai, Tamilnadu, India Dr. J. Raja is with the Department of Electronics and Communication Engineering in Anna University, Tiruchirapalli, Tamil Nadu, India Digital Object Identifier No: IISM00620100001

ISBN-978-1-4507-2041-0 by CiiT 2010 Published by Coimbatore Institute of Information Technology

International Conference on Intelligent Information Systems and Management (IISM2010), June10-12, 2010

Fig. 1. Architecture of array Multiplier, darkened cells indicate the adder units which lie in the critical paths [2]

Fig.1. shows the structure of array multiplier. These arrangements, however, yield multiple critical paths, all of which are of the same length. It turns out that majority of the adder units in the array (darkened cells in the figures) lie in the critical paths. The power consumption in the critical path of the whole circuit has to be reduced. The total delay of the array multiplier can be minimized by optimizing the critical path delay and transistor sizing. B. Full-Adder The basic building block of the multiplier is the one-bit fulladder [3]. The output function of the adder can be described by the following Boolean expression

Fig. 2.a Transistor schematics of the proposed Full Adder

(1) Where H = A B is the half adder. This implementation saves the resource by sharing the repetitive XOR gate. Fig. 2.a. shows the transistor schematics of the proposed Full-Adder unit based on the above equations. In this circuit width of the MOS transistors are varied to obtain better performance. The Fig 2.b shows the inputs, sum and carry waveforms of the proposed full adder. The Fig 2.c shows the layout view for low power full adder circuit.

Fig 2.b. Input and output waveforms of the full adder at vdd = 1.8v

ISBN-978-1-4507-2041-0 by CiiT 2010 Published by Coimbatore Institute of Information Technology

International Conference on Intelligent Information Systems and Management (IISM2010), June10-12, 2010

Fig. 3. Basic level converter

Fig 2.c. Layout view of the full adder

III. MULTI VDD SUPPLY TECHNIQUE FOR MULTIPLIER DESIGN We propose the low-power array multiplier employing dual supply voltage technique. The array multiplier designed using our approach can achieve the same delay performance as the multiplier designed using higher supply voltage but with significant decrease in power consumption. First, construct the array multiplier using only the higher supply voltage (1.8V) proposed full adder units as shown in Fig, 4. Identify critical paths and mark all adder units lying in the paths. Replace every unmarked adder unit with lower supply voltage (1V) adder unit. Recheck the critical paths. If critical paths do not change, then stop otherwise consider the new critical paths. Note that these new paths may be a mixture of both types of adder units. For each critical path, locate the lower supply voltage adder unit lying adjacent to a chain of higher supply voltage adder units. Replace it with a higher supply voltage adder unit. Insert level converters where necessary and remove those no longer needed. Find the critical paths. Repeat these procedure until minimum power consumption is achieved.

The proposed circuit has a good performance that the worst delay for sum and carry are almost equal, which is given in Table. I. It should be noted that, in our design, our inverters are intentionally inserted at the outputs to provide the necessary drive for the next adder stage and to solve the voltage problem caused by the transistor cascading effect.
TABLE I PERFORMANCE OF PROPOSED ADDER AT 1GHZ

Performance Power Sum worst delay Carry worst delay

At vdd =1.8 9.42 w 3ps 2ps

At vdd =1.0 2.83 w 12ps 10ps

C. Level Converter
Level converters are required whenever a module at lower supply voltage has to drive a gate at the higher voltage. In such a case, the PMOS transistor in the driven gate is never turned off, resulting in static current and reduced output swing. The problems can be prevented by applying level conversion at these interfaces. Low-to-high level shifters are required to convert signals from low-VDD to high-VDD and prevent short circuit current in the device at high VDD due to partial turn-off of the PMOS transistors. A multi-VDD approach is presented in [4] whereby gates off the critical path are allowed to operate at low VDD (VDDL) and gates on the critical path operate at high VDD (VDDH). This methodology allows a significant power reduction without compromising the performance of the circuit. The Fig.3 shows a basic asynchronous converter based on positive feedback [5] which is used in multiplier design. The effect of level converters on the overall performance of the multiplier is minimal since the conversions are required only at the transitions from lower to higher supply voltage units.

Fig . 4. Logic diagram of a 4-bir array multiplier

This methodology guarantees that higher supply voltage adder units are used only where necessary. For the most critical path, all adder units that belong to the path are kept operating at higher supply voltage. The purpose is not to deteriorate the overall delay performance of the multiplier. The less critical path contains both types of adders but will have enough
ISBN-978-1-4507-2041-0 by CiiT 2010 Published by Coimbatore Institute of Information Technology 3

International Conference on Intelligent Information Systems and Management (IISM2010), June10-12, 2010 number of higher supply voltage units in the path to maintain the timing constraint. The rest of the adder units in the multiplier which is non-critical are designated to operate in lower supply voltage in order to reduce power consumption. It is noted however, that each iteration step does require a significant amount of time to identify the right critical paths in the multiplier. IV. SIMULATIONS AND DISCUSION In this section, we have designed 4x4 multiplier with and without level converter, which is simulated in HSPICE with level 3, 0.25 micrometer and 90nm technology. The Table .II shows the power performance component of array multiplier without level converter and with level converter. First simulation of array multiplier is carried out at vdd =1.8v supply as well as vdd=1.0v alone using level 3 parameters. Then it is processed with 1.8v & 1.0v dual supply voltage for the adders using level converter at 0.25m TSMC technology. Then the measured power is compared with that of the multiplier which is simulated with high voltage (1.8v) alone. It shows 20% power saving in the 1.8& 1.0 dual voltage technique. The same process is done for 90nm technology at same model level 3. Fig.5. shows the output waveform of bit 0 and bit 4 of the multiplier. V. CONCLUSION In this paper, we have designed optimized full adder at different level of voltages (1.8V and 1.0 V) and new optimized array multiplier has been proposed with use of this full adder which is used for MAC unit of DSP processor. The multi voltage technique is introduced for minimizing power in array multiplier. In this method, high voltage is kept in adder units which are in critical path. The non-critical path of the multiplier is then replaced with the adder units at low supply voltage to save the overall power consumption. All paths are to be checked with these high and low voltage levels. All designs are simulated using HSPICE in CMOS 0.25m and 90nm technology process. The proposed multi Vdd technique multiplier has better power efficiency when compared with single Vdd multiplier. REFERENCES
[1] [2] [3] D. Soudris, C. Piguet and C. Goutis (eds) , Designing CMOS Circuits for Low Power, Kluwer academic publishers J. Rabaey, Digital Integrated Circuits: A Design Perspective, 2nd ed, Prentice-Hall,2003. C. Wey, C.H. Huang and H.C. Chow, A New Low-Voltage CMOS 1Bit Full Adder for High Performance Applications, IEEE, pp. 21- 24, 2002. Usami and M. Horowitz, Clustered voltage scaling technique for lowpower design, In Proceedings ISPLD, pp38, April 1995. Usami and M. Igarashi, Low-Power Design Methodology and Applications utilizing Dual Supply Voltages, IEEE, 2000 Pedram, Power Minimization in IC Design, ACM Transactions on Design Automation of Electronic Systems, Vol. 1, No. 1, pp. 3-56, January 1996.

[4] [5] [6]

Ms.G.Sathiyabama received her B.E. degree in Electronics and Communication Engineering from Madurai Kamaraj University, Tamil Nadu, India and M.E. degree from Anna University, Chennai, India. Currently she is doing her Research in the area of Low power VLSI Design in Sathyabama University, Chennai. Her research interests include Low power circuit design, Microprocessor, Embedded system Design and Digital Signal processing. Dr. J. Raja obtained his Batchelors degree in the area of Electronics and Communication Engineering and did his Masters in Control and Instrumentation in the year 1988 and Jan 1992, respectively. He pursued his research in the area of ATM networks. He proposed modification in the ATM switching architectures by employing coding techniques as part of his Ph.D. thesis and obtained his Ph.D. degree in the year 2003. He has around 20 years of teaching experience. He has taught the courses like Digital Communication Techniques, High Speed Communication Networks, and Communication Switching Systems at both under graduate and post graduate level. Currently he is heading the department of Electronics and Communication Engineering, Anna University Tiruchirapalli, Tiruchirapalli. He has published many papers in national and international journals and conferences.

Fig.5.Output waveform of the multiplier-bit 0 & bit 4

TABLE II PERFORMANCE OF 4 BIT ARRAY MULTIPLIER

Technology 0.25 m 90nm

Power Single supply(1.8v) 33.7mw 9.17mw

Dual supply (1.8 & 1.0v) 23.06mw 7.36mw

ISBN-978-1-4507-2041-0 by CiiT 2010 Published by Coimbatore Institute of Information Technology