International Conference on Electrical, Electronics and Civil Engineering (ICEECE'2011) Pattaya Dec.

2011

Transmitter Implementation Using DS-CDMA Technique in FPGA Using Verilog HDL

Tasneem S. Mahbub, Salsabil. Ahmed, and Iqbalur R. Rokon

Abstract- The DS-CDMA is expected to be the major medium access technology in the future mobile systems owing to its potential capacity enhancement and the robustness against noise. DS-CDMA is a type of spread-spectrum communication system in which multiple signal channels occupy the same frequency band, being distinguished by the use of different spreading codes. Implementation of DSCDMA transmitter using Field Programmable Gate Array (FPGA) has been proposed in this paper. It describes the design for pseudo random PN coding and a direct sequence principle based wireless transmitter. The circuit for the transmitter is comprised of basic digital components, such as flip-flops, shift registers, PN coder and a BPSK modulator. Verilog Hardware Description Language (HDL) was used for coding of the design. ModelSim Altera Edition 6.5b was used for functional simulation and logic verification. The Xilinx Synthesis Technology (XST) 12.3 of Xilinx ISE tool was used for synthesis of the transmitter. Keywords - DS-CDMA, transmitter, FPGA, Verilog. I. INTRODUCTION

OBILE communications are rapidly becoming more and more necessary for everyday activities. With so many more users to accommodate, more efficient use of bandwidth is a priority among cellular phone system operators. Another very important objective in designing a communication system is security. This is very essential in military communication. In fact, the need for high security in military communication led to the development of a modulation system known as Spread Spectrum Modulation during Second World War [5]. DS-CDMA is a type of spread-spectrum communication system in which multiple signal channels occupy the same frequency band, being distinguished by the use of different spreading codes [3]. CDMA communication is employed in, for example, digital cellular telephone systems and personal communication services.

In these systems, a base station communicates with a plurality of mobile stations, one frequency band being used for all of the up-links from the mobile stations to the base station, and another frequency band being used for all of the downlinks from the base station to the mobile stations [4].The idea is to transmit signals simultaneously through a linear band limited channel without inter channel or inter symbol interference [5]. FPGA implementation of DS-CDMA transmitter has been proposed in this paper. The research involved two phases simulation and synthesis of the Verilog codes. ModelSim Altera Edition 6.5b was used for functional simulation and logic verification at each block level and system level. The Xilinx Synthesis Technology (XST) of Xilinx ISE 12.3 tool was used for synthesis of the transmitter and simulates a design's reaction to different stimuli. Cellular technology has grown tremendously both in terms of traffic and services, the need for data high speed data transmission has increased The mobile telecommunication industry faces the problem providing technology that be able to support a variety of services ranging from voice communication with a bit rate of few Kbps to wireless multimedia in which bit rate up to 2 Mbps. This tremendous growth has also been fuelled by the recent improvements in the capacity of wireless links due to the use of multiple access techniques. The idea is to transmit signals simultaneously through a linear band limited channel without inter channel or inter symbol interference [5].

Tasneem S. Mahbub is with the North South University , Bashundhara R/A, Dhaka-1229, Bangladesh as a student of Electronics and Electrical Computer Science Department (corresponding author to provide phone: 01717325791 ; e-mail: tma667@gmail.com ). Salsabil Ahmed, is with the North South University, Bashundhara R/A, Dhaka-1229,Bangladesh as a student of Electronics and Electrical Computer Science Department (corresponding author to provide phone: 01713049727 ; e-mail: badhon_sahmed@ hotmail.com ). Iqbalur R. Rokon is with the North South University, Bashundhara R/A, Dhaka-1229, Bangladesh as a faculty member (corresponding author to provide phone: 01726246189; e-mail: irahman@northsouth.edu).

II. DESIGN OF CDMA TRANSMITTER In this paper, CDMA communication system is implemented with Maximum Length (ML) sequence PN code. The following specifications are considered for design and implementation of the CDMA transmitter and receiver. In this project two CDMA communication systems are implemented, one with Maximum Length (ML) sequence PN code and other with gold code. In the PN sequence generator section both the ML sequence and gold code generators are described. The following specifications are considered for design and implementation of the CDMA transmitter: (1)Type of PN sequence: ML code (2) PN sequence length: 64 in case of ML sequence
204

International Conference on Electrical, Electronics and Civil Engineering (ICEECE'2011) Pattaya Dec. 2011

(3) Type of modulation: BPS (4) Front end design entry: Verilog HDL (5) Backend synthesis: Xilinx Spartan 3E FPGA
The Following tools are used while developing, testing, implementing and programming the CDMA transmitter blocks:

A.

Simulation - Modelsim Altera 6.5b

B. Synthesis - Xilinx Synthesis Technology (XST) 12.3 of Xilinx ISE

Fig 1: Block diagram of CDMA transmitter

magnitude faster than a gate level description [4]. A Verilog HDL specification for a part can form the basis for a simulation model to model to verify the operation of the part in the wider system. Behavioral simulation can reduce design time by allowing design problems to detect early on, avoiding the need to rework designs at gate level. Behavioral simulation also permits design optimization by exploiting alternative architectures, resulting better design. Verilog HDL permits technology independent design through support for top down design and logic synthesis [6]. A Verilog HDL design begins with a block Module that describes the interface and function for the design. The interface defines the input and output logic signals of the circuit. The function states the internal operation of the design. Within these blocks, there are numerous other functional blocks used to build the design elements of the logic circuit created [1], [8]. The source code can be written using the normal TEXT editor, then saved as a Verilog HDL file with .v extension and transferred to any of the Verilog HDL design compilers (DC). If the compilation shows no error(s), the file can be simulated, synthesized and implemented with FPGA. The transmitter components were designed individually using the bottom-up approach. The designs were then combined and defined by a component declaration and port mapping. Generally, this is an easy method although it could have had complications [1]. V. DESIGN DESCRIPTION
TABLE I VARIABLES FOR LFSR DESIGN

The main blocks of CDMA transmitter are listed: PN sequence generator Multiplexer Shift Register Parity BPSK Modulator III. VERILOG IMPLEMENTATION The FPGA / Verilog HDL combination is a powerful tool for realizing sophisticated communications and cost effective design schemes. FPGA is chosen to realize CDMA transmitter because they can implement a wide range of logic gates such as up to millions of gates [1]. Traditional gate arrays contain a number of building blocks or primitive cell [9]. The FPGAs have similar structure to gate arrays however they have programmable elements. The programmable cell is called Logic Element (LE) in case of alter device and Configurable Logic Block (CLB) in Xilinx devices. Verilog HDL is hardware description language, common language for designers. This is the high level language and simulation, synthesis tools are available. It supports for versatile design reconfiguration and multiple level of abstraction.
IV. SOFTWARE OVERVIEW A Verilog HDL specification can be executed in order to achieve high level satisfaction in its correctness before commencing design and may simulate one to two orders of

Variable Number of stages in the shift register, n. Number of taps in the feedback path. Position of each tap (polynomial representation) 17 4

Set Value

f(x) = x17+x9 + x5 +x4+1

In the spread spectrum based multi user systems unique codes are to be assigned to different users to differentiate them. For the identification of unique user, the code must undergo some operations, so the data may not be diverted to wrong user. Autocorrelation is the procedure by which matching of one signal is done with the same signal. Good autocorrelation properties are required for reliable synchronization and reliable separation on the multipath components. The polynomial f(x) = x17+x9+ x5 +x4+1 was chosen because it gives good autocorrelation [5]. The polynomial could have taken in any form, as long as it gives good cross correlation. Cross correlation is defined as the correlation between two different signals [7].

205

International Conference on Electrical, Electronics and Civil Engineering (ICEECE'2011) Pattaya Dec. 2011

It is important to use a set of PN sequences with minimal cross correlation with each other in order to reduce the effect of adjacent channel interference. If the cross correlation is not small, there is a possibility that the data coded from one user can be incorrectly identified and assigned to another because of similarity between the two keys. When data is ready at the input of the pn generator, every bit of the data is available and waiting for the data to enter. After entering, Data is multiplied with the pn code. Shift enables controls the data enter and shifting it out from the pn generator. The coded data is shifted serially to the pn generator output bit by bit. The Shift enable switch the pn generator on until the coded data were shifted out of the pn generator. The coded data is delayed for 2-clock cycle at the PN generator after shifting the data is stored in the buffer during this time. VI. HARDWARE IMPLEMENTATION REQUIREMENTS
From the synthesis report we have got from our project, we came to the decision that this project can be implemented with Spartan 3 E FPGA.

Fig 3: Schematic Diagram of the whole design

SCHEMATIC DIAGRAMS AFTER SYNTHESIS

Fig 4: Diagram of the simulation of the whole design (with all inputs & outputs)

Fig 2: Top level view (with all inputs & outputs) of the design

We tried different cases to fully justify the objective and to complete the verification in total. We attempted different possibilities: Different bit stream of select signal and fill select signal Data input verification Display wrong answer if anything is different from desired outcome Thus, after all the different procedures, we came to a conclusion that our design for CDMA transmitter using Verilog HDL works properly. Implementation of a CDMA communication system with DS technique in Verilog has the following advantages: The design is fully reconfigurable. The number of bits and PN sequence can be changed very easily. Useful for both FPGA and ASIC implementations.

VII. CONCLUSION Verilog has become the linchpin for a complete design flow from concept to digital component.It is a language which allows switch-level modelling which some designers find useful for exploring new circuits. Moreover, a designer can describe a component in text rather than as a schematic in verilog. In this project, the transmitter was implemented on FPGA. This has been tested using an arbitrary chosen data stream, where these data have been transmitted through implemented transmitter. Increasing the number of bits using the same topology, it is possible to reach the standard rates specified for CDMA.

VIII. FUTURE SCOPE

The concept can be extended to design the GPS system which is CDMA system with 1023 chip length technique.
206

International Conference on Electrical, Electronics and Civil Engineering (ICEECE'2011) Pattaya Dec. 2011

FHSS technique can also be implemented and compared.

REFERENCES
[1] [2] [3] Palnitkar, Samir, Verilog HDL, ISBN 81-7758-918-0, Prentice Hall, March, 2003 Cooper, G.R., and Mcgillem, C.D., Modern Communications and Spread Spectrum, Mcgraw Hill, New York, 1986 Jakes, W. C., Jr. (1994), Microwave Mobile Communications, J. Wiley & Sons,New York,1974; reprinted by IEEE Press, 1994, ISBN 0-78031069-1. Zwolinski, M. (2000), Digital System Design with VHDL, Pearson Education Ltd., England. J. G. Proakis, Digital Communications, McGraw-Hill, Inc., 1995.

[4] [5]

Verilog Hardware Description Language Reference, Manual, Version 2.09, Los Gatos, CA, Open Verilog International, March 1993. [7] Mohammed K.E., Ali Borhanuddin mohd, Digital Design of DSCDMA Transmitter Using VHDL and FPGA, IEEE Communication Journal. [8] CDMA Technology Resources: Welcome to the world of CDMA: Common air interface 2003 CDMA Development group http://www.cdg.org/technology/index.asp). [9] Mark G. Arnold, Verilog Digital Computer Design: Algorithms into Hardware, PTR Prentice Hall, Upper Saddle River, NJ, 1999, p. 115 [10] F. Lima, L. Carro, R. Reis, Reducing Pin and Area Overhead in FaultTolerant FPGA-based Designs, FPGA03, 33-25 February, Monterey, CA, USA [11] Digital down converter/despreader for direct sequence spread spectrum CDMA communications system. http://www.patentstorm.us/patents/61413 72-description.html

[6]

207