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Direct memory access (DMA)

In many I/O interfacing applications and certainly in data acquisition systems, it is often necessary to transfer data to or from an interface at data rates higher than those possible using simple programmed I/O loops. Microprocessor controlled data transfers within the PC (using the IN (port) and OUT (port) instructions) require a significant amount of CPU time and are performed at a significantly reduced data rate. Further to this, the CPU cannot perform any other processing during program controlled I/O operations. While the use of interrupts might allow the CPU to perform some concurrent tasks, certain applications exist where the amount of data to be transferred and the data rate required is too high. Two such applications are as follows: Transferring screen information to the video card adapter on board memory Transferring data from a remote I/O device (data acquisition board) to the PCs memory Direct memory access (DMA) facilitates the maximum data transfer rate and microprocessor concurrence. Unlike programmed or interrupt controlled I/O, where data is transferred via the microprocessor and its internal registers, DMA (as its name implies) transfers data directly between an I/O device and memory (memory to memory DMA transfers are also possible). Whichever CPU is being used, it must have a DMA feature to determine when DMA is required, so that it can relinquish control of the address and data buses, as well as the control lines required to read and write to memory. In addition, the CPU must inform the I/O device that requires the DMA data transfer when it again requires control of the address and data buses and I/O control lines. Further to this, a separate DMA controller is required to actually perform the DMA I/O operations.

DMA controllers In the PC/XT a single Intel 8237-5 DMA controller, with four channels (Ch0Ch3), was used. The PC/AT has two DMA controller chips, cascaded together in a similar manner to the 8259A PIC. The supplementary DMA channels (Ch5Ch7) are 16-bit channels.

The 8237-5 DMA controller contains: A two-byte address register containing the starting memory address from which data must be read. A two-byte address register containing the current address to which data must be written. A two-byte count register, which holds the number of bytes/words to be written in total. A two-byte count register containing the current bytes/word count of each channel. Control lines that allow the reading/writing of data from/to memory. As each device only supports 16-bit addresses (limiting access to 64 kB of memory), each DMA channel has an associated page register in system I/O memory to provide the added upper 4 address lines required to address the complete 20-bit (1 MB) system base address space. Initialization required for DMA control Before any DMA operation can occur, the DMA controller must be initialized. Items requiring initialization are as follows: Select whether the DMA controller will read or write to memory. Configure the type of DMA data transfer. Four modes of DMA data transfer are available: Single transfer mode The DRQx signal must be asserted for every byte/word transferred. Block transfer mode A single DRQx signal DMA request initiates the transfer of an entire block of data. Demand transfer mode Data is transferred as long as the DRQx signal DMA request is asserted and the terminal count has not been reached. Cascade mode All DMA channels are programmed for single transfer mode. The total number of bytes to be transferred is loaded into the appropriate total byte/word count register. The current byte/word count register is then automatically initialized. The memory address to which the first data byte will be read/written is loaded into the start memory address register. The current memory address register is automatically initialized. The 4-bit page register corresponding to the upper four bits of the 20-bit address is written using the I/O port addresses of the PC. The DMA channel priorities should be set. When the PC is booted up, the ROM BIOS sets the priorities so that the lowest numbered channel has the highest priority. The DMA controller(s) channels that are to be used should be enabled. Channels to be enabled have the channel mask register bits cleared. I/O devices requesting DMA Assuming that the necessary DMA controller has been initialized, the standard operation, when an I/O device requests DMA data transfer on one of the channels of the DMA controller, is as follows: An I/O device requests a DMA transfer on a specified channel by asserting its DRQx (DMA request) signal from low to high. The requesting device must hold its DRQx line high until the DMA controller responds by asserting the corresponding /DAK line. The DMA request is prioritized by the 8237 DMA controller and if it is the highest priority request, the controller

asserts the HOLD signal to the CPU,requesting that the CPU relinquish control of the bus and float all its address,data, and control outputs. After floating the address, data and control outputs, the CPU asserts the HLDA signal to the DMA controller. When the DMA controller detects that the HLDA signal has been asserted, it asserts AEN, acknowledges the DMA request by asserting the corresponding DAKx low to the requesting I/O device. This signal is usually used as a chip select for the I/O device, enabling it onto the bus. The DMA controller drives the lower 16 ISA bus address lines SA [15..0], with the address contained in the corresponding channels current address register. The upper address lines are driven by the corresponding DMA channels page register. For a write cycle, this address represents the destination in memory for the data supplied by the I/O device. The DMA controller first asserts the /IORC bus signal to instruct the I/O device to drive the data onto the bus. The /MWTC signal is then asserted low, instructing the memory to latch the data at its trailing edge. Throughout this cycle the bus command signals /IOWC and /MRDC remain inactive (high). The DMA controller then performs the following functions: Decrements the corresponding channels byte/word transfer count register. Increments the same channels current address register. Asserts the I/O devices corresponding DACKx line. Once an I/O devices /DACKx line has been asserted by the DMA controller, it will release the DRQx line to an inactive state (low). Upon detecting the DRQx line low, the DMA controller now drives the HOLD signal low. The CPU responds by dropping the HLDA signal to the DMA controller, thus indicating it is ready to again take control of the bus. In much the same way a DMA memory read cycle is performed, the difference being that /IORC and /MWTC are inactive, while asserting /MRDC instructs the memory to drive the data onto the bus and asserting /IOWC instructs the I/O device to latch the data at its trailing edge.