EE539: Analog Integrated Circuit Design

Course summary

Nagendra Krishnapura
Department of Electrical Engineering Indian Institute of Technology, Madras Chennai, 600036, India

21 April 2008

Nagendra Krishnapura

EE539: Analog Integrated Circuit Design

Course goals

Learn to design negative feedback ampliers on CMOS ICs Negative feedback for controlling the output Ampliers, voltage references, voltage regulators, biasing

Nagendra Krishnapura

EE539: Analog Integrated Circuit Design

Course contents-Ampliers on ICs

Components available in CMOS integrated circuit (IC) processes Device models-dc small signal, dc large signal, ac small signal, mismatch, noise Basic single transistor amplier stages Transistor biasing, compound amplier stages Differential ampliers Fully differential ampliers and common mode feedback

Nagendra Krishnapura

EE539: Analog Integrated Circuit Design

Course contents-Design of opamps

Single stage opamp Folded, telescopic cascode opamps Two stage opamp Fully differential opamps and common mode feedback Applications: Bandgap reference, constant gm bias generation

Nagendra Krishnapura

EE539: Analog Integrated Circuit Design

What you should be able to do now

Analyze negative feedback loops for stability Compensate negative feedback loops Design transconductors and opamps Design appropriate biasing circuits Understand other opamp architectures Design fully differential circuits with common mode feedback Analyze circuit noise and offsets

Nagendra Krishnapura

EE539: Analog Integrated Circuit Design

What you should be able to do now

Bandgap reference Vref + Vout=kVref
LOAD

Vdd b0 b0 bM-1 bM-1

(k-1)R

Voltage regulator with reference + R R + Feedback amplifiers R (k-1)R

Current steering DAC R + RQ C OPA3 C V1 R + OPA2 Active RC filter R

V3

kR Vi1,R R1 + OPA1

V2

Nagendra Krishnapura

EE539: Analog Integrated Circuit Design

Other opamp architectures

Class AB output stage More than two stages Multi path opamp

Nagendra Krishnapura

EE539: Analog Integrated Circuit Design

Class AB opamp
gm1 inp inn +
single stage opamp Rc Cc

Vdd

gm1 inp inn +

single stage opamp Rc Cc

Vdd

Vg11 + vsig M11 out

Vg11 + vsig M11 out

I1

Vg12 + vsig

M12

Large output current drive with a small quiescent current Signal coupled to both transistors of the output stage Crossover distortion Used with heavy loads-headphone driver etc.

Nagendra Krishnapura

EE539: Analog Integrated Circuit Design

Class AB opamp
2I0 I0 I0 I0

Vbp2 Ip Vb1 + I0 Iout out

Vb2 I0 Vbn2 I0

I0 In

Vbn1 +
Nagendra Krishnapura EE539: Analog Integrated Circuit Design

out

2I0

2I0

I0

Class AB opamp: References

D. M. Monticelli, A quad CMOS single-supply op amp with rail-to-rail output swing, IEEE Journal of Solid-State Circuits, vol. 21, pp. 1026 - 1034, December 1986. T. Prabu Sankar, Shanthi Pavan, IITM
Switched capacitor batteries to couple to the output stage

S. Rabii and B. A. Wooley, A 1.8-V digital-audio sigma-delta modulator in 0.8- m CMOS, IEEE Journal of Solid-State Circuits, vol. 32, pp. 783 - 796, June 1997.

Nagendra Krishnapura

EE539: Analog Integrated Circuit Design

Three stage opamp

Very high dc gain for high accuracy High accuracy DACs (16b) Complicated compensation schemes Low speed applications K. N. Leung and P. Mok, Analysis of multistage amplier frequency compensation, IEEE TCAS-II, vol. 48, no. 9, Sep. 2001.

Nagendra Krishnapura

EE539: Analog Integrated Circuit Design

Multi path opamps

slow, high gain path gm2 + gm1
Nagendra Krishnapura

gm3

fast, low gain path

Very high u in a given technology Low power dissipation Low swing-differential pair output Pole zero doublets in close loop transfer functions
Not suitable for discrete time applications ???
EE539: Analog Integrated Circuit Design

Multi path opamps

J. N. Harrison, Dynamic Range and Bandwidth of Analog CMOS Circuits, PhD dissertation, Macquarie University, Sydney, 2002. T. Laxminidhi, V. Prasadu and S. Pavan, A Low Power 44-300 MHz Programmable Active-RC Filter in 0.18um CMOS, Proceedings of the Custom Integrated Circuits Conference, San Jose, September 2007.

Nagendra Krishnapura

EE539: Analog Integrated Circuit Design

References

P. R. Gray and R. G. Meyer, MOS operational amplier design-A tutorial overview, IEEE Journal of Solid-State Circuits, vol. 17, pp. 969 - 982, December 1982. D. M. Monticelli, A quad CMOS single-supply op amp with rail-to-rail output swing, IEEE Journal of Solid-State Circuits, vol. 21, pp. 1026 - 1034, December 1986. K. N. Leung and P. Mok, Analysis of multistage amplier frequency compensation, IEEE TCAS-II, vol. 48, no. 9, Sep. 2001. J. N. Harrison, Dynamic Range and Bandwidth of Analog CMOS Circuits, PhD dissertation, Macquarie University, Sydney, 2002.

Nagendra Krishnapura

EE539: Analog Integrated Circuit Design