ROLL NO.

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Training Report On Title of the Training

Submitted in the partial fulfillment of the requirement for the award of degree of

Bachelors of Technology In Electronics & Communication Engineering

Submitted by: Name: Syed Mohammad Faiz Reg. Number:10902647 Name and Location of Company: DKOP Labs Pvt. Ltd.,Sector-2,Noida Period Training: 01/06/2012- 14/07/2012

Department of Electronics & Comm. Engg Lovely Professional University Phagwara140401, Punjab (India)
Ph. (01824-506960-61) Department of Electronics & Communication Engineering Lovely Professional University Phagwara (Distt. Kapurthala) Punjab India 144001 1|Page

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Ref:______________

Dated: __________

Certificate
Certified that this Training entitled VLSI Design submitted by Syed Mohammad Faiz (10902647), students of Electronics & Communication Engineering Department, Lovely Professional University, Phagwara Punjab in the partial fulfillment of the requirement for the award of Bachelors of Technology (Electronics & Communication Engineering) Degree of LPU, is a record of students own study carried under my supervision & guidance.

Mr. Sandeep Gupta Name and Signature of Training Supervisor Designation:- Chief Learning Officer

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Acknowledgement
In my six weak industrial training it is a wonderful experience to be a part of DESIGN KOP LABS where I have opportunity to work under brilliant minds. I owe my deep regards for the supporting and kind staff authorities who are helping me in my lean patches during these six weak. The knowledge I am gaining throughout my studies have the practical implementation during this period. I am grateful to all the staff of DKOP LABS and for their timely support and sharing of their experience with me. I would like to express my heartiest concern for Mr. Ajeet Kumar Singh for his able guidance and for his inspiring attitude, praiseworthy attitude and honest support. Not to forget the pain staking efforts of our college training and placement cell and specially my training and placement officer. Last but not the least I would express my utmost regards for the electronics and communication department of our Institute.

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Attachment Of Training Certificate issued from training institute with specific training area

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TABLE OF CONTENTS
S. NO. 1. 2. TITLE PAGE NO. 7 to 9 10 to 15

INTRODUCTION ORGANIZATION AND REQUIREMENT 2.1. VLSI Design Flow 2.2. HDL(Hardware Description Language) 2.2.1. Design using HDLs 2.2.2. Simulating and Debugging HDL code 2.2.3. Design verifications with HDLs 2.3. HDL and programming languages 2.4. Importance of HDLs 2.5. Advantages of HDL 2.6. Disadvantages of HDL 3. EXECUTION OF WORK 3.1. VERILOG(Verify Logic) 3.1.1. History of verilog 3.1.2. Design methodology 3.1.3. General syntax for writing VERILOG program 3.1.4. What is MODULE in verilog 3.1.5. First verilog program 3.1.6. Language elements 3.2. Different types of modeling used in verilog 3.2.1. Gate level modeling 3.2.2. Data flow modeling 3.2.2.1.Operators 3.2.3. Behavioral modeling 3.2.3.1.Types of Statements 3.2.4. Switch level modeling 3.2.4.1.... Cmos(complimentary metal oxide semiconducator) 3.2.4.2.Cmos inverter 3.3. FPGA(Field Programmable Gate Array) 3.3.1. FPGA Comparisons 3.3.2. FPGA Architecture 3.3.3. FPGA Design and Programming 3.4. CPLD(Complex Programmable Logic Device) 4. HARDWARE/ SOFTWARE IMPLIMENATION 4.1. EDA(Electronic Design Automation) tools 4.1.1. History of EDA tools 4.1.2. Current status 4.2. Software focuses on Design 4.3. Modelsim simulator 4.3.1. Introduction 4.3.2. Creating the working library 5|Page

16 to 44

45 to 48

ROLL NO.-RE2R55B33 4.3.3. Project flow 4.3.4. Multiple library flow SIMULATIVE/ HARWARE ANALYSIS 5.1. UART 5.2. UART Specifications 5.3. UART Receiving Subsystem 5.4. UART Transmitting Subsystem 5.5. Entire UART System REFERENCES FUTURE SCOPE OF TRAINING

5.

49 to 50

6. 7.

51 52

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1. INTRODUCTION
What is an IC (integrated circuit)? A chip or die where many circuit components and the wiring that connects them are manufactured simultaneously. Integrated circuits are used in almost all electronic equipment in use today and have revolutionized the world of electronics. A hybrid integrated circuit is a miniaturized electronic circuit constructed of individual semiconductor devices, as well as passive components, bonded to a substrate or circuit board. Integrated circuits were made possible by experimental discoveries which showed that semiconductor devices could perform the functions of vacuum tubes and by mid-20th-century technology advancements in semiconductor device fabrication the integration of large numbers of tiny transistors into a small chip was an enormous improvement over the manual assembly of circuits using electronic components. The integrated circuit's mass production capability, reliability, and building-block approach to circuit design ensured the rapid adoption of standardized ICs in place of designs using discrete transistors. There are two main advantages of ICs over discrete circuits: cost and performance. Cost is low because the chips, with all their components, are printed as a unit by photolithography and not constructed as one transistor at a time. Furthermore, much less material is used to construct a circuit as a packaged IC die than as a discrete circuit. Performance is high since the components switch quickly and consume little power (compared to their discrete counterparts) because the components are small and close together

Generations of IC (Integrated Circuits)

The first integrated circuits contained only a few transistors. Called "Small-Scale Integration" (SSI), digital circuits containing transistors numbering in the tens provided a few logic gates for example, while early linear ICs such as the Plessey SL201 or the Philips TAA320 had as few as two transistors. SSI circuits were crucial to early aerospace projects, and vice-versa. Both the Minuteman missile and Apollo program needed lightweight digital computers for their inertial guidance systems; the Apollo guidance computer led and motivated the integrated-circuit technology The next step in the development of integrated circuits, taken in the late 1960s, introduced devices which contained hundreds of transistors on each chip, called "Medium-Scale Integration" (MSI). They were attractive economically because while they cost little more to produce than SSI devices, they allowed more complex systems to be produced using smaller circuit boards, less 7|Page

ROLL NO.-RE2R55B33 assembly work (because of fewer separate components), and a number of other advantages. Further development, driven by the same economic factors, led to "Large-Scale Integration" (LSI) in the mid 1970s, with tens of thousands of transistors per chip. Integrated circuits such as 1K-bit RAMs, calculator chips, and the first microprocessors, that began to be manufactured in moderate quantities in the early 1970s, had under 4000 transistors. True LSI circuits, approaching 10000 transistors, began to be produced around 1974, for computer main memories and second-generation microprocessors The final step in the development process, starting in the 1980s and continuing through the present, was "very large-scale integration" (VLSI). The development started with hundreds of thousands of transistors in the early 1980s, and continues beyond several billion transistors as of 2009. There was no single breakthrough that allowed this increase in complexity, though many factors helped. Manufacturers moved to smaller rules and cleaner fabs, so that they could make chips with more transistors and maintain adequate yield.

Advances of Integrated circuits

Among the most advanced integrated circuits are the microprocessors or "cores", which control everything from computers to cellular phones to digital microwave ovens. Digital memory chips and ASICs are examples of other families of integrated circuits that are important to the modern information society. While the cost of designing and developing a complex integrated circuit is quite high, when spread across typically millions of production units the individual IC cost is minimized. The performance of ICs is high because the small size allows short traces which in turn allows low power logic (such as CMOS) to be used at fast switching speeds. ICs have consistently migrated to smaller feature sizes over the years, allowing more circuitry to be packed on each chip. This increased capacity per unit area can be used to decrease cost and/or increase functionalitysee Moore's law which, in its modern interpretation, states that the number of transistors in an integrated circuit doubles every two years. Only a half century after their development was initiated, integrated circuits have become ubiquitous. Computers, cellular phones, and other digital appliances are now inextricable parts of the structure of modern societies. That is, modern computing, communications, manufacturing and transport systems, including the Internet, all depend on the existence of integrated circuits.

VLSI (Very Large Scale Integration)

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Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistor-based circuits into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device. The term is no longer as common as it once was, as chips have increased in complexity into billions of transistors Uses photolithography to fabricate transistors, wires, on silicon wafers. Common technologies used used in VLSI are CMOS, Bipolar, Bi Cmos, etc.

Challenges faced by VLSI

As microprocessors become more complex due to technology scaling, microprocessor designers have encountered several challenges which force them to think beyond the design plane, and look ahead to post-silicon: Power usage/Heat dissipation As threshold voltages have ceased to scale with advancing process technology, dynamic power dissipation has not scaled proportionally. Maintaining logic complexity when scaling the design down only means that the power dissipation per area will go up. This has given rise to techniques such as dynamic voltage and frequency scaling (DVFS) to minimize overall power. Stricter design rules Due to lithography and etch issues with scaling, design rules for layout have become increasingly stringent. Designers must keep ever more of these rules in mind while laying out custom circuits. The overhead for custom design is now reaching a tipping point, with many design houses opting to switch to electronic design automation (EDA) tools to automate their design process.

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2. ORGANIZATION AND REQUIREMENT 2.1 VLSI Design Flow

Basic VLSI design flow is shown in the above figure. 10 | P a g e

ROLL NO.-RE2R55B33 This design is usually used by the VLSI designers who uses HDLs (Hardware Description Language).in any design, specifications are written first. Specifications describe abstractly the functionality, interface, and overall architecture of the digital circuit to be designed. At this point the architects do need to think about how they will implement this circuit. A behavioral is then created to analyze the design in terms of functionality, performance, compliance to standards and other high level issues. Behavioral descriptions are written with HDLs. The behavioral description is manually converted to an RTL description in an HDL.The designers have to describe the dataflow that will implement the desired digital circuit. From this point onward, the design process is done with the help of EDA tools. Logic synthesis tools convert the RTL description to a gate level net list. A gate level net list is a description of circuit in terms of gates and connections between them. Logic synthesis tools ensure that gate level net list meets timing, area and power specifications. The gate level net list is a input to the place and route tool, which creates a layout. The layout is verified and then fabricated into the chip. Thus, most digital design activity is concentrating manually on optimizing the RTL description of the circuit.. After the RTL description is frozen, EDA tools are available to assist the user for the further processes. Designing at RTL level has shrunk the design cycle times from years to few months. It is also possible to do many design iterations in a short period of time. Behavioral synthesis tools have been emerged recently. These tools can create RTL description from a behavioral or algorithmic description of the circuit. As these tools mature, digital circuit design will become similar to high level computer programming. Designer will simply implement the HDL in algorithm in an HDL at a very abstract level. EDA tools will help the designers convert the behavioral descriptions to the final IC chip. It is note that although EDA tools are available to automate the processes and cut design cycle times, the designer is still the person who controls how the tool will work. EDA tools are susceptible to the GIGO: garbage in garbage out phenomenon. If used improperly the EDA tools will lead to inefficient designs. Thus, the designers still needs to understand the nuances of design methodologies, using EDA tool to obtain optimize design.

2.2 HDL(Hardware Description Language)

In electronics, a hardware description language or HDL is any language from a class of computer languages and/or programming languages for formal description of electronic circuits, and more specifically, digital logic. It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation. HDLs are standard text-based expressions of the spatial and temporal structure and behavior of electronic systems. Like concurrent programming languages, HDL syntax and semantics includes explicit notations for expressing concurrency. However, in contrast to most software programming languages, HDLs also include an explicit notion of time, which is a primary 11 | P a g e

ROLL NO.-RE2R55B33 attribute of hardware. Languages whose only characteristic is to express circuit connectivity between a hierarchy of blocks are properly classified as net list languages used on electric computer-aided design (CAD). HDLs are used to write executable specifications of some piece of hardware. A simulation program, designed to implement the underlying semantics of the language statements, coupled with simulating the progress of time, provides the hardware designer with the ability to model a piece of hardware before it is created physically. It is this executability that gives HDLs the illusion of being programming languages. Simulators capable of supporting discrete-event (digital) and continuous-time (analog) modeling exist, and HDLs targeted for each are available. It is certainly possible to represent hardware semantics using traditional programming languages such as C++, although to function such programs must be augmented with extensive and unwieldy class libraries. Primarily, however, software programming languages do not include any capability for explicitly expressing time and this is why they do not function as a hardware description language. Before the recent introduction of SystemVerilog, C++ integration with a logic simulator was one of the few ways to use OOP in hardware verification. SystemVerilog is the first major HDL to offer object orientation and garbage collection.

2.2.1 Design using HDLs

Efficiency gains realized using HDL means a majority of modern digital circuit design revolves around it. Most designs begin as a set of requirements or a high-level architectural diagram. Control and decision structures are often prototyped in flowchart applications, or entered in a state-diagram editor. The process of writing the HDL description is highly dependent on the nature of the circuit and the designer's preference for coding style . The HDL is merely the 'capture language'often begin with a high-level algorithmic description such as MATLAB or a C++ mathematical model. Designers often use scripting languages (such as Perl) to automatically generate repetitive circuit structures in the HDL language. Special text editors offer features for automatic indentation, syntax-dependent coloration, and macro-based expansion of entity/architecture/signal declaration The HDL code then undergoes a code review, or auditing. In preparation for synthesis, the HDL description is subject to an array of automated checkers. The checkers report deviations from standardized code guidelines, identify potential ambiguous code constructs before they can cause misinterpretation, and check for common logical coding errors, such as dangling ports or shorted outputs. This process aids in resolving errors before the code is synthesized. In industry parlance, HDL design generally ends at the synthesis stage. Once the synthesis tool has mapped the HDL description into a gate net list, this net list is passed off to the back-end stage. Depending on the physical technology (FPGA, ASIC gate array, ASIC standard cell), HDLs may or may not play a significant role in the back-end flow. In general, as the design flow progresses toward a physically realizable form, the design database becomes progressively more laden with technology-specific information, which cannot be stored in a generic HDL description.

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2.2.2 Simulating and Debugging HDL code

Essential to HDL design is the ability to simulate HDL programs. Simulation allows a HDL description of a design (called a model) to pass design verification, an important milestone that validates the design's intended function (specification) against the code implementation in the HDL description. It also permits architectural exploration. The engineer can experiment with design choices by writing multiple variations of a base design, then comparing their behavior in simulation. Thus, simulation is critical for successful HDL design. To simulate an HDL model, an engineer writes a top-level simulation environment (called a testbench). At minimum, a testbench contains an instantiation of the model (called the device under test or DUT), pin/signal declarations for the model's I/O, and a clock waveform. The testbench code is event driven: the engineer writes HDL statements to implement the (testbenchgenerated) reset-signal, to model interface transactions (such as a hostbus read/write), and to monitor the DUT's output. An HDL simulator the program that executes the testbench maintains the simulator clock, which is the master reference for all events in the testbench simulation. Events occur only at the instants dictated by the testbench HDL (such as a resettoggle coded into the testbench), or in reaction (by the model) to stimulus and triggering events. Modern HDL simulators have a full-featured graphical user interfaces, complete with a suite of debug tools. These allow the user to stop and restart the simulation at any time, insert simulator breakpoints (independent of the HDL code), and monitor or modify any element in the HDL model hierarchy. Modern simulators can also link the HDL environment to user-compiled libraries, through a defined PLI/VHPI interface. Linking is system-dependent (Win32/Linux/SPARC), as the HDL simulator and user libraries are compiled and link Design verification is often the most time-consuming portion of the design process, due to the disconnect between a device's functional specification, the designer's interpretation of the specification, and the imprecision of the HDL language. The majority of the initial test/debug cycle is conducted in the HDL simulator environment, as the early stage of the design is subject to frequent and major circuit changes. An HDL description can also be prototyped and tested in hardware programmable logic devices are often used for this purpose. Hardware prototyping is comparatively more expensive than HDL simulation, but offers a real-world view of the design. Prototyping is the best way to check interfacing against other hardware devices and hardware prototypes.

2.2.3 Design verifications with HDLs

Design verification was a laborious, repetitive loop of writing and running simulation test cases against the design under test. As chip designs have grown larger and more complex, the task of design verification has grown to the point where it now dominates the schedule of a design team. Looking for ways to improve design productivity, the EDA industry developed the Property Specification Language. In formal verification terms, a property is a factual statement about the expected or assumed behavior of another object. Ideally, for a given HDL description, a property or properties can be proven true or false using formal mathematical methods. In practical terms, many properties 13 | P a g e

ROLL NO.-RE2R55B33 cannot be proven because they occupy an unbounded solution space. However, if provided a set of operating assumptions or constraints, a property checker can prove (or disprove) more properties, over the narrowed solution space. The assertions do not model circuit activity, but capture and document the "designer's intent" in the HDL code. In a simulation environment, the simulator evaluates all specified assertions, reporting the location and severity of any violations. In a synthesis environment, the synthesis tool usually operates with the policy of halting synthesis upon any violation. Assertion-based verification is still in its infancy, but is expected to become an integral part of the HDL design toolset.

2.3 HDL and programming languages

A HDL is analogous to a software programming language, but with major differences. Many programming languages are inherently procedural (single-threaded), with limited syntactical and semantic support to handle concurrency. HDLs, on the other hand, resemble concurrent programming languages in their ability to model multiple parallel processes (such as flipflops, adders, etc.) that automatically execute independently of one another. Any change to the process's input automatically triggers an update in the simulator's process stack. Both programming languages and HDLs are processed by a compiler (usually called a synthesizer in the HDL case), but with different goals. For HDLs, 'compiler' refers to synthesis, a process of transforming the HDL code listing into a physically realizable gate netlist. The netlist output can take any of many forms: a "simulation" netlist with gate-delay information, a "handoff" netlist for post-synthesis place and route, or a generic industry-standard EDIF format (for subsequent conversion to a JEDEC-format file). On the other hand, a software compiler converts the source-code listing into a microprocessorspecific object-code, for execution on the target microprocessor. As HDLs and programming languages borrow concepts and features from each other, the boundary between them is becoming less distinct. However, pure HDLs are unsuitable for general purpose software application development, just as general-purpose programming languages are undesirable for modeling hardware. Yet as electronic systems grow increasingly complex, and reconfigurable systems become increasingly mainstream, there is growing desire in the industry for a single language that can perform some tasks of both hardware design and software programming. SystemC is an example of suchembedded system hardware can be modeled as non-detailed architectural blocks (blackboxes with modeled signal inputs and output drivers). The target application is written in C/C++, and natively compiled for the host-development system (as opposed to targeting the embedded CPU, which requires host-simulation of the embedded CPU). The high level of abstraction of SystemC models is well suited to early architecture exploration, as architectural modifications can be easily evaluated with little concern for signal-level implementation issues. In an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of assembly languages, there are moves to raise the abstraction level of the design.

2.4 Importance of HDLs

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A Hardware Description Language (HDL) is a software programming language used to model the intended operation of a piece of hardware EDA tools are computer based software systems to design Very Large Scale Integrated circuits. Now EDA tools are available for almost every stage of VLSI design flow. But to start with we must convey design idea (that is in our mind) to EDA tool in such a way that the tool is able to understand that and generate a highly optimized design implementation. This transfer of idea from human beings to machines is called Design Entry. There are two methods of design entry: graphical and textual. Graphical method includes schematic entry and state diagram entry while textual method implies use of HDL's (Hardware Description Languages). Graphical method works fairly well up to a certain level of circuit complexity but in larger circuits they become cumbersome and time consuming.

2.5 Advantages of HDL

Compact description. Easy to edit. Highly portable. Supports a higher level of abstraction. Rapid prototyping of design. Availability of extensive vendor libraries. Increasing capability of synthesis tools.

2.6 Disadvantages of HDL

No support for analog behavior. Need to learn coding styles that ensures synthesizable results.

Support for hardware concurrency and time frame are two main features that distinguishes HDLs from other programming language.

3. EXECUTION OF WORK 3.1 VERILOG(Verify Logic)

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ROLL NO.-RE2R55B33 In the semiconductor and electronic design industry, Verilog is a hardware description language (HDL) used to model electronic systems. Verilog HDL, not to be confused with VHDL, is most commonly used in the design, verification, and implementation of digital logic chips at the register transfer level (RTL) of abstraction. It is also used in the verification of analog and mixed-signal circuits.

3.1.1 History of verilog

Beginning Verilog was invented by Phil Moorby and Prabhu Goel during the winter of 1983/1984 at Automated Integrated Design Systems (renamed to Gateway Design Automation in 1985) as a hardware modeling language. Gateway Design Automation was purchased by Cadence Design Systems in 1990. Cadence now has full proprietary rights to Gateway's Verilog and the VerilogXL simulator logic simulators. Verilog-95 With the increasing success of VHDL at the time, Cadence decided to make the language available for open standardization. Cadence transferred Verilog into the public domain under the Open Verilog International (OVI) (now known as Accellera) organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95. In the same time frame Cadence initiated the creation of Verilog-A to put standards support behind its analog simulator Spectre. Verilog-A was never intended to be a standalone language and is a subset of Verilog-AMS which encompassed Verilog-95. Verilog 2001 Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that users had found in the original Verilog standard. These extensions became IEEE Standard 1364-2001 known as Verilog-2001. Verilog-2001 is a significant upgrade from Verilog-95. First, it adds explicit support for (2's complement) signed nets and variables. Previously, code authors had to perform signedoperations using awkward bit-level manipulations (for example, the carry-out bit of a simple 8bit addition required an explicit description of the boolean-algebra to determine its correct value). The same function under Verilog-2001 can be more succinctly described by one of the built-in operators: +, -, /, *, >>>. A generate/endgenerate construct (similar to VHDL's generate/endgenerate) allows Verilog-2001 to control instance and statement instantiation through normal decision-operators (case/if/else). Using generate/endgenerate, Verilog-2001 can instantiate an array of instances, with control over the connectivity of the individual instances. File I/O has been improved by several new system-tasks. And finally, a few syntax additions were introduced to improve code-readability (eg. always @*, named-parameter override, C-style function/task/module header declaration). 16 | P a g e

ROLL NO.-RE2R55B33 Verilog-2001 is the dominant flavor of Verilog supported by the majority of commercial EDA software packages. Verilog 2005 Not to be confused with SystemVerilog, Verilog 2005 (IEEE Standard 1364-2005) consists of minor corrections, spec clarifications, and a few new language features (such as the uwire keyword). A separate part of the Verilog standard, Verilog-AMS, attempts to integrate analog and mixed signal modelling with traditional Verilog. SystemVerilog SystemVerilog is a superset of Verilog-2005, with many new features and capabilities to aid design-verification and design-modeling.

3.1.2 Design methodology

TOP MODULE

SUB MODULE 1

SUB MODULE 2

SUB MODULE 3

cell

cell

cell

Sub Module 4

Sub Module5

cell

cell

cell

cell

cell

cell

cell

3.1.3 General syntax for writing VERILOG program

module Module_Name (Port_List) ;

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<Module Internals>

... ...

Endmodule

Syntax :
module Module_Name(Port_List) ; <Port Declarations> <Internal Signals Declaration> <Functionality> endmodule The port list in module definitions contains names of ports (terminals) only and we must specify whether they are input, output or bi-directional terminals. So port declarations are the first thing we write in module internals. Ports are declared using Verilog keywords input, output and inout. Keyword inout is used for bi-directional ports. All internal signals between various hardware units must be assigned some name and declared its type. So second thing we write in module internals is internal signal declaration. Then follows the actual module functionality.

3.1.4 What is MODULE in verilog

Module is a basic functional unit in Verilog. A module can be seen as a design block with some inputs and outputs. How that block works is written inside that module. All the distinct blocks in design tree corresponds to a module in Verilog. So module is just like black 18 | P a g e

ROLL NO.-RE2R55B33 box with input and output terminals and that black box interacts with the outside environment through these terminals only. The relationship between these input and output terminals is hidden from the environment. Every module definition begins with a keyword module and ends with keyword endmodule. Only within these two keywords functionality of a module is specified. Each module has a module name and port list. Module name is an identifier for that particular module and port list contains the list of all input and output terminals for the module. To build a full adder from the half adder defined just now we have to create an instance of halfadder module in fulladder module. This instance is given a name and ports are connected appropriately. Certain predefined modules of basic hardware elements are provided in Verilog and we call them as primitives. These primitives can be instantiated inside modules in same way but giving them names is optional. So a module may contain instances of primitives and other modules.

3.1.5 First verilog program

Program of the half adder using verilog:

in1 in2

sum

carry
module half_adder(sum, carry, in1, in2) ; output sum, carry ; input in1, in2 ; xor (sum, in1, in2) ; and (carry, in1, in2) ; endmodule

Program of the half adder using verilog:

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carry_in a b HALF ADDER HALF ADDER sum

carry_out

module full_adder(sum, carry_out, a, b, carry_in) ; output sum, carry_out ; input a, b, carry_in ; wire w1, w2, w3; half_adder ha1(w1, w2, a, b); half_adder ha2(sum, w3, w1, carry_in); or (carry_out, w2, w3); endmodule

3.1.6 Language elements White space

Blank spaces \b Tabs\t New lines\n White spaces have no syntactical significance readability.Whitespace is not ignored in strings.

and

can

be

inserted

for

better

Comments
// The rest of the line is a comment. /* Multiple line comments */ /* Nesting /* comments */ is NOT allowed */ Comments make life easier for you and others also. So insert a lot of meaningful comments in your code

Operators
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a=~b;

Operators are of three types:

Unary,binary and ternary. a= b && c; A=b ? c:d ;

Signal Values
0 1 x or X z or Z Logic Zero Logic One Unknown High Impedance

Representation of Number
Decimal Hex Octal Binary d or D h or H o or O b or B

Syntax
<size> '<radix> <number> size specifies number of bits to be occupied by number and is written only in decimal. radix determines the arithmetic base of number. number is the value expressed in the indicated base only. Number 2'b10 3'd6 6'o57 3'O4 8'H2d 32'haA19 5'B110x0 6'ozz 12'hZXb #Bits Base 2 3 6 3 8 Hex 32 Hex 5 Binary 6 12 Hex Storage Binary 10 Decimal 110 Octal 101111 Octal 100 00101101 1010101000011001 110x0 Octal zzzzzz zzzzxxxx1011

Number Format
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If we do not specify the size it takes default value which is machine and simulation dependent but is at least 32 bits. Also if we do not specify radix default is decimal base. Number 'bz 'h9 3 #Bits >= 32 >= 32 >= 32 Base Binary Hex Decimal Storage zz..zzz 0000..1001 000...011

If the size is greater than the value of number, the number in the most significant bit is extended for MSB = 0, x or z zero extended if MSB = 1. Number 8'bx001 5'o1 15'hzf 9'd5 #Bits 8 5 15 9 Hex Base Binary Storage xxxxx001 Octal 00001 zzzzzzzzzzz1111 Decimal 000000101

For negative numbers we place a minus sign before the number representation. Negative numbers are stored as 2's complement. Number #Bits Base Storage -6'd3 6 Decimal 111101 -3'b11 3 Binary 101 Underscores can be inserted in numbers to enhance readability and are ignored by Verilog. 12'b000111010100 12'b000_111_010_100

Identifiers are names given to different objects so that they can be referenced in design. An identifier is any sequence of letters [A-Z] and [a-z], digits [0-9], underscore [ _ ] and $ character. Cannot begin with $ or digits and are case sensitive. An identifier may contain up to 1024 characters. myid m_y_id 3my_id $myid _myid4 valid valid invalid invalid valid

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Keywords
Keywords are special words reserved by language, their meaning is Predefined and cannot be used as identifiers. All keywords are in lowercase.

always and assign begin buf bufif0 bufif1 case casex casez cmos deassign default defparam disable edge else end endcase endfunction endmodule endprimitive endspecify endtable endtask event

for force forever fork function highz0 highz1 if initial inout input integer join large rpmos medium module nand negedge nmos nor not notif0 notif1 output parameter

supply1 posedge table primitive task pull0 time pull1 tran pulldown tranif0 pullup tranif1 rcmos tri real tri0 realtime tri1 reg triand release trior repeat trireg rnmos vectored wait wire rtran xor rtranif0 rtranif1 scalared small specify xnor strength strong0 strong1 supply0

pmos

Data types
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Verilog contains predefined datatypes:

Nets (connectivity) wire tri wand wor triand trior supply0+ supply1 tri0 tri1 trireg real time realtime Registers (storage) reg integer

Nets
Nets represent the interconnection between hardware elements. Value of a net variable is determined throughout the simulation by output of the components they are connected to (called Drivers). If no driver is connected to a net, the net defaults to a value of Z. Most commonly used type of net is wire. module my_ckt (f, a, b, c, d, e); output f ; input a, b, c, d, e ; wire n1; wire m1, x0, x1 ; endmodule keyword wire. 24 | P a g e In above circuit n1, m1, x0, x1 are nets. They are declared inside module by

ROLL NO.-RE2R55B33 Some other type of nets will be discussed later in advance Verilog concepts. Any undeclared nets default to type wire.

a b

n1 x0

c d

m1 x1

Registers
Register Type reg integer time real realtime Usage Stores a logic value Supports computation Stores time as a 64-bit unsigned quantity Stores values (e.g. delays) as real numbers Stores time values as real numbers

Registers are variables that store values. It is an abstraction of a hardware storage element, but it need not correspond directly to physical storage elements in a circuit. Registers retain value until another value is placed onto them.Unlike a net, a register does not need a driver. A register object may be assigned value within a procedural statement, a user sequential primitive,task, or function.

REG The reg kind of register data type is the one most commonly used. A reg data type models the feature of hardware that allows a logic value to be stored in a flip-flop or a latch. A reg object may never be the output of primitive gate or the target of a continuous assignment. The default value for a reg data type is X. 25 | P a g e

ROLL NO.-RE2R55B33 INTEGER The integer data type supports numeric computation in procedural code. Integers are represented internally to the word length of the host machine (at least 32 bits). A negative number is stored in 2s complement format. Registers declared as data types reg store values as unsigned quantities,whereas integers store values as signed quantities. REAL Accurate modeling of delay values might require the use of real data types. Real objects are stored in double precision, typically a 64-bit value. Real values can be specified in decimal and exponential notation. An object of type real may not be connected to a port or terminal of a primitive.Real numbers cannot have a range declaration and their default value is 0. TIME The data type time supports time-related computations within procedural code in Verilog models. Time variables are stored as unsigned 64-bit quantities. A variable of type time may not be used in a module port; nor may it be an input or output of a primitive. Data type realtime stores time values in real number format. The system function $time is invoked to get the current simulation time.

Constants
A constant in Verilog is declared with the keyword parameter, which declares and assigns values to the constant. The value of a constant may not be changed during simulation but parameters (or constants) can be changed at module instantiation or by using the defparam statement. parameter high_index = 22 ; parameter av_delay = (min_delay + max_delay) / 2 ; parameter initial_state = 8b1011_1000 ;

3.2 Different types of modeling used in verilog

Gate level modeling Data flow modeling Behavioral modeling Switch level modelling

3.2.1. Gate level modeling

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Primitives
Verilog provides a robust set of built-in gate primitives. Primitives are like predefined modules. A logic circuit is described on gate to gate basis using these primitives. Primitives can be instantiated only within modules and use of identifier name with primitive instantiation is optional. The port list of a primitive have output(or outputs) written first, followed by inputs. AND if any of the input is 0, output is 0 else if any of input is x or z , output is x else if all inputs are 1, output is 1 NAND if any of the input is 0, output is 1 else if any of input is x or z , output is x else if all inputs are 1, output is 0 OR if any of the input is 1, output is 1 else if any of input is x or z , output is x else if all inputs are 0, output is 0 NOR if any of the input is 1, output is 0 else if any of input is x or z , output is x else if all inputs are 0, output is 1

XOR if any of the input is x or z, output is x else if odd number of inputs are 1, output is 1 else output is 0 XNOR if any of the input is x or z, output is x 27 | P a g e

ROLL NO.-RE2R55B33 else if even number of inputs are 1, output is 1 else output is 0 BUF if input is 1, output is 1 else if input is 0, output is 0 else if input is x or z, output is x NOT if input is 1, output is 0 else if input is 0, output is 1 else if input is x or z, output is x We can instantiate multiple primitives of same type by a single statement using comma-separated lists e.g. nand G1(y1, a1, a2, a3), (y2, b1, b2, b3), M2(d3, e1, e2);

Verilog gate level description of a and-or-invert logic gate module AOI(out, in1, in2, in3, in4) ; output out ; input in1, in2, in3, in4 ; wire y1, y2 ; and (y1, in1, in2) ; and a1(y2, in3, in4) ; nor (out, y1, y2); endmodule
in1 in2 y1 out in3 in4 y2

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3.2.2. Data flow modeling

Data flow modeling describes the design in terms of expressions instead of primitive gates. A continuous assignment statement is the most basic statement in the dataflow modeling. It is used to assign a value to a net. It starts with the keyword assign followed by actual assignment e.g. assign A = x | (Y & ~Z) ; assign B[3:0] = 4b10xx ; assign C[15:0] = F[15:0] ^ E[15:0] ; Left hand side of the assignment must be nets(scalar or vector), but right hand side expression can have registers, nets or function calls as operands. The continuous assignment statement are continuously active and they all execute in parallel. Whenever value of any operand on right side changes expression is reevaluated and new value is assigned to the corresponding net. Continuous assignments can be made implicitly by associating the right hand side expression with the declaration of target net e.g. Instead of wire cout ; assign cout = cin1 + cin2 ; we can write wire cout = cin1 + cin2 Multiple assignments can be made with one assign keyword using comma-separated lists e.g. assign y1 = a1 ^ a2, y2 = a2 | a3, y3 = a1 + a3 ; assign data = s[3:0] + r[5:2], m = a & g ; Verilog dataflow style description of a 1-bit full adder

module f_add_1bit ( sum, cout, a, b, cin) ; 29 | P a g e

ROLL NO.-RE2R55B33 output sum, cout ; input a, b, cin ;

assign sum = a ^ b ^ cin ; assign cout = (a & cin) | (b & cin) | (a & b) ;

endmodule Verilog has a robust set of built-in operators that manipulate the various types of data implemented in the language to produce values on nets and registers. Some of the operators are used within expressions on right-hand side of continuous assignment statements and procedural statements; others are used in Boolean expressions in conditional statements or with conditional operators.

3.2.2.1 Operators
Functional Group Logical && || ! Bitwise & | ~ ^ ~^ or ^~ Reduction & 30 | P a g e Reduction and Bitwise and Bitwise or Bitwise not Bitwise xor Bitwise xnor Logical and Logical or Logical not Operator Name

ROLL NO.-RE2R55B33 ~& | ~| ^ ~^ or ^~ Shift >> << Right Shift Left Shift Reduction nand Reduction or Reduction nor Reduction xor Reduction xnor

Functional Group Concatenation

Operator

Name

{ } { { } } Relational > < >= <= Equality == != === !== Conditional ?:

Concatenation Replication

Greater than Less than Greater than or equal to Less than or equal to

Equality Inequality Case equality Case inequality

Conditional

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Arithmetic + * / % Add Subtract Multiply Divide Modulus

Logical Operators
&& || ! - logical AND - logical OR - logical NOT

Logical operators evaluates to one bit value 0, 1, or x. These operators gives result on the basis of logical values of operands I.e. If operand has zero value, it is taken as logical false (0) If operand has non-zero value, it is taken as logical true (1) If a bit in any of the operand is x or z, whole operand is treated as x

A= 6 B=0 C=x C && B

A && B A || (!B) C || B

1 && 0 1 || 1 x || 0 x && 0 0

0 1 x

Reduction Operators
& | 32 | P a g e Reduction AND Reduction OR

ROLL NO.-RE2R55B33 ^ ~& ~| ~^ or ^~ Reduction XOR Reduction NAND Reduction NOR Reduction XNOR

Reduction operators are unary operators i.e. they act on single operands. They create a single-bit result by operating on a multibit operand. &(010101) a = 4b1001 b = ^a |(010x10) b=1^0^0^1 0|1|0|x|1|0 b=1 1 0&1&0&1&0&1 0

Bitwise Operators
& | ~ ^ ~^ - bitwise AND - bitwise OR - bitwise NOT - bitwise XOR - bitwise XNOR

Bitwise operators acts on individual bits of the operands. The operands may be scalar or vector. If one of the operand is shorter than the other, it will be zero extended to match the length of the longer operand. The bitwise not operator negates the individual bits of an operand. a = 4b1010 b = 4b1100 c = ~a d=a&b e = (101011) ^ b c = ~(1010) d = 1010 & 1100 e = 101011 ^ 1100 c = 0101 d = 1000 e = 101011 ^ 001100 e = 100111

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Shift Operators
>> << shift right shift left

Verilog shift operators operate on a single operand and shift (left or right) the bit pattern of the operand by a specified number of positions, filling zeroes in the position that are vacated. a = 4b1010 d = a >> 2 c = a << 1 d = 0010 c = 0100

Concatenation Operators
{ op1, op2, } This operator concatenates op1, op2, to a single number. The operand should be sized, no unsized constant operand is allowed. If the operand A is bit pattern 1011 and the operand B is the bit pattern 0001, then {A, B} is the bit pattern 1011_0001 {0011, {{01}, {10}}} = 0011_0110 Replication of same operand can be expressed by using a replication constant which specifies how many times to replicate the number inside the brackets ({ }). a = 1b1 b = 3b010 c = 3b101 catr = { 4{a}, b, 2{c} } catr = {1, 1, 1, 1, 010, 101, 101} Relational Operators > < >= <= greater than less than greater than or equal to less than or equal to 34 | P a g e

ROLL NO.-RE2R55B33

The Verilog relational operators compare operands and produce a Boolean 0 or 1 (true or false) result. If any bit in one of the operands is unknown (x), the result is unknown.

1>0 b1x1 <= 0 10 < z x x

3.2.3 Behavioral modeling

Verilog behavioral code is inside procedures blocks, but there is a exception, some behavioral code also exist outside procedures blocks. We can see this in detail as we make progress. There are two types of procedural blocks in Verilog initial : initial blocks execute only once at time zero (start execution at time zero). always : always blocks loop to execute over and over again, in other words as name means, it executes always. initial begin clk = 0; reset = 0; enable = 0; data = 0; end end always@ (posedge clk) begin : D_FF if (reset == 1) q <= 0; else q <=d; end

3.2.3.1 Types of Statements Procedural Assignment Statements

Procedural assignment statements assign values to registers and can not assign values to nets ( wire data types) You can assign to the register (reg data type) the value of a net (wire), constant, another register, or a specific value. If a procedure block contains more then one statement, those statements 35 | P a g e

ROLL NO.-RE2R55B33 must be enclosed within Sequential begin - end block Parallel fork - join block When using begin-end, we can give name to that group. This is called Named blocks.

Sequential statement
The begin - end keywords: Group several statements together. Cause the statements to be evaluated in sequentially (one at a time). Any timing within the sequential groups is relative to the previous statement. Delays in the sequence accumulate (each delay is added to the previous delay) Block finishes after the last statement in the block.

Conditional statement:
The if - else statement controls the execution of other statements, In programming language like c, if - else controls the flow of program. if (condition) statements; if (condition) statements; else statements; if (condition) statements; else if (condition) statements; ................ ................ else statements;

Case statement:

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ROLL NO.-RE2R55B33 The case statement compares a expression to a series of cases and executes the statement or statement group associated with the first matching case ? case statement supports single or multiple statements. ? Group multiple statements using begin and end keywords. case (<expression>) <case1> : <statement> <case2> : <statement> ..... default : <statement> endcase

Looping statement:
Looping statements appear inside a procedural blocks only, Verilog has four looping statements like any other programming language. forever repeat while for

Continuous assignment statements:

Continuous assignment statements drives nets (wire data type). They represent structural connections. They are used for modeling Tri-State buffers. They can be used for modeling combinational logic. They are outside the procedural blocks (always and initial blocks). The continuous assign overrides and procedural assignments. The left-hand side of a continuous assignment must be net data type. syntax : assign (strength, strength) # delay net = expression;

Modeling the flip flops with always statement

Very basic: an edge-sensitive flip-flop reg q; always @(posedge clk) q = d; 37 | P a g e

ROLL NO.-RE2R55B33 q = d assignment runs when clock rises: exactly the Behavior you expect

Modeling FSM(Finite State Machine) behaviorally

There are many ways to do it: -Define the next-state logic combinationally and define the state-holding latches explicitly -Define the behavior in a single always @(posedge clk) block -Variations on these themes

3.2.4 Switch level modeling

We have learnt about the digital design and simulations at a higher level of abstractions such as gates, data flow, and behavior. However, in rare cases designers will choose to design the leaf level modules, using transistors. Verilog provides the ability to design at a MOS-transistor level. Design at this level is becoming rare with the increasing complexity of circuits(millions of transistors) and with the availabity of sophisticated CAD tools. Verilog HDL currently provides only digital design capability with logic values 0,1,x,z and the drive strengths associated with them. There is no analog capability. Thus is analog transistors are known as switches that either conduct or ar open.

3.2.4.1 Cmos(complimentary metal oxide semiconducator)

Complementary metaloxidesemiconductor (CMOS) is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for several analog circuits such as image sensors, data converters, and highly integrated transceivers for many types of communication. Frank Wanlass successfully patented CMOS in 1967 (US patent 3,356,858. CMOS is also sometimes referred to as complementary-symmetry metaloxidesemiconductor (or COS-MOS). The words "complementary-symmetry" refer to the fact that the typical digital design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions. Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Significant power is only drawn while the transistors in the CMOS device are switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic, which uses all n-channel devices without p-channel devices. CMOS also allows a high density of 38 | P a g e

ROLL NO.-RE2R55B33 logic functions on a chip. It was primarily this reason why CMOS won the race in the eighties and became the most used technology to be implemented in VLSI chips

3.2.4.2 CMOS inverter

An inverter (also referred to as NOT gate) is a logic gate with an output that is the complement of its input. Transistor level structure of this gate, its logic symbol, its algebraic notations, and its truth table are shown in Figure 2.2. In the transistor structure shown in this figure, if a is 0, the upper transistor conducts and w becomes 1. If a is 1, there will be a conduction path from w to Gnd which makes it 0. The table shown in Figure 2.2 is called the truth table of the inverter and lists all possible input values and their corresponding outputs. The inverter symbol is a bubble that can be placed on either side of a triangle representing a buffer.

CMOS Inverter (NOT gate) 3.3 FPGA(Field Programmable Gate Array) A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturinghence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). FPGAs can be used to implement any logical function that an ASIC could perform. The ability to update the functionality after shipping, partial re-configuration of a portion of the design and the low non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together" somewhat like many (changeable) logic gates that can be inter-wired in (many) different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.In addition to digital functions, some FPGAs have analog features. The most common analog feature is programmable slew rate and drive strength on each output pin, allowing the engineer to set slow rates on lightly loaded pins that would 39 | P a g e

ROLL NO.-RE2R55B33 otherwise ring unacceptably, and to set stronger, faster rates on heavily loaded pins on highspeed channels that would otherwise run too slow.Another relatively common analog feature is differential comparators on input pins designed to be connected to differential signaling channels. A few "mixed signalFPGAs" have integrated peripheral analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) with analog signal conditioning blocks allowing them to operate as a system-on-a-chip.[5] Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric, and field-programmable analog array (FPAA), which carries analog values on its internal programmable interconnect fabric.

3.3.1 FPGA Comparisons

Historically, FPGAs have been slower, less energy efficient and generally achieved less functionality than their fixed ASIC counterparts. A study has shown that designs implemented on FPGAs need on average 40 times as much area, draw 12 times as much dynamic power, and are three times slower than the corresponding ASIC implementations. Advantages include the ability to re-program in the field to fix bugs, and may include a shorter time to market and lower non-recurring engineering costs. Vendors can also take a middle road by developing their hardware on ordinary FPGAs, but manufacture their final version so it can no longer be modified after the design has been committed. Xilinx claims that several market and technology dynamics are changing the ASIC/FPGA paradigm: Integrated circuit costs are rising aggressively. ASIC complexity has lengthened development time. R&D resources and headcount are decreasing. Revenue losses for slow time-to-market are increasing. Financial constraints in a poor economy are driving low-cost technologies. These trends make FPGAs a better alternative than ASICs for a larger number of highervolume applications than they have been historically used for, to which the company attributes the growing number of FPGA design starts. Some FPGAs have the capability of partial re-configuration that lets one portion of the device be re-programmed while other portions continue running.

3.3.2 FPGA Architecture

The most common FPGA architecture consists of an array of logic blocks (called Configurable Logic Block, CLB, or Logic Array Block, LAB, depending on vendor), I/O pads, and routing channels. Generally, all the routing channels have the same width (number of wires). Multiple I/O pads may fit into the height of one row or the width of one column in the array.

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ROLL NO.-RE2R55B33 An application circuit must be mapped into an FPGA with adequate resources. While the number of CLBs/LABs and I/Os required is easily determined from the design, the number of routing tracks needed may vary considerably even among designs with the same amount of logic. For example, a crossbar switch requires much more routing than a systolic array with the same gate count. Since unused routing tracks increase the cost (and decrease the performance) of the part without providing any benefit, FPGA manufacturers try to provide just enough tracks so that most designs that will fit in terms of Lookup tables (LUTs) and IOs can be routed. This is determined by estimates such as those derived from Rent's rule or by experiments with existing designs. In general, a logic block (CLB or LAB) consists of a few logical cells (called ALM, LE, Slice etc.). A typical cell consists of a 4-input LUT, a Full adder (FA) and a D-type flip-flop, as shown below. The LUTs are in this figure split into two 3-input LUTs. In normal mode those are combined into a 4-input LUT through the left mux. In arithmetic mode, their outputs are fed to the FA. The selection of mode is programmed into the middle multiplexer. The output can be either synchronous or asynchronous, depending on the programming of the mux to the right, in the figure example. In practice, entire or parts of the FA are put as functions into the LUTs in order to save space.

Simplified example illustration of a logic cell. ALMs and Slices usually contains 2 or 4 structures similar to the example figure, with some shared signals.CLBs/LABs typically contains a few ALMs/LEs/Slices.In recent years, manufacturers have started moving to 6-input LUTs in their high performance parts, claiming increased performance. Since clock signals (and often other high-fanout signals) are normally routed via specialpurpose dedicated routing networks in commercial FPGAs, they and other signals are separately managed. For this example architecture, the locations of the FPGA logic block pins are shown below.

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Logic Block Pin Locations Each input is accessible from one side of the logic block, while the output pin can connect to routing wires in both the channel to the right and the channel below the logic block. Each logic block output pin can connect to any of the wiring segments in the channels adjacent to it. Similarly, an I/O pad can connect to any one of the wiring segments in the channel adjacent to it. For example, an I/O pad at the top of the chip can connect to any of the W wires (where W is the channel width) in the horizontal channel immediately below it. Generally, the FPGA routing is unsegmented. That is, each wiring segment spans only one logic block before it terminates in a switch box. By turning on some of the programmable switches within a switch box, longer paths can be constructed. For higher speed interconnect, some FPGA architectures use longer routing lines that span multiple logic blocks. Whenever a vertical and a horizontal channel intersect, there is a switch box. In this architecture, when a wire enters a switch box, there are three programmable switches that allow it to connect to three other wires in adjacent channel segments. The pattern, or topology, of switches used in this architecture is the planar or domain-based switch box topology. In this switch box topology, a wire in track number one connects only to wires in track number one in adjacent channel segments, wires in track number 2 connect only to other wires in track number 2 and so on. The figure below illustrates the connections in a switch box.

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Switch box topology Modern FPGA families expand upon the above capabilities to include higher level functionality fixed into the silicon. Having these common functions embedded into the silicon reduces the area required and gives those functions increased speed compared to building them from primitives. Examples of these include multipliers, generic DSP blocks, embedded processors, high speed IO logic and embedded memories. FPGAs are also widely used for systems validation including pre-silicon validation, postsilicon validation, and firmware development. This allows chip companies to validate their design before the chip is produced in the factory, reducing the time-to-market. To shrink the size and power consumption of FPGAs, vendors such as Tabula and Xilinx have introduced new 3D or stacked architectures. Following the introduction of its 28 nm 7-series FPGAs, Xilinx revealed that several of the highest-density parts in those FPGA product lines will be constructed using multiple dice in one package, employing technology developed for 3D construction and stacked-die assemblies. The technology stacks several (three or four) active FPGA dice side-by-side on a silicon interposer a single piece of silicon that carries passive interconnect.

3.3.3 FPGA Design and Programming

To define the behavior of the FPGA, the user provides a hardware description language (HDL) or a schematic design. The HDL form is more suited to work with large structures because it's possible to just specify them numerically rather than having to draw every piece by hand. However, schematic entry can allow for easier visualisation of a design.Then, using an electronic design automation tool, a technology-mapped netlist is generated. The netlist can then be fitted to the actual FPGA architecture using a process called place-and-route, usually performed by the FPGA company's proprietary place-androute software. The user will validate the map, place and route results via timing analysis, simulation, and other verificationmethodologies. Once the design and validation 43 | P a g e

ROLL NO.-RE2R55B33 process is complete, the binary file generated (also using the FPGA company's proprietary software) is used to (re)configure the FPGA. This file is transferred to the FPGA/CPLD via a serial interface (JTAG) or to an external memory device like an EEPROM.The most common HDLs are VHDL and Verilog, although in an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of assembly languages, there are moves to raise the abstraction level through the introduction of alternative languages. National Instrument's LabVIEW graphical programming language (sometimes referred to as "G") has an FPGA add-in module available to target and program FPGA hardware.To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. These predefined circuits are commonly called IP cores, and are available from FPGA vendors and third-party IP suppliers (rarely free, and typically released under proprietary licenses). Other predefined circuits are available from developer communities such as OpenCores (typically released under free and open source licenses such as the GPL, BSD or similar license), and other sources. In a typical design flow, an FPGA application developer will simulate the design at multiple stages throughout the design process. Initially the RTL description in VHDL or Verilog is simulated by creating test benches to simulate the system and observe results. Then, after the synthesis engine has mapped the design to a netlist, the netlist is translated to a gate level description where simulation is repeated to confirm the synthesis proceeded without errors. Finally the design is laid out in the FPGA at which point propagation delays can be added and the simulation run again with these values backannotated onto the netlist.

3.4 CPLD(Complex Programmable Logic Device)

The primary differences between CPLDs (Complex Programmable Logic Devices) and FPGAs are architectural. A CPLD has a somewhat restrictive structure consisting of one or more programmable sum-of-products logic arrays feeding a relatively small number of clocked registers. The result of this is less flexibility, with the advantage of more predictable timing delays and a higher logic-to-interconnect ratio. The FPGA architectures, on the other hand, are dominated by interconnect. This makes them far more flexible (in terms of the range of designs that are practical for implementation within them) but also far more complex to design for.In practice, the distinction between FPGAs and CPLDs is often one of size as FPGAs are usually much larger in terms of resources than CPLDs. Typically only FPGA's contain more advanced embedded functions such as adders, multipliers, memory, serdes and other hardened functions. Another common distinction is that CPLDs contain embedded flash to store their configuration while FPGAs usually, but not always, require an external flash.

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4. HARDWARE/ SOFTWARE IMPLIMENATION 4.1 EDA(Electronic Design Automation) tools

Electronic design automation (also known as EDA or ECAD) is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chip.

4.1.1 History of EDA tools

1981 marks the beginning of EDA as an industry. For many years, the larger electronic companies, such as Hewlett Packard, Tektronix, and Intl, had pursued EDA internally. In 1981, managers and developers spun out of these companies to concentrate on EDA as a business. Daisy Systems, Mentor Graphics, and Valid Logic Systems were all founded around this time, and collectively referred to as DMV. Within a few years there were many companies specializing in EDA, each with a slightly different emphasis. In 1986, Verilog, a popular high-level design language, was first introduced as a hardware description language by Gateway Design Automation. In 1987, the U.S. Department of Defense funded creation of VHDL as a specification language. Simulators quickly followed these introductions, permitting direct simulation of chip designs: executable specifications. In a few more years, back-ends were developed to perform logic synthesis.

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4.1.2 Current status

Current digital flows are extremely modular (see Integrated circuit design, Design closure, and Design flow (EDA)). The front ends produce standardized design descriptions that compile into invocations of "cells,", without regard to the cell technology. Cells implement logic or other electronic functions using a particular integrated circuit technology. Fabricators generally provide libraries of components for their production processes, with simulation models that fit standard simulation tools. Analog EDA tools are far less modular, since many more functions are required, they interact more strongly, and the components are (in general) less ideal. EDA for electronics has rapidly increased in importance with the continuous scaling of semiconductor technology.Some users are foundry operators, who operate the semiconductor fabrication facilities, or "fabs", and design-service companies who use EDA software to evaluate an incoming design for manufacturing readiness. EDA tools are also used for programming design functionality into FPGAs

4.2 Software focuses on Design

High-level synthesis(syn. behavioural synthesis, algorithmic synthesis) For digital chips Logic synthesis translation of abstract, logical language such as Verilog or VHDL into a discrete netlist of logic-gates Schematic Capture For standard cell digital, analog, rf like Capture CIS in Orcad by CADENCE and ISIS in Proteus Layout like Layout in Orcad by Cadence, ARES in Proteus

4.3 Modelsim simulator

Modelsim simulator is used for the designing and simulation of circuit design.

4.3.1 Introduction:
ModelSim is a verification and simulation tool for VHDL, Verilog, SystemVerilog, and mixedlanguage designs.This lesson provides a brief conceptual overview of the ModelSim simulation environment.It isdivided into fourtopics, which you will learn more about in subsequent lessons. Basic simulation flow. Project flow . Multiple library flow 46 | P a g e

ROLL NO.-RE2R55B33 Debugging tools Basic simulation 1. 2. 3. 4. Create a working library Compile design files Load and Run simulation Debug results

4.3.2 Creating the working library

In ModelSim, all designs are compiled into a library. You typically start a new simulation in ModelSim by creating a working library called "work". "Work" is the library name used by the compiler as the default destination for compiled design units. Compiling Your Design After creating the working library, you compile your design units into it. The ModelSimlibrary format is compatible across all supported platforms. You can simulate yourdesign on any platform without having to recompile your design. Loading the Simulator with Your Design and Running the SimulationWith the design compiled, you load the simulator with your design by invoking thesimulator on a top-level module (Verilog) or a configuration orentity/architecture pair(VHDL). Assuming the design loads successfully, the simulation time is set to zero, and you entera run command to begin simulation. Debugging Your Results If you dont get the results you expect, you can use ModelSims robust debugging environment to track down the cause of the problem.

4.3.3 Project flow

A project is a collection mechanism for an HDL design under specification or test. Even though you dont have to use projects in ModelSim, they may ease interaction with the tool and are useful for organizing files and specifying simulation settings. The following flow shows the basic steps for simulating a design within a ModelSim project. 47 | P a g e Create a project

ROLL NO.-RE2R55B33 Add files to the project Compile design files Run simulations Debug results

As you can see, the flow is similar to the basic simulation flow. However, there are twoimportant differences: You do not have to create a working library in the project flow; it is done for you automatically. Projects are persistent. In other words, they will open every time you invoke ModelSim unless you specifically close them.

4.3.4 Multiple library flow

ModelSim uses libraries in two ways: 1) as a local working library that contains the compiled version of your design; 2) as a resource library. The contents of your working library will change as you update your design and recompile. A resource library is typically static and serves as a parts source for your design. You can create your own resource libraries, or they may be supplied by another design team or a third party (e.g., a silicon vendor). You specify which resource libraries will be used when the design is compiled, and there are rules to specify in which order they are searched. A common example of using both a working library and a resource library is one where your gate-level design and testbench are compiled into the working library, and the design references gate-level models in a separate resource library. The flow below shows the basic steps for simulating with multiple libraries. 1. 2. 3. 4. 5. Create the working library Compile the design files Link to resources library Run simulations Debug results

You can also link to resource libraries from within a project. If you are using a project, you would replace the first step above with these two steps: create the project and add the testbench to the project.

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5. SIMULATIVE/ HARWARE ANALYSIS 5.1 UART

Universal Asynchronous Receiver and Transmitter. A serial communication protocol that sends parallel data through a serial line. Typically used with RS-232 standard. Your FPGA boards have an RS-232 port with a standard 9-pin connector. The voltages of the FPGA and serial port are different, and therefore a levelconverter circuit is also present on the board. The board handles the RS-232 standard and therefore our focus is on the UART. The UART includes both a transmitter and receiver. The transmitter is a special shift register that loads data in parallel and then shifts it out bit-by-bit. The receiver shifts in data bit-by-bit and reassembles the data byte. The data line is 1 when idle.

5.2 UART Specifications

Transmission starts when a start bit (a 0) is sent, followed by a number of data bits (either 6, 7 or 8), an optional partity bit and stop bits (with 1, 1.5 or 2 1s). This is the transmission of 8 data bits and 1 stop bit. Note that no clk signal is sent through the serial line. This requires agreement on the transmission parameters by both the transmitter and receiver in advance. This information includes the band rate (number of bits per second), the number 49 | P a g e

ROLL NO.-RE2R55B33 of data bits and stop bits, and whether parity is being used. Common baud rates are 2400, 4800, 9600 and 19,200.

5.3 UART Receiving Subsystem

An oversampling scheme is commonly used to locate the middle position of the transmitted bits, i.e., where the actual sample is taken.The most common oversampling rate is 16 times the baud rate. Therefore, each serial bit is sampled 16 times but only one sample is saved as we will see. The oversampling scheme using N data bits and M stop bits: Wait until the incoming signal becomes 0 (the start bit) and then start the sampling tick cnter. When the cnter reaches 7, the incoming signal reaches the middle position of the start bit. Clear the cnter and restart. When the cnter reaches 15, we are at the middle of the first data bit. Retrieve it and shift into a register. Restart the cnter. Repeat the above step N-1 times to retrieve the remaining data bits. If optional parity bit is used, repeat this step once more. Repeat this step M more times to obtain the stop bits. The oversampling scheme replaces the function of the clock. Instead of using the rising edge to sample, the sampling ticks are used to estimate the center position of each bit. Note that the system clock must be much faster than the baud rate for oversampling to be possible. The receiver block diagram consists of three components.

The interface circuit provides a buffer and status between the UART and the computer or FPGA.

5.4 UART Transmitting Subsystem

The UART transmitting subsystem is similar to the receiving subsystem. It consists of UART transmitter, baud rate generator and interface circuit. Roles are reversed for the interface circuit, i.e., the system sets the flag FF or writes the buffer interface circuit while the UART transmitter clears FF or reads the buffer. The transmitter is essentially a shift register that shifts out data bits. Since no oversampling is involved, the frequency of the ticks are 16 times slower than that of the receiver. 50 | P a g e

ROLL NO.-RE2R55B33 However, instead of introducing another cnter, the transmitter usually shares the baud rate generator and uses an internal cnter to cnt through the 16 ticks.

5.5 Entire UART System

Block diagram of whole system

6. REFERENCES Wikipedia Verilog HDL Samir Palnitkar www.verilog.com www. fpgacpu.org

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7. FUTURE SCOPE OF TRAINING

In the era of rapid change in technologies the Indian electronics and communication landscape is expanding every year and more and more new projects are emerging in the field of VLSI Design. It requires a large pool of highly skilled and technically sound engineers who can execute these projects. This is an area of concern at PG Level. The VLSI Design is an advanced level course in the field of Electronics & Communication engineering in masters with specialization in terms of technology and application to fulfill the requirements of the industry. VLSI design a huge scope for Indian engineers. Students who have strong electronics background and an engineer degree either in electronics, computer science,electrical etc. are eligible for a career in VLSI design.

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