CSSE3000 Digital System Design I

Clocking sequential logic

Combinational logic
tcomb(max)
D1

B
D2 Q2

Lecture 12
A Q1

FF2
Q2

Timing aspects of digital design

CLOCK

FF1
Q1

tcomb(min)

D2

Q2

FF2
Q2

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Setup and Hold Times

CLOCK

Timing diagram

tHIGH clock
There must be no change in input during this window
flip flop outputs
change

tclk tFF(max) FF(max)

change

tLOW
change

input ts th

combinational outputs flip flop inputs

change

tcomb(max) comb(max)
change change

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tsetup

thold
4

Timing calculations
Change regions indicate minimum to maximum propagation delays. For correct operation we must have: t clk - (t FF + t comb) > t setup The setup-time margin is defined as: setupt clk - (t FF(max) + t comb(max) + t setup) If this is negative, the circuit wont work. Note the use of maximum propagation delay.

Timing calculations
The hold time margin is defined as: t FF(min) + t comb(min) - t hold This, too, must be greater than or equal to zero. Note the use of minimum propagation delays.

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Clock skew
Synchronous systems using edge-triggered flip-flops work properly only if all flip-flops see the triggering clock edge at the same time. This difference between arrival times of the clock at different devices is called clock skew. How can this difference occur: In large systems, a single clock signal may not have adequate fanout to drive all the devices with clock inputs, so that it may be necessary to provide two or more copies of the clock signal.

Clock Skew
Illustrative Circuit Example:
74LS74

combinational logic: tcomb(max) comb(max)

74LS74

C
A D1 Q1

D2

Q2

FF1
Q1 CLOCKD CLOCK

FF2
Q2

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Delay: tskew(max) skew(max)

Clock Skew Timing

CLOCK

Maximum Clock Skew

We can determine quantitatively whether clock skew is a problem in a given system by defining t skew to be the amount of clock skew. For proper operation, we must have: tFF(min) + tcomb(min) - tH - tskew(max) > 0 FF(min) comb(min) skew(max)

tP Best through FF2

Q1 OUTPUT DATA C INTO FF2
PREVIOUS DATA OUTPUT CHANGING VALID OUTPUT

tP
tH

Best through comb. logic

C CHANGING C VALID

Earliest that C can change

CLOCKD (SAFE)

tskew
CLOCKD (MAXIMUM SKEW)

tH

FF2 Hold Time

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Buffering the Clock - I

The following method results in clock skew: Controllable clock skew:

Clock Skew
Good designers take care to balance the loads on multiple clocks, looking at both DC load (fanout) and AC load (wiring and input capacitance). Clock skew occurs if one clock signal is loaded much more heavily than the other; transitions on the more heavily loaded clock appear to occur later because of increases in output-transistor switching delay and signal rise and fall times.

CLOCK1 CLOCK CLOCK2 CLOCK3 CLOCK

CLOCK1 CLOCK2 CLOCK3

Different ICs

BAD

GOOD

Same IC

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Hazards
Timing anomalies in combinational circuits 1 0 1-> 1 (a) Static hazard 1 0 1 -> 0 0 ->1 (b) Dynamic hazard
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x2

Static Hazards
x1 p f

0 -> 0

x3

x2 x1 x3 p q f 5 5 5 5 5 5 5 5 5 5 5 5 5 5ns

(a) Circuit with a hazard x1 x2 00 0 1 1 1 01 11 1 1 10

x3

x2 x1 f

x3

(b) Karnaugh map

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Static Hazard
x1 x2 p f x3 q

Dynamic Hazard
One gate delay x1 x2, x3, x4 a b c d f (b) Timing diagram

x1 x2 x3 p q f

b x1 x2 a c x3 x4 (a) Circuit x3 f (c) Hazard-free circuit d f

(a) Circuit with a hazard x1 x2 00 0 1 0 0 01 0 1 11 0 1 10 1 1

5 5 5 5 5 5 5 5 5 5 5 5 5 5ns
x1 x2

x3

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HAZARDS
Static hazards can always be avoided in two-level circuits by inserting additional products. There must be a static hazard for the dynamic hazard to occur. Dynamic hazards occur in multilevel circuits. Prevention: - use two-level circuits (not always possible) - use synchronous design - always latch the outputs which are used to control other blocks of the design

State diagrams and Timing Diagrams

How to build a timing diagram from state diagram Mealy and Moore OUTPUTS How to deal with Mealy spikes and combinational hazard spikes Will be covered in detail the tutorial next week

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Mealy and Moore outputs

Z E A !Z/out2 !Z/out1 Z C out3 !Z B D out1
clock state Z out1 --

Timing Diagram
out1

Z E A !Z !Z/out1 Z C B Z D out3

!Z/out2

out2 out3

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Clock gating
AVOID IF POSSIBLE !!! Gate the clock for the whole well defined module Legitimate use: optimising power consumption Frivolous use: cascading counters USE with CARE, and only after thorough analysis
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Clock gating
CLOCK GCLK CLKEN CLKEN GCLK CLOCK

WRONG because: If CLKEN is a state machine output or other signal produced by a register clocked by CLOCK, then CLKEN changes some time after CLOCK has already gone HIGH. This produces glitches on GCLK, and false clocking of the registers controlled by GCLK.

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Safer clock gating

Clock gate signal generated in the system from the falling edge of clock. The rising edge is used for clocking the gated module.
Same IC package similar delays
CLOCK GCLK1 GCLK2 GCLK3 /CLOCK CLOCK CLKEN

Summary
Timing is more difficult than logic ! Timing is related to electrical properties Logic simulation is not enough to assure that integrated circuit will behave as expected Extensive timing simulations are performed after physical synthesis is made only then good approximations of delays are known More on timing later in the course

/CLOCK CLKEN1 CLKEN2 CLKEN3

GCLK

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