Building a Battery Operated Auto Ranging DVM with the ICL7106

Application Note AN046

Larry Goff

Introduction
In the eld of DVM design, three areas are being addressed with vigor: size, power dissipation, and novelty. The handheld portable multimeter has gained in popularity since low power dissipation devices enabled battery operation, LSI A/D converters reduced IC count, and novelties such as conductance, automatic range scaling, and calculating were included to entice the user. This application note describes a technique for auto-ranging a battery operated DVM suitable for panel meter applications. Also, circuit ideas will be presented for conductance and resistance measurement, 9V battery and 5V supply operations, and current measurement.

Input Divider Network

A simplied drawing of the divider network is shown in Figure 2. This conguration was chosen for simplicity and implementation using analog switches. The low leakage ID101s are used for input protection, and the second set of switches to IN LO reduces the net error due to switch resistance. This can be seen calculating IN HI and IN LO voltages for the two equivalent circuits. For equivalent circuit A,
RS + R K V MEAS = V IN HI = ------------------------------------ V IN R S + R + R K (EQ. 1)

Auto Ranging Circuitry

The control signals necessary for auto-ranging are overrange, under-range, and clock. The over-range and underrange inputs control the direction of a scale shift, becoming active at the completion of an invalid conversion and remaining active until a valid conversion occurs. The clock input controls the timing of a scale shift. This signal should occur only once per conversion cycle, during a time window which will not upset an ongoing conversion and must be disabled after valid conversions. In the circuit of Figure 1, inverted over-range (O/R) and under-range (U/R) are generated by detecting the display reading. The ICL7106 turns the most signicant digit on and blanks the rest to indicate an over-range. An under-range occurs if the display reads less than 0100. R1C1 and R2C2 are required to deglitch O/R and U/R. The next step in the logic disables O/R and U/R prior to shifting into nonexistent ranges. O/R is disabled when in the 200V range, while U/R is disabled when in the 200mV range. The next level of gating disables the clock if the conditions are as described above and a valid conversion state exists. Clock is enabled only when a range shift is called for and there exists a valid range to shift into. The CD4029 is a four bit up/down counter, used as a register to hold the present state and as a counter to shift the scale as directed by the control inputs. The CD4028 is a BCD to decimal decoder interfacing the CD4029 and ladder switches. An additional exclusive OR gate package is added to drive the appropriate decimal point.

where RS = switch resistance, R = input resistance (1M), and 1 + K is the desired divider ratio. Ideally VINHI should be
RK 1 V IDEAL = ---------------------- V IN = ------------ V IN R K + R 1 + K (EQ. 2)

Therefore the percent error is:

Ideal Actual --------------------------------------- 100, Ideal R S + R/K or 1 ( 1 + K ) ---------------------------------- 100 R S + R/K + R (EQ. 3)

(EQ. 4)

The worst case error occurs at (1+K) = 1000. For this example, the error due to a 1kW switch resistance is 99.7%. IN HI for equivalent circuit B is the same as Equation 1. However, IN LO for circuit B is:
RS ------------------------------------ V IN , R S + R + R K (EQ. 5)

and combining Equations (1) and (5)

RK V MEAS = V INHI V INLO = ------------------------------------ V IN R + R + R K S (EQ. 6)

The percent error is equal to:

R/K 1 ( 1 + K ) ---------------------------------- 100 R + R + R/K
S

(EQ. 7)

Using the same values for RS, (1+K), and R, the worst case error is 0.1%. This error can be further improved if lower rDS(ON) switches are used. From the results calculated above, the worst case conversion error due to switch resistance will be one count of the least signicant digit for a full scale input, and a slight adjustment to R itself will correct the remaining error on all scales.

1-888-INTERSIL or 321-724-7143 | Copyright

Intersil Corporation 1999

V+ 1 2 V+ 3 4 5 6 7 ICL7106 PIN26 V8 9 V+ D1 C1 B1 A1 F1 G1 E1 D2 OSC 1 OSC 2 OSC 3 TEST REF HI REF LO CREF CREF COMMON IN HI IN LO A-Z BUFF INT VG2 C3 A3 G3 BP 40 39 38 100pF CLOCK A/Z CREF 100k

37 DIG GND 36 35 1F 34 24k 33 32 31 30 29 28 27 26 25 24 23 22 21 V0.47F 47k 3N169 N CH. 0.01F 47M R8 5.1k D1 Q2 D S D Q1 S 20k 22k 1k

C3 0.1F

2
D 3 1 10 4011 3 13 12 4011 11 4011 1 2 4011 6 4 A 8 9 74C32 5 2 C1 R1 TEST TEST 1 2 3 4 CD4029BC 5 6 7 8 V
C1

10 C2 11 B2 12 A2 13 F2 14 E2 10k 6 O/RANGE 3 4 4023 3 11 4 12 13 10 2 1 5 6 8 9 12 11 13 15 D3 16 B3 17 F3 18 E3 19 AB4 20 POL

2N3702 Q3 100k

1M

D2

0.22F

Application Note 046

TEST

4023 5 10 0.005F TEST O/RANGE 1 10k 2 8

R2 9 4023 C2 0.005F

VIN

C ID101 V+ PE V+ 16 CLK 15 14 13 12 Q7 11 UP/DOWN 10 BINARY 9 DECODE 1 2 3 4 CD402T 5 6 7 8 V C 12 D 11 A A 10 9 BACK PLANE DECODER ARROW 1 2 B 5 C 6 8 9 12 A OR D 13 5, 13 12 TEST UP/DOWN COUNTER 8 6 CD4016 TEST 2 O V+ 16 3 15 1 14 B 13 6, 12 1 2 B A V+ D 13, 5 4 8 CD4016 9 R1 R2 R3 1.001k 3 R4 R6 VIN 1M

10.1k 10 11 R5 3 4 111.1k

Q1

10 11 9

OPEN OPEN

FIGURE 1. AUTO RANGING CIRCUITRY

Application Note 046

R IN HI ID101 VIN IN LO R/999 R/99.01 R/9

SWITCH CONTROL LINES 200V 20V 2V 200mV

FIGURE 2A.

+ R TO IN HI VIN R/K VMEAS R SWITCH

+ R TO IN HI VIN R/K VMEAS TO IN LO R SWITCH TO IN LO

FIGURE 2B. EQUIVALENT CIRCUIT A (SWITCHES TO IN LO REMOVED)

FIGURE 2C. EQUIVALENT CIRCUIT B (SWITCHES TO IN LO INCLUDED) FIGURE 2. INPUT DIVIDER NETWORK

Ranging Clock Circuit

Two N-Channel MOSFETs, a PNP transistor and a handful of passive components combine to generate the clock signal used to gate the auto-ranging logic. A closer look at the inner workings of the ICL7106 will help clarify the discussion of this circuit. The analog section of the ICL7106 is shown in Figure 3. It can be shown that CREF low (pin 33 of ICL7106) will sit at -VREF for DE+ and at common for DE-, with DE+ designating the deintegrate phase for a positive input signal and DE- referring to a negative input signal. During the autozero phase, CREF low is tied to an external reference through pin 35, which in Figure 1 is VREF below the positive supply. The net result is that CREF low is above COMMON during auto-zero, is left to oat during signal integrate, and is at or below COMMON during deintegrate. R8 and D1 are added externally to pull CREF to COMMON during integrate, with Q2 and R1 included to speed this action. The signal at CREF low is now a square wave that is high during auto-zero and low at all other times. Q1 and Q3 amplify and level shift this waveform for logic level compatibility. This clock signal is

gated through D2 and controls the timing of the auto-ranging circuitry. C3 is added to delay the clock, eliminating disparity with O/R and U/R (see Figure 4 for timing diagram).

Application Note 046

CREF RINT CREF+ V+ 34 REF HI 36 A-Z 10A 31 IN HI INT DEDE+ INPUT HIGH 6.2V A-Z 2.8V REF LO 35 A-Z CREF 33 BUFFER 28 V+ 1 29 INTEGRATOR
+

CAZ A-Z

CINT INT 27

TO DIGITAL SECTION

A-Z N 32 COMMON INT 30 IN LO 26 VA-Z AND DE() INPUT LOW DE+ DE+

COMPARATOR

FIGURE 3. ANALOG SECTION OF ICL7106

INTEGRATOR A/Z OVER-RANGE CONVERSION A/Z VALID CONVERSION A/Z

CREF LOW (PIN 33)

CLOCK

O/R, U/R

FIGURE 4. TIMING DIAGRAM

Supply Requirements
The circuit of Figure 1 operates on a standard 9V transistor battery. CMOS logic and a CMOS A/D converter (ICL7106) are used to extend battery life; the approximate power drain for this circuit is 8mW. The circuit in Figure 5 can also be added to detect low supply voltage. The circuit of Figure 6 can be used to generate 5V from a single 5V supply. The ICL7660 is a voltage converter which takes a 5V input and produces a -5V output. With respect to common mode signals, the circuit of Figure 1 will have innite common mode handling capability if operated from a oating 9V battery. However, if powered by a xed supply such as in Figure 6, the common mode capability of the

converter will be limited to approximately 2V, if COMMON is disconnected from -VIN.

Application Note 046

For transconductance measurement, merely switch RSTD and RX. This scheme makes the measurement of large resistors, in conductance form, convenient and easy. This is also convenient for leakage measurements. A simple current meter can be built using the circuit of Figure 8. The low leakage of the ICL7106 (10pA/max) makes possible the measurement of currents in the mid pico-Amp range. However, the switch leakage current will limit the accuracy of the resistor network and may degrade converter resolution.

1M 1 2 3 4 FIG 7 180K TO DISPLAY INDICATOR BACKPLANE TEST ICL8211 8 7 6 5 1M

FIGURE 5. LOW VOLTAGE DETECTOR

+5V NC 1 2 + 10F ICL7660 3 4 6 NC 5 10F -5V R 8 7 NC 90R AUTO-RANGING DVM CIRCUIT IIN 9R IN LO ICL7106 900R IN HI

FIGURE 6. GENERATING 5V FROM +5V

Resistance, Transconductance and Current Circuits

The purpose of this section is to show the simplicity of measuring transconductance (1/R) and resistance with the ICL7106. The circuit of Figure 7 requires only one precision resistor per decade range of interest. The conversion output is described by the formula:
RX --------------- 1000 R STD
V+

FIGURE 8. CURRENT METER

Using the ICL7126 and ICL7107

With a few modications, the circuit of Figure 1 can easily be adapted for use with either the low power ICL7126 or the ICL7107. Using the ICL7126 simply requires a change in the values of the integrating and auto-zero components. Refer to the ICL7126 data sheet for details. The ICL7107 is an LED version of the ICL7106, and is a bit trickier to use in this application. First the over-range/underrange logic must be changed slightly. Simply replace the quad exclusive-NOR with an LM339; connect the outputs, as before, to the CD4023 triple 3-input NAND. Second, the ICL7107 requires +5V and -5V rather than the +9V battery used in Figure 1. If battery operation is desired, the negative supply can be derived from 4 Ni-Cad cells in series and an ICL7660 (see Figure 9). Note that both supplies oat with respect to the input terminals. (Logic supplies are V+ and DIG. GND.)

(EQ. 8)

REF HI RSTD REF LO IN914 or IN4148 X4 ICL7106 IN HI RX IN LO

COMMON

FIGURE 7. TRANSCONDUCTANCE AND RESISTANCE MEASUREMENT

Application Note 046

ICL7107 +5V ICL7660 1 2 + 10F 3 4 8 7 6 5 + 10F -5V 12k 1 V3 2 D1 3 C1 4 B1 5 A1 6 F1 7 G1 8 E1 9 D2 10 C2 11 B2 12 A2 13 F2 + 14 E2 15 D3 16 B3 + U /RANGE + 17 F3 18 E3 19 AB4 20 POL CD4023 OR 74C10 + LM339 33k OSC 1 40 OSC 2 39 OSC 3 38 TEST 37 REF HI 36 REF LO 35 CREF 34 CREF 33 COMMON 32 IN HI 31 IN LO 30 A-Z 29 BUFF 28 INT 27 V- 26 G2 25 C3 24 A3 23 G3 22 GND 21 NEGATIVE (0V) LOGIC SUPPLY -5V

O /RANGE

FIGURE 9. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNALS FROM ICL7107 OUTPUTS. THE LM339 IS REQUIRED TO ENSURE LOGIC COMPATIBILITY WITH HEAVY DISPLAY LOADING

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certication.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Ofce Headquarters

NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: ( 321) 724-7000 FAX: ( 321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029