80x86 Processor Instruction Set (Intel 8086 AMD Athlon)

Integer Instruction Opcode, Mnemonic, Operand, and Abbreviation Legend: n This is a Number variable, which represents a range of the possible values for a particular instruction opcode or operand. i The operand is an Immediate constant, which is provided as part of the instruction itself. Also, it can be an address label. c A Code label, pointing to part of the program either jumped to or called. A byte is -128 to 127 bytes of the instruction,

a word is within the same code segment, and a doubleword (segment:offset) is within the 32-bit (4GB) address space. e This prefix is used to specify word/doubleword register, that depends on the presence of the operand override prefix byte. cc This represents a Conditional abbreviated mnemonic suffix defining which action is taken upon a true comparison result. r, reg The operand is a general-purpose Register, which may be a high/low byte, a word, or doubleword operand data type. m, mem A Memory variable or an indexed memory quantity; anything which is an Effective Address (except for a register). rm, reg/mem An Effective Address operand (general-purpose register, a memory variable, or an indexed memory quantity). moffsb, moffsv The operands are simple Memory variables (Offset) byte or word/doubleword relative to the segment base. dword, qword, dqword These abbreviations specify operand size meaning Doubleword, Quadword, or Double-quadword. xb, xw, xd, xv, xq, xdq, xp Define size Byte, Word, Dword, word/dword, Qword, packed DQword, or segment-offset Pair. sreg This is one of the segment registers (CS, DS, SS, ES, FS, GS), which is used as an operand data type in an instruction. v&v This is used in Bound instruction to specify a pair of signed word/dword integers, which are lower and upper bounds. SIMD The abbreviation means Simultaneous Instruction Multiple Data, used by the MMX, XMM, and SSE(2) instructions. mm, mn An MMX(0-7) 64-bit SIMD packed byte, word, doubleword, or quadword integer register. Also, used by SSE(2). xm, xn One of XMM(0-7) 128-bit SIMD packed/scalar single-/double-precision floating-point, or packed integer registers. B This abbreviation means Byte(s), that is used in the instruction description column to specify the size of the data operand. S This means Signed, which is an operand format that uses the most significant binary digit to indicate positive or negative. P This abbreviation means Packed, which describes the data operand storage format used in MMX and XMM instructions. O The abbreviation stands for Overflow, in which the operations destination operand does not have enough bits of storage. OS The abbreviation is for Operand-Size, which is a prefix override of the operand-size 16-/32-bits for the next instruction. TOS This means the Top Of Stack, that is the lowest word/doubleword on the stack frame, pointed to by the (E)SP register. Quo, Rem These abbreviations mean Quotient and Remainder; used in division and multiplication instruction descriptions. SP, DP; FP The first two stand for Single-Precision and Double-Precision, which are descriptions used with Floating-Point. CR, DR, TR The abbreviations mean Control Register, Debug Register, and Test Register; used with system instructions. GDTR, IDTR, LDTR These mean Global/Interrupt/Local Descriptor Table Register, which is used in system instructions. CPL, RPL These mean Current/Register Privilege Level, used by system instructions for segment protection mechanisms. TLB Used by INVLPG, is Translation Lookaside Buffer, an internal cache storing most recently used page-directory/table. SMM This abbreviation means System Management Mode, in which the context of current program is saved until resumed.

The Integer Instruction Set:

In the CPU column, the instructions level of processor support is given. The numbers 1, 2, 3, 4, and 5 are for the 186, 286, 386, 486, and Pentium. M is for MMX instructions, P2 for Pentium Pro/ Pentium II, P3 for Pentium III, P4 for Pentium IV, 3D is for AMD 3DNow!, and 3E for the DSP Extensions. The Athlon supports all Pentium III instructions except ones using SIMD registers. The instructions are listed by categories in alphabetical order in the divisions of: mnemonic, destination operand, and source operand. Opcode Instruction CP U Description FLAGS/FP Exceptions none none none none none none none none

Lock and Repeat Prefixes:

F0 F3 F3 F2 2E 3E 26 64 LOCK REP REPE/REPZ REPNE/REPNZ CS DS ES FS Assert LOCK# signal for the following instruction Repeat INSx, LODSx, MOVSx, OUTSx, STOSx CX times Repeat CMPSx or SCASx CX times or until ZF = 0 Repeat CMPSx or SCASx CX times or until ZF = 1 Use Code Seg next mem reference or Jcc hint (branch untaken) Use Data Seg next mem reference or Jcc hint (branch is taken) Use ES data segment for following memory reference Use FS data segment for following memory reference

Segment Override Prefixes:

65 36 66 or null 67 or null

GS SS O2/O4 A2/A4

Use GS data segment for following memory reference Use Stack Segment for following memory reference Use 16-/32-bit (2 or 4 byte) data Operand in next instruction Use 16-/32-bit (2 or 4 byte) Addressing in next instruction

none none none none

Operand-Size Override Prefix:

3 3

Address-Size Override Prefix:

Data Transfer Instructions:

0F C8+rd 98 99 0F 4n /r 0F B0 /r 0F B1 /r 0F C7 /1 mq 99 98 E4 ib EC E5 ib ED A0 iv A1 iv A2 iv A3 iv B0+rb ib 8A /r C6 /0 ib 88 /r C7 /0 iv 89 /r 8C /r B8+rv iv 8B /r 8E /r 0F BF /r 0F BE /r 0F B7 /r 0F B6 /r E6 ib E7 ib EE EF 1F 07 0F A1 0F A9 8F /0 58+rv 17 61 61 0E 1E 06 0F A0 0F A8 6A ib 68 iv FF /6 50+rv 16 60 60 0F C0 /r 0F C1 /r 90+rv BSWAP rd CBW CDQ CMOVcc rv, rmv CMPXCHG rmb, rb CMPXCHG rmv, rv CMPXCHG8B mq CWD CWDE IN AL, ib IN AL, DX IN eAX, ib IN eAX, DX MOV AL, moffsb MOV eAX, moffsv MOV moffsb, AL MOV moffsv, eAX MOV rb, ib MOV rb, rmb MOV rmb, ib MOV rmb, rb MOV rmv, iv MOV rmv, rv MOV rmw, sreg MOV rv, iv MOV rv, rmv MOV sreg, rmw MOVSX rd, rmw MOVSX rv, rmb MOVZX rd, rmw MOVZX rv, rmb OUT ib, AL OUT ib, eAX OUT DX, AL OUT DX, eAX POP DS POP ES POP FS POP GS POP mv POP rv POP SS POPA POPAD PUSH CS PUSH DS PUSH ES PUSH FS PUSH GS PUSH ib PUSH iv PUSH mv PUSH rv PUSH SS PUSHA PUSHAD XADD rmb, rb XADD rmv, rv XCHG eAX, rv 4 Byte Swap 1, 4 & 2, 3 of dword register to reverse byte order Convert Byte AL to Word AX (AH[15-0] bit 7) 3 Convert Dword EAX, Qword EDX:EAX (EDX[31-0] bit 7) P2 Conditional Move (see Jcc, all conditions valid except xECXZ) 4 If AL = rb, then AL rb, else AL rmb 4 If eAX = rv, then eAX rv, else eAX rmv 5 If EDX:EAX = mq, mq ECX:EBX, else EDX:EAX mq Convert Word AX to Dword DX:AX (DX[15-0] bit 7) 3 Convert Word AX to Dword EAX with sign-Extension Input byte from immediate port ib (0-255) into AL Input byte from port in DX (0-65,535) into AL Input vword from immediate port ib (0-255) into eAX Input vword from port in DX (0-65,535) into eAX Move byte at moffsb (segment:offset) into AL Move vword at moffsv (segment:offset) into eAX Move AL into byte at moffsb (segment:offset) Move eAX into vword at moffsv (segment:offset) Move immediate byte into byte register Move reg/mem byte into byte register Move immediate byte into reg/mem byte Move byte register into reg/mem byte Move immediate vword into reg/mem vword Move vword register into reg/mem vword Move segment reg into reg/mem word (OS prefix) Move immediate vword into vword register Move reg/mem vword into vword register Move reg/mem word to sreg, except CS (OS prefix) 3 Move reg/mem word to dword register and Sign-Extend 3 Move reg/mem byte to vword register and Sign-Extend 3 Move word to dword with Zero-Extension 3 Move byte to vword with Zero-Extension Output byte AL to immediate port number ib (0-255) Output word eAX to immediate port number ib (0-255) Output byte AL to port in DX (0-65,535) Output word eAX to port in DX (0-65,535) Pop TOS to DS register, eSP (eSP + 2) Pop TOS to ES register, eSP (eSP + 2) 3 Pop TOS to FS register, eSP (eSP + 2) 3 Pop TOS to GS register, eSP (eSP + 2) Pop TOS to mem vword, eSP (eSP + (2 or 4 (word/dword)) Pop TOS to vword reg, eSP (eSP + (2 or 4 (word/dword)) Pop TOS to SS register, eSP (eSP + 2) 1 Pop DI, SI, BP, BX, DX, CX, & AX (SP ignored) 3 Pop EDI, ESI, EBP, EBX, EDX, ECX, & EAX (ESP ignored) eSP (eSP - 2); Push CS register to TOS eSP (eSP - 2); Push DS register to TOS eSP (eSP - 2); Push ES register to TOS 3 eSP (eSP - 2); Push FS register to TOS 3 eSP (eSP - 2); Push GS register to TOS 1 Push sign-extended immediate byte to TOS 1 eSP (eSP + (2 or 4 (word/dword)); Push iv to TOS eSP (eSP + (2 or 4 (word/dword)); Push mem vword to TOS eSP (eSP + (2 or 4 (word/dword)); Push vword reg to TOS eSP (eSP - 2); Push SS register to TOS 1 Push AX, CX, DX, BX, original SP, BP, SI, & DI 3 Push EAX, ECX, EDX, EBX, original ESP, EBP, ESI, & EDI 4 Exchange rmb & rb; load sum to rmb (LOCK prefix) 4 Exchange rmv & rv; load sum to rmv (LOCK prefix) Exchange vword register with eAX none none none none CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF none

86 /r 86 /r 87 /r 90+rv 87 /r 14 ib 15 iv 12 /r 80 /2 ib 10 /r 83 /2 ib 81 /2 iv 11 /r 13 /r 04 ib 05 iv 02 /r 80 /0 ib 00 /r 83 /0 ib 81 /0 iv 01 /r 03 /r 3C ib 3D iv 3A /r 80 /7 ib 38 /r 83 /7 ib 81 /7 iv 39 /r 3B /r FE /1 FF /1 48+rv F6 /6 F7 /6 F6 /7 F7 /7 F6 /5 F7 /5 6B /r ib 69 /r iv 0F AF /r 6B /r ib 69 /r iv FE /0 FF /0 40+rv F6 /4 F7 /4 F6 /3 F7 /3 1C ib 1D iv 1A /r 80 /3 ib 18 /r 83 /3 ib

XCHG rb, rmb XCHG rmb, rb XCHG rmv, rv XCHG rv, eAX XCHG rv, rmv ADC AL, ib ADC eAX, iv ADC rb, rmb ADC rmb, ib ADC rmb, rb ADC rmv, ib ADC rmv, iv ADC rmv, rv ADC rv, rmv ADD AL, ib ADD eAX, iv ADD rb, rmb ADD rmb, ib ADD rmb, rb ADD rmv, ib ADD rmv, iv ADD rmv, rv ADD rv, rmv CMP AL, ib CMP eAX, iv CMP rb, rmb CMP rmb, ib CMP rmb, rb CMP rmv, ib CMP rmv, iv CMP rmv, rv CMP rv, rmv DEC rmb DEC rmv DEC rv DIV rmb DIV rmv IDIV rmb IDIV rmv IMUL rmb IMUL rmv IMUL rv, ib IMUL rv, iv IMUL rv, rmv IMUL rv, rmv, ib IMUL rv, rmv, iv INC rmb INC rmv INC rv MUL rmb MUL rmv NEG rmb NEG rmv SBB AL, ib SBB eAX, iv SBB rb, rmb SBB rmb, ib SBB rmb, rb SBB rmv, ib

Exchange reg/mem byte with byte register Exchange byte register with reg/mem byte Exchange vword register with reg/mem vword Exchange eAX with vword register Exchange reg/mem vword with register vword Add with Carry immediate byte into AL Add with Carry immediate vword into eAX Add with Carry reg/mem byte into byte register Add with Carry immediate byte into reg/mem byte Add with Carry byte register into reg/mem byte Add with CF sign-extend immediate byte into reg/mem vword Add with Carry immediate vword into reg/mem vword Add with Carry vword register into reg/mem vword Add with Carry reg/mem vword into vword register Add immediate byte into AL Add immediate vword into eAX Add reg/mem byte into byte register Add immediate byte into reg/mem byte Add byte register into reg/mem byte Add immediate byte into reg/mem vword Add immediate vword into reg/mem vword Add vword register into reg/mem vword Add reg/mem vword into vword register Compare subtracting ib from AL, setting EFLAGS only Compare subtracting iv from eAX, setting EFLAGS only Compare subtracting rmb from rb, setting EFLAGS only Compare subtracting ib from rmb, setting EFLAGS only Compare subtracting rb from rmb, setting EFLAGS only Compare subtracting ib from rmv, setting EFLAGS only Compare subtracting iv from rmv, setting EFLAGS only Compare subtracting rv from rmv, setting EFLAGS only Compare subtracting rmv from rv, setting EFLAGS only Decrement reg/mem byte 1 (CF unaffected, LOCK prefix) Decrement reg/mem vword 1 (CF unaffected, LOCK prefix) Decrement vword register by 1 (CF unaffected, LOCK prefix) Unsigned Divide AX by reg/mem byte (AL = Quo, AH = Rem) Unsigned Divide eDX:eAX, rmv (eAX = Quo, eDX = Rem) Signed Divide AX by reg/mem byte (AL = Quo, AH = Rem) Signed Divide eDX:eAX by rmv (eAX = Quo, eDX = Rem) Signed Multiply (AX AL * reg/mem byte) Signed Multiply (eDX:eAX eAX * reg/mem vword) Signed Multiply sign-extend immediate byte into vword reg Signed Multiply immediate vword into vword register Signed Multiply reg/mem vword into vword register Signed Multiply (rv reg/mem vword * sign-extended ib) Signed Multiply (rv reg/mem vword * immediate vword) Increment reg/mem byte 1 (CF unaffected, LOCK prefix) Increment reg/mem vword 1 (CF unaffected, LOCK prefix) Increment vword register 1 (CF unaffected, LOCK prefix) Unsigned Multiply (AX AL * reg/mem byte) Unsigned Multiply (eDX:eAX eAX * reg/mem vword) Twos complement Negate reg/mem byte (LOCK prefix) Twos complement Negate reg/mem vword (LOCK prefix) Subtract with Borrow ib from/to AL (LOCK prefix) Subtract with Borrow iv from/to eAX (LOCK prefix) Subtract with Borrow rmb from/to rb (LOCK prefix) Subtract with Borrow ib from/to rmb (LOCK prefix) Subtract with Borrow rb from/to rmb (LOCK prefix) Subtract with Borrow ib from/to rmv (LOCK prefix)

none none none none none CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF PF, AF, ZF, SF, OF PF, AF, ZF, SF, OF PF, AF, ZF, SF, OF undefined undefined undefined undefined CF, OF CF, OF CF, OF CF, OF CF, OF CF, OF CF, OF PF, AF, ZF, SF, OF PF, AF, ZF, SF, OF PF, AF, ZF, SF, OF CF, OF CF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF

Binary Arithmetic Instructions:

1 1 3 1 1

81 /3 iv 19 /r 1B /r 2C ib 2D iv 2A /r 80 /5 ib 28 /r 83 /5 ib 81 /5 iv 29 /r 2B /r 37 D5 0A D4 0A 3F 27 2F 24 ib 25 iv 22 /r 80 /4 ib 20 /r 83 /4 ib 81 /4 iv 21 /r 23 /r F6 /2 F7 /2 0C ib 0D iv 0A /r 80 /1 ib 08 /r 83 /1 ib 81 /1 iv 09 /r 0B /r 34 ib 35 iv 32 /r 80 /6 ib 30 /r 83 /6 ib 81 /6 iv 31 /r 33 /r D0 /2 C0 /2 ib D2 /2 D1 /2 C1 /2 ib D3 /2 D0 /3 C0 /3 ib D2 /3

SBB rmv, iv SBB rmv, rv SBB rv, rmv SUB AL, ib SUB eAX, iv SUB rb, rmb SUB rmb, ib SUB rmb, rb SUB rmv, ib SUB rmv, iv SUB rmv, rv SUB rv, rmv AAA AAD AAM AAS DAA DAS AND AL, ib AND eAX, iv AND rb, rmb AND rmb, ib AND rmb, rb AND rmv, ib AND rmv, iv AND rmv, rv AND rv, rmv NOT rmb NOT rmv OR AL, ib OR eAX, iv OR rb, rmb OR rmb, ib OR rmb, rb OR rmv, ib OR rmv, iv OR rmv, rv OR rv, rmv XOR AL, ib XOR eAX, iv XOR rb, rmb XOR rmb, ib XOR rmb, rb XOR rmv, ib XOR rmv, iv XOR rmv, rv XOR rv, rmv RCL rmb, 1 RCL rmb, ib RCL rmb, CL RCL rmv, 1 RCL rmv, ib RCL rmv, CL RCR rmb, 1 RCR rmb, ib RCR rmb, CL

Subtract with Borrow iv from/to rmv (LOCK prefix) Subtract with Borrow rv from/to rmv (LOCK prefix) Subtract with Borrow rmv from/to rv (LOCK prefix) Subtract immediate byte from/to AL (LOCK prefix) Subtract immediate vword from/to eAX (LOCK prefix) Subtract reg/mem byte from/to rb (LOCK prefix) Subtract immediate byte from/to rmb (LOCK prefix) Subtract byte register from/to rmb (LOCK prefix) Subtract immediate byte from/to rmv (LOCK prefix) Subtract immediate vword from/to rmv (LOCK prefix) Subtract vword register from/to rmv (LOCK prefix) Subtract reg/mem vword from/to rv (LOCK prefix) ASCII Adjust sum of AL (carry into AH) after Addition ASCII Adjust AX before Divide (ALAH * 10 + AL; AH0) ASCII Adjust AX after Multiply (AH = Quo, AL = Rem) ASCII Adjust AL (borrows of AH, AH 0) after Subtraction Decimal Adjust AL after Addition Decimal Adjust AL after Subtraction Bitwise logical AND immediate byte into AL (LOCK prefix) Bitwise logical AND iv into eAX (LOCK prefix) Bitwise logical AND rmb into byte register (LOCK prefix) Bitwise logical AND ib into reg/mem byte (LOCK prefix) Bitwise logical AND byte register into rmb (LOCK prefix) Bitwise logical AND ib into reg/mem vword (LOCK prefix) Bitwise logical AND iv into reg/mem vword (LOCK prefix) Bitwise logical AND vword register into rmv (LOCK prefix) Bitwise logical AND rmv into vword register (LOCK prefix) Bitwise logical NOT on reg/mem byte (LOCK prefix) Bitwise logical NOT on reg/mem vword (LOCK prefix) Bitwise logical OR immediate byte into AL (LOCK prefix) Bitwise logical OR immediate vword into eAX (LOCK prefix) Bitwise logical OR reg/mem byte into rb (LOCK prefix) Bitwise logical OR ib into reg/mem byte (LOCK prefix) Bitwise logical OR rb into reg/mem byte (LOCK prefix) Bitwise logical OR ib into reg/mem vword (LOCK prefix) Bitwise logical OR iv into reg/mem vword (LOCK prefix) Bitwise logical OR rv into reg/mem vword (LOCK prefix) Bitwise logical OR reg/mem vword into rv (LOCK prefix) Bitwise logical XOR immediate byte into AL (LOCK prefix) Bitwise logical XOR iv into eAX (LOCK prefix) Bitwise logical XOR reg/mem byte into rb (LOCK prefix) Bitwise logical XOR ib into reg/mem byte (LOCK prefix) Bitwise logical XOR rb into reg/mem byte (LOCK prefix) Bitwise logical XOR ib into reg/mem vword (LOCK prefix) Bitwise logical XOR iv into reg/mem vword (LOCK prefix) Bitwise logical XOR rv into reg/mem vword (LOCK prefix) Bitwise logical XOR reg/mem vword into rv (LOCK prefix) Rotate 9 bits (CF, reg/mem byte) Left once Rotate 9 bits (CF, reg/mem byte) Left ib times Rotate 9 bits (CF, reg/mem byte) Left CL times Rotate 17/33 (word/dword) bits (CF, rmv) Left once Rotate 17/33 (word/dword) bits (CF, rmv) Left ib times Rotate 17/33 (word/dword) bits (CF, rmv) Left CL times Rotate 9 bits (CF, reg/mem byte) Right once Rotate 9 bits (CF, reg/mem byte) Right ib times Rotate 9 bits (CF, reg/mem byte) Right CL times

CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, AF PF, ZF, SF PF, ZF, SF CF, AF CF, PF, AF, ZF, SF CF, PF, AF, ZF, SF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF none none CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, OF CF, OF CF, OF CF, OF CF, OF CF, OF CF, OF CF, OF CF, OF

Decimal (base 10) Arithmetic Instructions:

Logic Instructions:

Shift and Rotate Instructions:

1 1 1

D1 /3 C1 /3 ib D3 /3 D0 /0 C0 /0 ib D2 /0 D1 /0 C1 /0 ib D3 /0 D0 /1 C0 /1 ib D2 /1 D1 /1 C1 /1 ib D3 /1 D0 /4 C0 /4 ib D2 /4 D1 /4 C1 /4 ib D3 /4 D0 /7 C0 /7 ib D2 /7 D1 /7 C1 /7 ib D3 /7 D0 /4 C0 /4 ib D2 /4 D1 /4 C1 /4 ib D3 /4 0F A4 /r ib 0F A5 /r D0 /5 C0 /5 ib D2 /5 D1 /5 C1 /5 ib D3 /5 0F AC /r ib 0F AD /r 0F BC /r 0F BD /r 0F BA /4 ib 0F A3 /r 0F BA /7 ib 0F BB /r 0F BA /6 ib 0F B3 /r 0F BA /5 ib 0F AB /r 0F 97 0F 93 0F 92 0F 96 0F 92 0F 94

RCR rmv, 1 RCR rmv, ib RCR rmv, CL ROL rmb, 1 ROL rmb, ib ROL rmb, CL ROL rmv, 1 ROL rmv, ib ROL rmv, CL ROR rmb, 1 ROR rmb, ib ROR rmb, CL ROR rmv, 1 ROR rmv, ib ROR rmv, CL SAL rmb, 1 SAL rmb, ib SAL rmb, CL SAL rmv, 1 SAL rmv, ib SAL rmv, CL SAR rmb, 1 SAR rmb, ib SAR rmb, CL SAR rmv, 1 SAR rmv, ib SAR rmv, CL SHL rmb, 1 SHL rmb, ib SHL rmb, CL SHL rmv, 1 SHL rmv, ib SHL rmv, CL SHLD rmv, rv, ib SHLD rmv, rv, CL SHR rmb, 1 SHR rmb, ib SHR rmb, CL SHR rmv, 1 SHR rmv, ib SHR rmv, CL SHRD rmv, rv, ib SHRD rmv, rv, CL BSF rv, rmv BSR rv, rmv BT rmv, ib BT rmv, rv BTC rmv, ib BTC rmv, rv BTR rmv, ib BTR rmv, rv BTS rmv, ib BTS rmv, rv SETA rmb SETAE rmb SETB rmb SETBE rmb SETC rmb SETE rmb

1 1 1 1 1 1 1

1 1 1 3 3 1 1 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

Rotate 17/33 (word/dword) bits (CF, rmv) Right once Rotate 17/33 (word/dword) bits (CF, rmv) Right ib times Rotate 17/33 (word/dword) bits (CF, rmv) Right CL times Rotate 8 bits reg/mem byte Left once Rotate 8 bits reg/mem byte Left ib times Rotate 8 bits reg/mem byte Left CL times Rotate 16/32 bits (word/dword) reg/mem vword Left once Rotate 16/32 bits (word/dword) reg/mem vword Left ib times Rotate 16/32 bits (word/dword) reg/mem vword Left CL times Rotate 8 bits reg/mem byte Right once Rotate 8 bits reg/mem byte Right ib times Rotate 8 bits reg/mem byte Right CL times Rotate 16/32 (word/dword) bits reg/mem vword Right once Rotate 16/32 (word/dword) bits reg/mem vword Right ib times Rotate 16/32 (word/dword) bits reg/mem vword Right CL times Multiply reg/mem byte by 2 once Multiply reg/mem byte by 2 ib times Multiply reg/mem byte by 2 CL times Multiply reg/mem vword by 2 once Multiply reg/mem vword by 2 ib times Multiply reg/mem vword by 2 CL times Signed divide reg/mem byte by 2 once (rounding to -) Signed divide reg/mem byte by 2 ib times (rounding to -) Signed divide reg/mem byte by 2 CL times (rounding to -) Signed divide reg/mem vword by 2 once (rounding to -) Signed divide reg/mem vword by 2 ib times (rounding to -) Signed divide reg/mem vword by 2 CL times (rounding to -) Multiply reg/mem byte by 2 once Multiply reg/mem byte by 2 ib times Multiply reg/mem byte by 2 CL times Multiply reg/mem vword by 2 once Multiply reg/mem vword by 2 ib times Multiply reg/mem vword by 2 CL times Shift rmv to Left ib places while shifting rv bits in from right Shift rmv to Left CL places while shifting rv bits in from right Unsigned divide reg/mem byte by 2 once Unsigned divide reg/mem byte by 2 ib times Unsigned divide reg/mem byte by 2 CL times Unsigned divide reg/mem vword by 2 once Unsigned divide reg/mem vword by 2 ib times Unsigned divide reg/mem vword by 2 CL times Shift rmv to Right ib places while shifting rv bits in from left Shift rmv to Right CL places while shifting rv bits in from left Set rv to lowest set Bit (1 bit) in rmv (if rmv = 0, rv undefined) Set rv to highest set Bit (1 bit) in rmv (if rmv = 0, rv undefined) Set CF to Bit in rmv at immediate byte Set CF to Bit in rmv at vword register Set CF to, then Complement Bit in rmv at ib (LOCK prefix) Set CF to, then Complement Bit in rmv at rv (LOCK prefix) Set CF to, then Reset (set to 0) Bit in rmv at ib (LOCK prefix) Set CF to, then Reset (set to 0) Bit in rmv at rv (LOCK prefix) Set CF to, then Set (set to 1) Bit in rmv at ib (LOCK prefix) Set CF to, then Set (set to 1) Bit in rmv at rv (LOCK prefix) Set byte if Above unsigned integer (CF = 0 & ZF = 0) Set byte if Above or Equal to unsigned integer (CF = 0) Set byte if Below unsigned integer (CF = 1) Set byte if Below or Equal to unS integer (CF = 1/ZF = 1) Set byte if Carry (CF = 1) Set byte if Equal (ZF = 1)

CF, OF CF, OF CF, OF CF, OF CF, OF CF, OF CF, OF CF, OF CF, OF CF, OF CF, OF CF, OF CF, OF CF, OF CF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF ZF ZF CF CF CF CF CF CF CF CF none none none none none none

Bit and Byte Instructions:

0F 9F 0F 9D 0F 9C 0F 9E 0F 96 0F 92 0F 93 0F 97 0F 93 0F 95 0F 9E 0F 9C 0F 9D 0F 9F 0F 91 0F 9B 0F 99 0F 95 0F 90 0F 9A 0F 9A 0F 9B 0F 98 0F 94 A8 ib A9 iv F6 /0 ib 84 /r F7 /0 iv 85 /r 62 /r 9A cp E8 cv FF /3 FF /2 C8 iw 00 C8 iw 01 C8 iw ib CC CD ib CE CF CF 77 cb 0F 87 cv 73 cb 0F 83 cv 72 cb 0F 82 cv 76 cb 0F 86 cv 72 cb 0F 82 cv E3 cb 74 cb 0F 84 cv E3 cb 7F cb 0F 8F cv 7D cb

SETG rmb SETGE rmb SETL rmb SETLE rmb SETNA rmb SETNAE rmb SETNB rmb SETNBE rmb SETNC rmb SETNE rmb SETNG rmb SETNGE rmb SETNL rmb SETNLE rmb SETNO rmb SETNP rmb SETNS rmb SETNZ rmb SETO rmb SETP rmb SETPE rmb SETPO rmb SETS rmb SETZ rmb TEST AL, ib TEST eAX, iv TEST rmb, ib TEST rmb, rb TEST rmv, iv TEST rmv, rv BOUND rv, mv&v CALL cp CALL cv CALL mp CALL rmv ENTER iw, 0 ENTER iw, 1 ENTER iw, ib INT 3 INT ib INTO IRET IRETD JA cb JA cv JAE cb JAE cv JB cb JB cv JBE cb JBE cv JC cb JC cv JCXZ cb JE cb JE cv JECXZ cb JG cb JG cv JGE cb

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

Set byte if Greater than signed integer (ZF = 0 & SF = OF) Set byte if Greater or Equal to signed integer (SF = OF) Set byte if Less than signed integer (SF <> OF) Set byte if Less or Equal to signed integer (ZF = 1/SF <> OF) Set byte if Not Above unsigned integer (CF = 1/ZF = 1) Set byte if Not Above or Equal to unsigned integer (CF = 1) Set byte if Not Below unsigned integer (CF = 0) Set byte if Not Below or Equal to unS int. (CF = 0 & ZF = 0) Set byte if Not Carry (CF = 0) Set byte if Not Equal (ZF = 0) Set byte if Not Greater than signed integer (ZF = 1/SF <> OF) Set byte if Not Greater or Equal to signed integer (SF <> OF) Set byte if Not Less than signed integer (SF = OF) Set byte if Not Less or Equal to S integer (ZF = 0 & SF = OF) Set byte if Not Overflow (OF = 0) Set byte if Not Parity (lowest byte 1 bits not even #, PF = 0) Set byte if Not Signed (positive integer, SF = 0) Set byte if Not Zero (ZF = 0) Set byte if Overflow (OF = 1) Set byte if Parity (lowest byte 1 bits not even #, PF = 1) Set byte if Parity Even (lowest byte 1 bits not even #, PF = 1) Set byte if Parity Odd (lowest byte 1 bits not even #, PF = 0) Set byte if Signed (negative integer, SF = 1) Set byte if Zero (ZF = 1) Bitwise logical AND ib with AL, set EFLAGS (CF, OF 0) Bitwise logical AND iv with eAX, set EFLAGS (CF, OF 0) Bitwise logical AND ib with rmb, set EFLAGS (CF, OF 0) Bitwise logical AND rb with rmb, set EFLAGS (CF, OF 0) Bitwise logical AND iv with rmv, set EFLAGS (CF, OF 0) Bitwise logical AND rv with rmv, set EFLAGS (CF, OF 0) Check if rv is within Bounds of mv&v (if not, exception #BR) Push CS & EIP; Call far, absolute, 4-/6-byte address cp Push EIP; Call near offset cv (relative to next instruction) Push CS & EIP; Call far, absolute indirect, 4-/6-B address mp Push CS & EIP; Call far, absolute indirect, address rmv Make procedural stack frame, iw bytes local storage, 0 levels Make procedural stack frame, iw bytes local storage, 1 level Make procedural stack frame, iw bytes local storage, ib levels Interrupt 3trap to debugger (push EFLAGS, CS, EIP; far call) Interrupt vector number ib (push EFLAGS, CS, EIP; far call) Interrupt 4if OF is 1 (push EFLAGS, CS, & EIP; far call) Interrupt Return (pops EIP, CS, EFLAGS; may SS, data sregs) Interrupt Return (pops EIP, CS, EFLAGS; may SS, data sregs) Jump short if Above unsigned integer (CF = 0 & ZF = 0) Jump near if Above unsigned integer (CF = 0 & ZF = 0) Jump short if Above or Equal to unsigned integer (CF = 0) Jump near if Above or Equal to unsigned integer (CF = 0) Jump short if Below unsigned integer (CF = 1) Jump near if Below unsigned integer (CF = 1) Jump short if Below or Equal to unS integer (CF = 1/ZF = 1) Jump near if Below or Equal to unS integer (CF = 1/ZF = 1) Jump short if Carry (CF = 1) Jump near if Carry (CF = 1) Jump short if CX register is Zero Jump short if Equal (ZF = 1) Jump near if Equal (ZF = 1) Jump short if ECX register is Zero Jump short if Greater than signed integer (ZF = 0 & SF = OF) Jump near if Greater than signed integer (ZF = 0 & SF = OF) Jump short if Greater than or Equal to signed integer (SF = OF)

none none none none none none none none none none none none none none none none none none none none none none none none CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF CF, PF, ZF, SF, OF none all or none all or none all or none all or none none none none TF, IF, NT, RF, VM, AC TF, IF, NT, RF, VM, AC TF, IF, NT, RF, VM, AC all all none none none none none none none none none none none none none none none none none

Control Transfer Instructions:

2

1 1 1

3 3 3 3 3 3 3 3 3

0F 8D cv 7C cb 0F 8C cv 7E cb 0F 8E cv EB cb EA cp E9 cv FF /4 FF /5 76 cb 0F 86 cv 72 cb 0F 82 cv 73 cb 0F 83 cv 77 cb 0F 87 cv 73 cb 0F 83 cv 75 cb 0F 85 cv 7E cb 0F 8E cv 7C cb 0F 8C cv 7D cb 0F 8D cv 7F cb 0F 8F cv 71 cb 0F 81 cv 7B cb 0F 8B cv 79 cb 0F 89 cv 75 cb 0F 85 cv 70 cb 0F 80 cv 7A cb 0F 8A cv 7A cb 0F 8A cv 7B cb 0F 8B cv 78 cb 0F 88 cv 74 cb 0F 84 cv C9 E2 cb E1 cb E0 cb E0 cb E1 cb C3 CB C2 iw CA iw CB

JGE cv JL cb JL cv JLE cb JLE cv JMP cb JMP cp JMP cv JMP rmv JMP mp JNA cb JNA cv JNAE cb JNAE cv JNB cb JNB cv JNBE cb JNBE cv JNC cb JNC cv JNE cb JNE cv JNG cb JNG cv JNGE cb JNGE cv JNL cb JNL cv JNLE cb JNLE cv JNO cb JNO cv JNP cb JNP cv JNS cb JNS cv JNZ cb JNZ cv JO cb JO cv JP cb JP cv JPE cb JPE cv JPO cb JPO cv JS cb JS cv JZ cb JZ cv LEAVE LOOP cb LOOPE cb LOOPNE cb LOOPNZ cb LOOPZ cb RET RET RET iw RET iw RETF

3 3 3

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1

Jump near if Greater than or Equal to signed integer (SF = OF) Jump short if Less than signed integer (SF <> OF) Jump near if Less than signed integer (SF <> OF) Jump short if Less or Equal to S integer (ZF = 1/SF <> OF) Jump near if Less or Equal to S integer (ZF = 1/SF <> OF) Jump short signed byte (relative to next instruction) Jump far, absolute, 4-/6-byte address cp Jump near, offset cv (relative to next instruction) Jump near, absolute indirect, address reg/mem vword Jump far, absolute indirect, 4-/6-byte address mp Jump short if Not Above unsigned integer (CF = 1 & ZF = 1) Jump near if Not Above unsigned integer (CF = 1 & ZF = 1) Jump short if Not Above or Equal to unsigned integer (CF = 1) Jump near if Not Above or Equal to unsigned integer (CF = 1) Jump short if Not Below unsigned integer (CF = 0) Jump near if Not Below unsigned integer (CF = 0) Jump short if Not Below or Equal to unS (CF = 0 or ZF = 0) Jump near if Not Below or Equal to unS (CF = 0 or ZF = 0) Jump short if Not Carry (CF = 0) Jump near if Not Carry (CF = 0) Jump short if Not Equal (ZF = 0) Jump near if Not Equal (ZF = 0) Jump short if Not Greater than unsigned (ZF = 1 or SF <> OF) Jump near if Not Greater than unsigned (ZF = 1 or SF <> OF) Jump short if Not Greater or Equal to unsigned (SF <> OF) Jump near if Not Greater or Equal to unsigned (SF <> OF) Jump short if Not Less than unsigned integer (SF = OF) Jump near if Not Less than unsigned integer (SF = OF) Jump short if Not Less or Equal to unS (ZF = 0 & SF = OF) Jump near if Not Less or Equal to unS (ZF = 0 & SF = OF) Jump short if Not Overflow (OF = 0) Jump near if Not Overflow (OF = 0) Jump short if Not Parity (lowest byte 1 bits not even #, PF = 0) Jump near if Not Parity (lowest byte 1 bits not even #, PF = 0) Jump short if Not Signed (positive integer, SF = 0) Jump short if Not Signed (positive integer, SF = 0) Jump short if Not Zero (ZF = 0) Jump near if Not Zero (ZF = 0) Jump short if Overflow (OF = 1) Jump near if Overflow (OF = 1) Jump short if Parity (lowest byte 1 bits are even #, PF = 1) Jump near if Parity (lowest byte 1 bits are even #, PF = 1) Jump short if Parity Even (lowest byte 1 bits are even #, PF = 1) Jump near if Parity Even (lowest byte 1 bits are even #, PF = 1) Jump short if Parity Odd (lowest byte 1 bits not even #, PF = 0) Jump near if Parity Odd (lowest byte 1 bits not even #, PF = 0) Jump short if Signed (negative integer, SF = 1) Jump near if Signed (negative integer, SF = 1) Jump short if Zero (ZF = 1) Jump near if Zero (ZF = 1) Set SP to BP, then pop BP (releases stack frame of ENTER) DEC eCX; jump short if eCX 0 DEC eCX; jump short if eCX 0 & equal (ZF = 1) DEC eCX; jump short if eCX 0 & (ZF = 0) DEC eCX; jump short if eCX 0 & not 0 (ZF = 0) DEC eCX; jump short if eCX 0 & zero (ZF = 1) Near Return to calling procedure (return address on TOS) Far Return to calling procedure (return address on TOS) Near Return to calling procedure (TOS); pop iw B from stack Far Return to calling procedure (TOS); pop iw B from stack Return Far to calling procedure (return address on TOS)

none none none none none all or none all or none all or none all or none all or none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none

CA iw C3 C2 iw A6 A7 A6 A7 A7 6C 6D 6C 6D 6D AC AD AC AD AD A4 A5 A4 A5 A5 6E 6F 6E 6F 6F AE AF AE AF AF AA AB AA AB AB F8 FC FA F5 9F 9D 9D 9C 9C 9E F9 FD FB C5 /r C4 /r 0F B4 /r 0F B5 /r 0F B2 /r

RETF iw RETN RETN iw CMPS mb, mb CMPS mv, mv CMPSB CMPSD CMPSW INS rmb, DX INS rmv, DX INSB INSD INSW LODS mb LODS mv LODSB LODSD LODSW MOVS mb, mb MOVS mv, mv MOVSB MOVSD MOVSW OUTS DX, rmb OUTS DX, rmv OUTSB OUTSD OUTSW SCAS mb SCAS mv SCASB SCASD SCASW STOS mb STOS mv STOSB STOSD STOSW CLC CLD CLI CMC LAHF POPF POPFD PUSHF PUSHFD SAHF STC STD STI LDS rv, mp LES rv, mp LFS rv, mp LGS rv, mp LSS rv, mp

Return Far to calling procedure (TOS); pop iw B from stack Return Near to calling procedure (return address on TOS) Return Near to calling procedure (TOS); pop iw B from stack Compare bytes DS:[eSI] to ES:[eDI]; advance eSI & eDI Compare vwords DS:[eSI] to ES:[eDI]; advance eSI & eDI Compare Bytes DS:[eSI] to ES:[eDI]; advance eSI & eDI Compare Dwords DS:[eSI] to ES:[eDI]; advance eSI & eDI Compare Words DS:[eSI] to ES:[eDI]; advance eSI & eDI Input byte from port DX (0-65,535) to ES:[eDI]; advance eDI Input vword of port DX (0-65,535) to ES:[eDI]; advance eDI Input Byte from port DX (0-65,535) to ES:[eDI]; advance eDI Input Dword of port DX (0-65,535) to ES:[eDI]; advance eDI Input Word of port DX (0-65,535) to ES:[eDI]; advance eDI Load byte DS:[eSI] into AL; advance eSI Load vword DS:[eSI] into eAX; advance eSI Load Byte DS:[eSI] into AL; advance eSI Load Dword DS:[eSI] into EAX; advance eSI Load Word DS:[eSI] into AX; advance eSI Move byte DS:[eSI] to ES:[eDI]; advance eSI & eDI Move vword DS:[eSI] to ES:[eDI]; advance eSI & eDI Move Byte DS:[eSI] to ES:[eDI]; advance eSI & eDI Move Dword DS:[eSI] to ES:[eDI]; advance eSI & eDI Move Word DS:[eSI] to ES:[eDI]; advance eSI & eDI Output byte DS:[eSI] to port in DX (0-65,535); advance eSI Output vword DS:[eSI] to port in DX (0-65,535); advance eSI Output Byte DS:[eSI] to port in DX (0-65,535); advance eSI Output Dword DS:[eSI] to port in DX (0-65,535); advance eSI Output Word DS:[eSI] to port in DX (0-65,535); advance eSI Compare byte AL to ES:[eDI]; advance eDI; set EFLAGS Compare vword eAX to ES:[eDI]; advance eDI; set EFLAGS Compare Byte AL to ES:[eDI]; advance eDI; set EFLAGS Compare Dword EAX to ES:[eDI]; advance eDI; set EFLAGS Compare Word AX to ES:[eDI]; advance eDI, set EFLAGS Store byte AL to ES:[eDI]; advance eDI Store vword eAX to ES:[eDI]; advance eDI Store Byte AL to ES:[eDI]; advance eDI Store Dword EAX to ES:[eDI]; advance eDI Store Word AX to ES:[eDI]; advance eDI Clear Carry flag (CF 0) Clear Direction flag (DF 0) so eSI and eDI auto-increment Clear Interrupt enable flag (IF 0) (interrupts disabled) Complement Carry flag (CF) (set CF to opposite value) Load: AH EFLAGS (SF, ZF, 0, AF, 0, PF, 1, CF) Pop TOS into lower 16 bits of EFLAGS; increment eSP by 2 Pop TOS into EFLAGS; increment eSP by 2 Decrement eSP by 2; Push lower 16 bits of EFLAGS to TOS Decrement eSP by 4; Push EFLAGS to TOS Store: SF, ZF, xx, AF, xx, PF, xx, & CF of AH EFLAGS Set Carry flag (CF 1) Set Direction flag (DF 1) so SI and DI auto-decrement Set Interrupt enable flag (IF 1) (interrupts enabled) Load far 32-/48-bit pointer from reg/mem to DS & vword reg Load far 32-/48-bit pointer from reg/mem to ES & vword reg Load far 32-/48-bit pointer from reg/mem to FS & vword reg Load far 32-/48-bit pointer from reg/mem to GS & vword reg Load far 32-/48-bit pointer from reg/mem to SS & vword reg

none none none CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF none none none none none none none none none none none none none none none none none none none none CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF CF, PF, AF, ZF, SF, OF none none none none none CF DF IF CF none all but reserve & VM bits all but reserve & VM bits none none CF, PF, AF, ZF, SF CF DF IF none none none none none

String Instructions (may use REPx prefix for block operations):

3 1 1 1 3 1

3 1 1 1 3 1

Flag Control Instructions:

3 3

Segment Register Instructions:

3 3 3

Miscellaneous Instructions:
0F A2 8D /r 90 0F 0B D7 D7 0F 6E /r 0F 7E /r 0F 6F /r 0F 7F /r 0F 6B /r 0F 63 /r 0F 67 /r 0F 68 /r 0F 6A /r 0F 69 /r 0F 60 /r 0F 62 /r 0F 61 /r 0F FC /r 0F FE /r 0F EC /r 0F ED /r 0F DC /r 0F DD /r 0F FD /r 0F F5 /r 0F E5 /r 0F D5 /r 0F F8 /r 0F FA /r 0F E8 /r 0F E9 /r 0F D8 /r 0F D9 /r 0F F9 /r 0F 74 /r 0F 76 /r 0F 75 /r 0F 64 /r 0F 66 /r 0F 65 /r 0F DB /r 0F DF /r 0F EB /r 0F EF /r CPUID LEA rv, m NOP UD2 XLAT mb XLATB MOVD mm, rmd MOVD rmd, mm MOVQ mm, mm/mq MOVQ mm/mq, mm PACKSSDW m1, m2/mq PACKSSWB x1, x2/mdq PACKUSWB mm, mm/mq PUNPCKHBW mm, mm/mq PUNPCKHDQ mm, mm/mq PUNPCKHWD mm, mm/mq PUNPCKLBW mm, mm/md PUNPCKLDQ mm, mm/md PUNPCKLWD mm, mm/md PADDB mm, mm/mq PADDD mm, mm/mq PADDSB mm, mm/mq PADDSW mm, mm/mq PADDUSB mm, mm/mq PADDUSW mm, mm/mq PADDW mm, mm/mq PMADDWD mm, mm/mq PMULHW m1, m2/mq PMULLW m1, m2/mq PSUBB mm, mm/mq PSUBD mm, mm/mq PSUBSB mm, mm/mq PSUBSW mm, mm/mq PSUBUSB mm, mm/mq PSUBUSW mm, mm/mq PSUBW mm, mm/mq PCMPEQB mm, mm/mq PCMPEQD mm, mm/mq PCMPEQW mm, mm/mq PCMPGTB mm, mm/mq PCMPGTD mm, mm/mq PCMPGTW mm, mm/mq PAND mm, mm/mq PANDN mm, mm/mq POR mm, mm/mq PXOR mm, mm/mq 5 EAX value CPU Id & features to EAX, EBX, ECX, & EDX Calculate & Load Effective Address for m into vword register No Operation (takes up space in execution, only affects EIP) Raise invalid opcode exception (#UD) Set AL to memory byte DS:[eBX + unsigned AL] Set AL to memory byte DS:[eBX + unsigned AL] Move reg/mem Dword to mm; zero-extend (mm[63-32] 0) Move low Dword of mm to reg/mem dword Move Qword from mm/mq to mm; if mq, mm[127-64] 0 Move Qword from mm to mm/mq Pack m1, 2 Dwords m2/mq to 4 Words m1 (Signed Saturation) Pack 8 Words x1, x2/mdq to 16 Bytes x1 (Signed Saturation) Pack 4 Words mm, mm/m64 to 8 unsigned B mm (unS sat.) Unpack, interleave High Bytes mm, mm/mq into Words mm Unpack, interleave High Dwords mm, mm/mq into Qwords mm Unpack, interleave High Words mm, mm/mq into Dwords mm Unpack, interleave Low Bytes mm, mm/md into Words mm Unpack, interleave Low Dwords mm, mm/md into Qwords mm Unpack, interleave Low Words mm, mm/md into Dwords mm Packed Add Bytes mm/mq into mm; wrap-around overflow Packed Add Dwords mm/mq into mm; wrap-around overflow Packed Add Bytes mm/mq into mm; wrap-around O (S sat.) Packed Add Words mm/mq into mm; wrap-around O (S sat.) Packed Add Bytes mm/mq into mm; wrap-around O (UnS sat.) Packed Add Words mm/mq into mm; wrap-around O (UnS sat.) Packed Add Words mm/mq into mm; wrap-around overflow Packed Multiply Words mm, mm/mq; Add adjacents into mm Packed Multiply S Words m1, m2/mq; High 16 bits into m1 Packed Multiply S Words m1, m2/mq; Low 16 bits into m1 Packed Subtract B mm/mq from/to mm, wrap-around overflow Packed Subtract Dwords mm/mq from/to mm, wrap-around O Packed Subtract Bytes mm/mq from/to mm (S saturate) Packed Subtract Words mm/mq from/to mm (S saturate) Packed Subtract Bytes mm/mq from/to mm (UnS saturate) Packed Subtract Words mm/mq from/to mm (UnS saturate) Packed Subtract Words mm/mq from/to mm, wrap-around O Packed Compare Bytes mm/mq to mm; 1s mm if =, else 0s Packed Compare Dwords mm/mq to mm; 1s mm if =, else 0s Packed Compare Words mm/mq to mm; 1s mm if =, else 0s Packed Compare S B mm/mq to mm; 1s mm if >, else 0s Packed Compare S Dwords mm/mq to mm; 1s mm if >, else 0s Packed Compare S Words mm/mq to mm; 1s mm if >, else 0s Packed bitwise AND mm/mq into mm Packed bitwise AND NOT mm/mq into mm Packed bitwise OR mm/mq into mm Packed bitwise XOR mm/mq into mm none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none

MMX Data Transfer (Integer) Instructions:

M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M M

MMX Conversion (Integer) Instructions:

MMX Packed Arithmetic (Integer) Instructions:

MMX Comparison (Integer) Instructions:

MMX Logic (Integer) Instructions:

MMX Shift and Rotate (Integer) Instructions:

0F 72 /6 ib 0F F2 /r 0F 73 /6 ib 0F F3 /r 0F 71 /6 ib 0F F1 /r 0F 72 /4 ib 0F E2 /r 0F 71 /4 ib 0F E1 /r 0F 72 /2 ib 0F D2 /r 0F 73 /2 ib 0F D3 /r 0F 71 /2 ib 0F D1 /r 0F 77 0F 28 /r 0F 29 /r 0F 12 /r 0F 17 /r 0F 16 /r 0F 16 /r 0F 13 /r 0F 12 /r 0F 50 /r F3 0F 10 /r F3 0F 11 /r 0F 10 /r 0F 11 /r 0F 58 /r F3 0F 58 /r 0F 5E /r F3 0F 5E /r 0F 5F /r F3 0F 5F /r 0F 5D /r F3 0F 5D /r 0F 59 /r F3 0F 59 /r 0F 53 /r F3 0F 53 /r 0F 52 /r F3 0F 52 /r 0F 51 /r F3 0F 51 /r 0F 5C /r F3 0F 5C /r 0F C2 /r 00 PSLLD mm, ib PSLLD mm, mm/mq PSLLQ mm, ib PSLLQ mm, mm/mq PSLLW mm, ib PSLLW mm, mm/mq PSRAD mm, ib PSRAD mm, mm/mq PSRAW mm, ib PSRAW mm, mm/mq PSRLD mm, ib PSRLD mm, mm/mq PSRLQ mm, ib PSRLQ mm, mm/mq PSRLW mm, ib PSRLW mm, mm/mq EMMS MOVAPS x1, x2/mdq MOVAPS x2/mdq, x1 MOVHLPS x1, x2 MOVHPS mq, xm MOVHPS xm, mq MOVLHPS x1, x2 MOVLPS mq, xm MOVLPS xm, mq MOVMSKPS rd, xm MOVSS x1, x2/md MOVSS x2/md, x1 MOVUPS x1, x2/mdq MOVUPS x2/mdq, x1 ADDPS x1, x2/mdq ADDSS x1, x2/md DIVPS x1, x2/mdq DIVSS x1, x2/md MAXPS x1, x2/mdq MAXSS x1, x2/md MINPS x1, x2/mdq MINSS x1, x2/md MULPS x1, x2/mdq MULSS x1, x2/md RCPPS x1, x2/mdq RCPSS x1, x2/md RSQRTPS x1, x2/mdq RSQRTSS x1, x2/md SQRTPS x1, x2/mdq SQRTSS x1, x2/md SUBPS x1, x2/mdq SUBSS x1, x2/md M M M M M M M M M M M M M M M M Packed Shift Dwords mm Left by ib, shifting 0s in right Packed Shift Dwords mm Left by mm/mq, shifting 0s in right Packed Shift Qword mm Left by ib, shifting 0s in right Packed Shift Qword mm Left by mm/mq, shifting 0s in right Packed Shift Words mm Left by ib, shifting 0s in right Packed Shift Words mm Left by mm/mq, shifting 0s in right Packed Shift Dwords mm Right by ib, shifting in sign bits Packed Shift Dwords mm Right by mm/mq, shifting in sign bits Packed Shift Words mm Right by ib, shifting in sign bits Packed Shift Words mm Right by mm/mq, shifting in sign bits Packed Shift Dwords mm Right by ib, shifting 0s in left Packed Shift Dwords mm Right by mm/mq, shifting 0s in left Packed Shift Qword mm Right by ib, shifting 0s in left Packed Shift Qword mm Right by mm/mq, shifting 0s in left Packed Shift Words mm Right by ib, shifting 0s in left Packed Shift Words mm Right by mm/mq, shifting 0s in left none none none none none none none none none none none none none none none none none none none none none none none none none none none none none none #I, #D, #O, #U, #P #I, #D, #O, #U, #P #I, #D, #Z, #O, #U, #P #I, #Z, #D, #O, #U, #P #I (with QNaN source), #D #I (with QNaN source), #D #I (with QNaN source), #D #I (with QNaN source), #D #I, #D, #O, #U, #P #I, #D, #O, #U, #P none none none none #I, #D, #P #I, #D, #P #I, #D, #O, #U, #P #I, #D, #O, #U, #P #I (if SNaN), #D

MMX State Management Instruction:

M Set x87 FPU tag word to Empty (clear the MMX State) P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 Move 4 P SP FPs from x2/mdq to x1 (16-B Aligned or #GP) Move 4 P SP FPs from x1 to x2/mdq (16-B Aligned or #GP) Move 2 P SP FPs from High qword of x2 to Low qword of x1 Move 2 P SP FP from High qword of xm to mqword Move 2 P SP FP from mqword to High qword of xm Move 2 P SP FPs from Low qword of x2 to High qword of x1 Move 2 P SP FPs from Low qword of xm to mqword Move 2 P SP FPs from mqword to Low qword of xm Extract 4-bit sign Mask from xm and store in dword register Move Scalar SP FP dword x2/md to x1; if md, x1[127-32] 0 Move Scalar SP FP dword value from x1 register to x2/md Move 4 P SP FPs from x2/mdq to x1 (may be Unaligned) Move 4 P SP FPs from x1 to x2/mdq (may be Unaligned) Add 4 Packed SP FPs from x2/mdq into x1 Add low SP FPs from x2/md into x1; x1[127-32] not changed Divide 2 P SP FPs in x2/mdq into x1 (x1 = quotient) Divide low SP FP in x2/md into x1 (x1 = quotient) Return Maximum SP FPs between x2/mdq and/to x1 Return Maximum Scalar SP FP between x2/md and/to x1 Return Minimum SP FPs between x2/mdq and/to x1 Return Minimum Scalar SP FP between x2/md and/to x1 Multiply Packed SP FPs in x2/mdq into x1 Multiply low SP FP in x2/md into x1 Set 4 approximate Reciprocals of P SP FPs x2/mdq to x1 Set approximate Reciprocal low Scalar SP FP x2/md to x1 Set 4 approx. Reciprocal Square Roots P SP FP x2/mdq to x1 Set approx. Reciprocal Square Root low SP FP x2/md to x1 Set 4 Square Roots of P SP FPs x2/mdq to x1 Set Square Root of low SP FP x2/md to x1 Subtract 4 P SP FPs in x2/mdq from/to x1 Subtract low SP FP in x2/md from/to x1

SSE Data Transfer (SP Floating-Point) Instructions:

SSE Packed Arithmetic (SP Floating-Point) Instructions:

SSE Comparison (SP Floating-Point) Instructions:

CMPEQPS x1, x2/mdq P3 Compare 2 P SP FPs x2/mdq, x1; dwords 1s x1 if =, else 0s

F3 0F C2 /r 00 CMPEQSS x1, x2/md

P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 F3 0F C2 /r 03 CMPUNORDSS x1, x2/md P3 0F 2F /r COMISS x1, x2/md P3 0F 2E /r UCOMISS x1, x2/md P3 0F C2 /r 02 CMPLEPS x1, x2/mdq F3 0F C2 /r 02 CMPLESS x1, x2/md 0F C2 /r 01 CMPLTPS x1, x2/mdq F3 0F C2 /r 01 CMPLTSS x1, x2/md 0F C2 /r 04 CMPNEQPS x1, x2/mdq F3 0F C2 /r 04 CMPNEQSS x1, x2/md 0F C2 /r 06 CMPNLEPS x1, x2/mdq F3 0F C2 /r 06 CMPNLESS x1, x2/md 0F C2 /r 05 CMPNLTPS x1, x2/mdq F3 0F C2 /r 05 CMPNLTSS x1, x2/md 0F C2 /r 07 CMPORDPS x1, x2/mdq F3 0F C2 /r 07 CMPORDSS x1, x2/md 0F C2 /r 03 CMPUNORDPS x1, x2/mdq 0F 55 /r 0F 54 /r 0F 56 /r 0F 57 /r 0F C6 /r ib 0F 15 /r 0F 14 /r ANDNPS x1, x2/mdq ANDPS x1, x2/mdq ORPS x1, x2/mdq XORPS x1, x2/mdq P3 P3 P3 P3

Compare low SP FP x2/md, x1; dword 1s x1 if =, else 0s Compare 2 P SP FPs x2/mdq, x1; dwords 1s x1 if , else 0s Compare low SP FP x2/md, x1; dword 1s x1 if , else 0s Compare 2 P SP FPs x2/mdq, x1; dwords 1s x1 if <, else 0s Compare low SP FP x2/md, x1; dword 1s x1 if <, else 0s Compare 2 P SP FPs x2/mdq, x1; dwords 1s x1 if , else 0s Compare low SP FP x2/md, x1; dword 1s x1 if , else 0s Compare 2 P SP FPs x2/mdq, x1; dwords 1s x1 if not , else 0s Compare low SP FP x2/md, x1; dword 1s x1 if not , else 0s Compare 2 P SP FP x2/mdq, x1; dwords 1s x1 if not <, else 0s Compare low SP FP x2/md, x1; dword 1s x1 if not <, else 0s Compare 2 P SP FP x2/mdq, x1; dwords 1s x1 Ordered, else 0s Compare low SP FP x2/md, x1; dword 1s x1 if Ordered, else 0s Compare 2 P SP FP x2/mdq, x1; dwords 1s x1 Unorder, else 0s Compare low SP FP x2/md, x1; dword 1s x1 Unordered, else 0s Ordered Compare low SP FP x2/md & x1; set EFLAGS Unordered Compare low SP FP x2/md & x1; set EFLAGS Bitwise logical AND NOT 4 P SP FPs in x2/mdq into x1 Bitwise logical AND 4 P SP FPs in x2/mdq into x1 Bitwise logical OR 4 P SP FPs in x2/mdq into x1 Bitwise logical XOR 4 P SP FPs x2/mdq into x1

#I (if SNaN/QNaN), #D #I (if SNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN), #D none none none none

SSE Logical (SP Floating-Point) Instructions:

SSE Shuffle and Unpack (SP Floating-Point) Instructions:

SHUFPS x1, x2/mdq, ib P3 Shuffle P SP FP x2/mdq to low or high of x1, selected by ib none UNPCKHPS x1, x2/mdq P3 Unpack & interleave SP FPs of High qwords x2/mdq and/to x1 none UNPCKLPS x1, x2/mdq P3 Unpack & interleave SP FPs of Low qwords x2/mdq and/to x1 none P3 P3 P3 P3 P3 P3 Convert 2 P signed dwords from mm/mq to 2 P SP FPs in xm Convert 2 P SP FPs from xm/mq to 2 P signed dwords in mm Convert signed dword from rmw to SP FP in xm Convert SP FP xm/md to rounded signed dword in rd Convert 2 P SP FPs xm/mq to 2 P S Truncated dwords in mm Convert SP FP from xm/md to S Truncated dword in rd #P #I, #P #P #I, #P #I, #P #I, #P none none none none none none none none none none none none none none none none none none none

SSE Conversion (SP Floating-Point) Instructions:

0F 2A /r CVTPI2PS xm, mm/mq 0F 2D /r CVTPS2PI mm, xm/mq F3 0F 2A /r CVTSI2SS xm, rmd F3 0F 2D /r CVTSS2SI rd, xm/md 0F 2C /r CVTTPS2PI mm, xm/mq F3 0F 2C /r CVTTSS2SI rd, xm/md 0F AE /2 0F AE /3 0F E0 /r 0F E3 /r 0F C5 /r ib 0F C4 /r ib 0F EE /r 0F DE /r 0F EA /r 0F DA /r 0F D7 /r 0F E4 /r 0F F6 /r 0F 70 /r ib 0F F7 /r 0F 2B /r 0F E7 /r 0F 18 /1 0F 18 /2 LDMXCSR md STMXCSR md

MXCSR (SSE(2) SIMD FP Control/Status Register) State Management Instructions:

P3 Load md into SIMD Control/Status Register (MXCSR) P3 Store SIMD Control/Status Register (MXCSR) to md Packed Average unS B m2/mq and/to m1 with rounding Packed Average unS Words m2/mq and/to m1 with rounding Packed Extract Word number ib from mm and move to rd Packed Insert low Word of rd/mw into word number ib of mm Return Packed Maximum of Signed Words in m2/mq and/to m1 Return Packed Maximum of Unsigned B in m2/mq and/to m1 Return Packed Minimum of Signed Words in m2/mq and/to m1 Return Packed Minimum Unsigned B in m2/mq and/to m1 Set dword register to most significant bits of bytes in mm Packed unS Multiply words m2/mq, m1;High 16-bit resultm1 Word sum of P unS B absolute differences of x2/mq and/to m1 Packed Shuffle Words m2/mq to m1, using 2-bit encoding ib Non-temporal Move m2 Masked B of m1 to [eDI]; MMX state Non-temporal SP FP Move from xm to 16-B aligned mdqword Non-temporal Qword Move from mx to 16-B aligned mqword Prefetch memory mb into all cache levels Prefetch memory mb into all cache levels, except level 0

SSE 64-Bit SIMD Integer Instructions:

PAVGB m1, m2/mq P3 PAVGW m1, m2/mq P3 PEXTRW rd, mm, ib P3 PINSRW mm, rd/mw, ib P3 PMAXSW m1, m2/mq P3 PMAXUB m1, m2/mq P3 PMINSW m1, m2/mq P3 PMINUB m1, m2/mq P3 PMOVMSKB rd, mm P3 PMULHUW m1, m2/mq P3 PSADBW m1, m2/mq P3 PSHUFW m1, m2/mq, ib P3 MASKMOVQ m1, m2 MOVNTPS mdq, xm MOVNTQ mq, mx PREFETCH0 mb PREFETCH1 mb P3 P3 P3 P3 P3

SSE Cacheability Control, Prefetch, and Instruction Ordering Instructions:

0F 18 /3 0F 18 /0 0F AE FF

PREFETCH2 mb PREFETCHNTA mb SFENCE

P3 Prefetch memory mb into all cache levels, except levels 0 & 1 P3 Non-temporal prefetch memory mb into all cache levels P3 Serializes so that previous stores are visible before next stores

none none none

SSE2 Data Movement (DP Floating-Point) Instructions:

66 0F 28 /r 66 0F 29 /r 66 0F 17 /r 66 0F 16 /r 66 0F 13 /r 66 0F 12 /r 66 0F 50 /r F2 0F 10 /r F2 0F 11 /r 66 0F 10 /r 66 0F 11 /r 66 0F 58 /r F2 0F 58 /r 66 0F 5E /r F2 0F 5E /r 66 0F 5F /r F2 0F 5F /r 66 0F 5D /r F2 0F 5D /r 66 0F 59 /r F2 0F 59 /r 66 0F 51 /r F2 0F 51 /r 66 0F 5C /r F2 0F 5C /r 66 0F 55 /r 66 0F 54 /r 66 0F 56 /r 66 0F 57 /r MOVAPD x1, x2/mdq MOVAPD x2/mdq, x1 MOVHPD mq, xm MOVHPD xm, mq MOVLPD mq, xm MOVLPD xm, mq MOVMSKPD rd, xm MOVSD x1, x2/mq MOVSD x2/mq, x1 MOVUPD x1, x2/mdq MOVUPD x2/mdq, x1 ADDPD x1, x2/mdq ADDSD x1, x2/mq DIVPD x1, x2/mdq DIVSD x1, x2/mq MAXPD x1, x2/mdq MAXSD x1, x2/mq MINPD x1, x2/mdq MINSD x1, x2/mq MULPD x1, x2/mdq MULSD x1, x2/mq SQRTPD x1, x2/mdq SQRTSD x1, x2/mq SUBPD x1, x2/mdq SUBSD x1, x2/mq ANDNPD x1, x2/mdq ANDPD x1, x2/mdq ORPD x1, x2/mdq XORPD x1, x2/mdq P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 Move 2 P DP FPs from x2/mdq to x1 (16-B Aligned or #GP) Move 2 P DP FPs from x1 to x2/mdq (16-B Aligned or #GP) Move DP FP from High qword of xm to mqword Move DP FP from mqword to High qword of xm Move DP FP from Low qword of xm to mqword Move DP FP from mqword to Low qword of xm Extract 2-bit sign Mask from xm and store in dword register Move Scalar DP FP dword x2/md to x1; if md, x1[127-32] 0 Move Scalar DP FP dword value from x1 register to x2/md Move 2 P DP FPs from x2/mdq to x1 (may be Unaligned) Move 2 P DP FPs from x1 to x2/mdq (may be Unaligned) Add 2 Packed DP FPs from x2/mdq into x1 Add low DP FPs from x2/mq into x1; x1[127-32] not changed Divide 2 P DP FPs in x2/mdq into x1 (x1 = quotient) Divide low DP FP in x2/mq into x1 (x1 = quotient) Return Maximum DP FPs between x2/mdq and/to x1 Return Maximum Scalar DP FP between x2/mq and/to x1 Return Minimum DP FPs between x2/mdq and/to x1 Return Minimum Scalar DP FP between x2/mq and/to x1 Multiply Packed DP FPs in x2/mdq into x1 Multiply low DP FP in x2/mq into x1 Set Square Roots of 2 P DP FPs in x2/mdq to x1 Set Square Root of low DP FP in x2/mdq to x1 Subtract 2 P DP FPs in x2/mdq from/to x1 Subtract low DP FP in x2/mq from/to x1 Bitwise logical AND NOT 2 P DP FPs in x2/mdq into x1 Bitwise logical AND 2 P DP FPs in x2/mdq into x1 Bitwise logical OR 2 P DP FPs in x2/mdq into x1 Bitwise logical XOR 2 P DP FPs x2/mdq into x1 Compare 2 P DP FPs x2/mdq, x1; dwords 1s x1 if =, else 0s Compare 2 P DP FPs x2/mdq, x1; dwords 1s x1 if , else 0s Compare 2 P DP FPs x2/mdq, x1; dwords 1s x1 if <, else 0s Compare 2 P DP FPs x2/mdq, x1; dwords 1s x1 if , else 0s Compare 2 P DP FP x2/mdq, x1; dwords 1s x1 if not , else 0s Compare 2 P DP FP x2/mdq, x1; dwords 1s x1 if not <, else 0s Compare 2 P DP FP x2/mdq, x1; dwords 1s x1 Ordered, else 0s Compare low DP FP x2/mdq, x1; dword 1s x1 Unord., else 0s Compare low DP FP x2/mq, x1; dword 1s x1 if =, else 0s Compare low DP FP x2/mq, x1; dword 1s x1 if , else 0s Compare low DP FP x2/mq, x1; dword 1s x1 if <, else 0s Compare low DP FP x2/mq, x1; dword 1s x1 if , else 0s Compare low DP FP x2/mq, x1; dword 1s x1 if not , else 0s Compare low DP FP x2/mq, x1; dword 1s x1 if not <, else 0s Compare low DP FP x2/mq, x1; dword 1s x1 if Ordered, else 0s Compare low DP FP x2/mq, x1; dword 1s x1 Unordered, else 0s Ordered compare low DP FP x2/mq & x1; set EFLAGS Unordered compare low DP FP x2/mq & x1; set EFLAGS none none none none none none none none none none none #I, #D, #O, #U, #P #I, #D, #O, #U, #P #I, #Z, #D, #O, #U, #P #I, #Z, #D, #O, #U, #P #I (with QNaN source), #D #I (with QNaN source), #D #I (with QNaN source), #D #I (with QNaN source), #D #I, #D, #O, #U, #P #I, #D, #O, #U, #P #I, #D, #O, #U, #P #I, #D, #P #I, #D, #O, #U, #P #I, #D, #O, #U, #P none none none none #I (if SNaN/QNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN/QNaN), #D #I (if SNaN), #D none

SSE2 Packed Arithmetic (DP Floating-Point) Instructions:

SSE2 Logical (DP Floating-Point) Instructions:

SSE2 Compare (DP Floating-Point) Instructions:

66 0F C2 /r 00 CMPEQPD x1, x2/mdq 66 0F C2 /r 02 CMPLEPD x1, x2/mdq 66 0F C2 /r 01 CMPLTPD x1, x2/mdq 66 0F C2 /r 04 CMPNEQPD x1, x2/mdq 66 0F C2 /r 06 CMPNLEPD x1, x2/mdq 66 0F C2 /r 05 CMPNLTPD x1, x2/mdq 66 0F C2 /r 07 CMPORDPD x1, x2/mdq 66 0F C2 /r 03 CMPUNORDPD x1, x2/mdq F2 0F C2 /r 00 CMPEQSD x1, x2/mq 66 0F C2 /r 02 CMPLESD x1, x2/mq 66 0F C2 /r 01 CMPLTSD x1, x2/mq 66 0F C2 /r 04 CMPNEQSD x1, x2/mq 66 0F C2 /r 06 CMPNLESD x1, x2/mq 66 0F C2 /r 05 CMPNLTSD x1, x2/mq 66 0F C2 /r 07 CMPORDSD x1, x2/mq 66 0F C2 /r 03 CMPUNORDSD x1, x2/mq

66 0F 2F /r 66 0F 2E /r
66 0F C6 /r ib

COMISD x1, x2/mq UCOMISD x1, x2/mq

SSE2 Shuffle and Unpack (DP Floating-Point) Instructions:

SHUFPD x1, x2/mdq, ib P4 Shuffle P DP FP x2/mdq to low or high of x1, selected by ib

66 0F 15 /r 66 0F 14 /r

UNPCKHPD x1, x2/mdq P4 Unpack & interleave DP FPs of High qwords x2/mdq and/to x1 none UNPCKLPD x1, x2/mdq P4 Unpack & interleave DP FPs of Low qwords x2/mdq and/to x1 none

SSE2 Conversion (DP Floating-Point) Instructions:

F3 0F E6 CVTDQ2PD x1, x2/mq F2 0F E6 CVTPD2DQ x1, x2/mdq 66 0F 2D /r CVTPD2PI mm, xm/mdq 66 0F 5A /r CVTPD2PS x1, x2/mdq 66 0F 2A /r CVTPI2PD xm, mm/mq 0F 5A /r CVTPS2PD x1, x2/mq F2 0F 2D /r CVTSD2SI rd, xm/mq F2 0F 5A /r CVTSD2SS x1, x2/mq F2 0F 2A /r CVTSI2SD xm, rmd F3 0F 5A /r CVTSS2SD x1, x2/md 66 0F E6 CVTTPD2DQ x1, x2/mdq 66 0F 2C /r CVTTPD2PI mm, xm/mdq F2 0F 2C /r CVTTSD2SI rd, xm/mq P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 Convert 2 P signed Dwords from x2/mq to 2 P DP FPs in x1 Convert 2 P DP FPs from x2/mdq to 2 P signed Dwords in x1 Convert 2 P DP FPs from xm/mdq to 2 P S Dwords in mm Convert 2 P DP FPs form x2/mdq to 2 Packed SP FPs in x1 Convert 2 P S dwords from mm/mq to 2 P DP FPs in xm Convert 2 P SP FPs from x2/mq to 2 P DP FPs in x1 Convert DP FP from xm/mq to S dword in rd Convert DP FP from x2/mq to SP FP in x1 Convert Signed dword from reg/mem dword to DP FP in xm Convert SP FP from x2/md to DP FP in x1 Convert 2 P DP FPs x2/mdq to 2 P S Truncated dwords in x1 Convert 2 P DP FPs xm/mdq to 2 P S Truncated dwords in mm Convert DP FP form xm/mq to Signed Truncated dword in rd none #I, #P #I, #P #I, #D, #O, #U, #P none #I, #D #I, #P #I, #D, #O, #U, #P none #I, #D #I, #P #I, #P #I, #P #P #I, #P #I, #P none none none none none none none none none none none none none none none none none none none none none none none none none none none ZF TS none none none

SSE2 Packed Single-Precision Floating-Point Instructions:

0F 5B /r CVTDQ2PS x1, x2/mdq P4 Convert 4 P S dwords from x2/mdq to 4 SP FPs in x1 66 0F 5B /r CVTPS2DQ x1, x2/mdq P4 Convert 4 P SP FPs from x2/mdq to 4 P S dwords in x1 F3 0F 5B /r CVTTPS2DQ x1, x2/mdq P4 Convert 4 SP FPs from x2/mdq to 4 S Truncated dwords in x1

SSE2 128-Bit SIMD Integer Instructions:

66 0F 6F /r 66 0F 7F /r F3 0F 6F /r F3 0F 7F /r F2 0F D6 F3 0F D6 0F D4 /r 66 0F D4 /r 0F F4 /r 66 0F F4 /r
66 0F 70 /r ib F3 0F 70 /r ib F2 0F 70 /r ib 66 0F 73 /7 ib 66 0F 73 /3 ib

MOVDQA x1, x2/mdq MOVDQA x2/mdq, x1 MOVDQU x1, x2/mdq MOVDQU x2/mdq, x1 MOVDQ2Q mm, xm MOVQ2DQ xm, mm PADDQ m1, m2/mq PADDQ x1, x2/mdq PMULUDQ m1, m2/mq PMULUDQ x1, x2/mdq PSHUFD x1, x2/mdq
PSHUFHW x1, x2/mdq, ib PSHUFLW x1, x2/mdq, ib

0F FB /r 66 0F FB /r
66 0F 6A /r 66 0F 6C /r

PSLLDQ x1, ib PSRLDQ x1, ib PSUBQ m1, m2/mq PSUBQ x1, x2/mdq
PUNPCKHQDQ x1, x2/mdq PUNPCKLQDQ x1, x2/mdq

P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 P4 2 2 4 4

Move Aligned Dqword x2/mdq to x1 (16-B aligned or #GP) Move Aligned Dqword x1 to x2/mdq (16-B aligned or #GP) Move Unaligned Dqword x2/mdq to x1 Move Unaligned Dqword x1 to x2/mdq Move low Qword from xm to mm register Move Qword from mm register to low qword of xm register Add Qword m2/mq into m1 (EFLAGS unaffected) Packed Add Qwords m2/mdq into x1 (EFLAGS unaffected) Multiply Unsigned Dwords m1 and/to m2/mq Packed Multiply Unsigned Dwords x1 and/to x2/mdq Shuffle Dwords in x2/mdq to x1 in order selected by ib Shuffle High Words in x2/mdq to x1 in order selected by ib Shuffle Low Words in x2/mdq to x1 in order selected by ib Shift x1 Left by ib bytes while shifting 0s in right Shift x1 Right by ib bytes while shifting 0s in left Subtract Qword m2/mq from/to m1 Packed Subtract Qwords x2/mdq from/to x1 Unpack & Interleave High Qwords from x2/mdq and/to x1 Unpack & Interleave Low Qwords from x2/mdq and/to x1 Flushes Cache Line containing mb Serializes load-from-memory instruction operations Selectively write B from m1 to memory using m2 B Mask Serialize load-from-memory & store-from-memory operations Non-temporal Move Dqword from xm to mdq Non-temporal Move dword from rd to md Non-temporal Move P DP FPs from xm to mdq Processor hint & delay to improve spin-wait loop performance Adjust RPL of reg/mem word to not less than RPL of rw Clear Task Switched flag (TS) in CR0 Halt (start: interrupts, debug except., BINIT#, INIT#, RESET#) Flush internal caches; initiate flushing external caches Invalidate TLB Entry for Page that contains m

SSE2 Cacheability Control and Instruction Ordering Instructions:

0F AE /7 CLFLUSH mb 0F AE /5 LFENCE 0F F7 /r MASKMOVDQU m1, m2 0F AE /6 MFENCE 66 0F E7 /r MOVNTDQ mdq, xm 0F C3 /r MOVNTI md, rd 66 0F 2B /r MOVNTPD mdq, xm F3 90 PAUSE 63 /rw 0F 06 F4 0F 08 0F 01 /7 *@ ARPL rmw, rw CLTS HLT INVD INVLPG m

System Instructions (* - Protected Mode; @ - CPL 3 Application, else need CPL 0):

0F 02 /r 0F 01 /2 0F 01 /3 0F 00 /2 0F 01 /6 0F 03 /r 0F 00 /3 0F 22 /4 0F 22 /n 0F 23 /n 0F 20 /4 0F 20 /n 0F 21 /n 0F 24 /n 0F 26 /n 0F 32 0F 33 0F 31 0F AA 0F 01 /0 0F 01 /1 0F 00 /0 0F 01 /4 0F 00 /1 0F 34 0F 35 0F 00 /4 0F 00 /5 0F 09 0F 30

*@ LAR rv, rmv LGDT m LIDT m * LLDT rmw LMSW rmw *@ LSL rv, rmv * LTR rmw MOV CR4, rd MOV CRn, rd MOV DRn, rd MOV rd, CR4 MOV rd, CRn MOV rd, DRn MOV rd, TRn MOV TRn, rd RDMSR RDPMC RDTSC RSM @ SGDT m @ SIDT m *@ SLDT rmw @ SMSW rmw *@ STR rmw *@ SYSENTER * SYSEXIT *@ VERR rmw *@ VERW rmw WBINVD WRMSR PAVGUSB m1, m2/mq PF2ID m1, m2/mq PF2IW mm, m2/mq PFACC m1, m2/mq PFADD m1, m2/mq PFCMPEQ m1, m2/mq PFCMPGE m1, m2/mq PFCMPGT m1, m2/mq PFMAX m1, m2/mq PFMIN m1, m2/mq PFMUL m1, m2/mq PFNACC mm, m2/mq PFPNACC mm, m2/mq PFRCP m1, m2/mq PFRCPIT1 m1, m2/mq PFRCPIT2 m1, m2/mq PFRSQIT1 m1, m2/mq PFRSQRT m1, m2/mq PFSUB m1, m2/mq PFSUBR m1, m2/mq PI2FD m1, m2/mq PI2FW mm, m2/mq PMULHRW m1, m2/mq PREFETCH mb PREFETCHW mb PSWAPD mm, m2/mq FEMMS

2 2 2 2 2 2 2 5 3 3 5 3 3 3 3 5 P2 5 5 2 2 2 2 2 P2 P2 2 2 4 5 3D 3D 3E 3D 3D 3D 3D 3D 3D 3D 3D 3E 3E 3D 3D 3D 3D 3D 3D 3D 3D 3E 3D 3D 3D 3E

Load: rv rmv mask by FF00/00FxFF00 hex (16/32); set ZF Load lower 16-bit limit, upper 24-/32-bit base m into GDTR Load lower 16-bit limit, upper 24-/32-bit base m into IDTR Load selector rmw into Local Descriptor Table reg (LDTR) Load reg/mem word into Machine Status Word of CR0[15-0] Load: rv Segment Limit (20-bits) of selector rmv; set ZF Load reg/mem word into Task Register Move register dword into Control Register 4 Move dword register into Control Register n (= 0, 2, or 3) Move dword register into Debug register n (= 0-3, 6, or 7) Move Control Register 4 into dword register Move Control Register n (= 0, 2, or 3) into dword register Move Debug register n (= 0-3, 6, or 7) into dword register Move Test Register n (= 6, 7) into register dword Move register dword into Test Register n (= 6, 7) Read 64-bit Model Specific Register by ECX to EDX:EAX Read Performance Monitoring Counter by ECX to EDX:EAX Read Time Stamp Counter into EDX:EAX (not serializing) Resume (return control) to interrupted program from SMM Store lower 16-bit limit, upper 24-/32-bit base GDTR to m Store lower 16-bit limit, upper 24-/32-bit base IDTR to m Store lower 16-bit limit, upper 24-/32-bit base LDTR to rmw Store Machine Status Word to reg/mem word of CR0[15-0] Store segment selector from Task Register to reg/mem word Fast call from level 3 code to level 0 operating system code Fast call from level 0 code to level 3 user application code Set ZF = 1 if segment of selector at rmw address can be read Set ZF = 1 if segment of selector at rmw can be written Write Back & flush internal caches; initiate in external caches Write EDX:EAX to 64-bit Model Specific Register by ECX Packed rounded Average Unsigned Bytes m2/mq and/to m1 Packed truncated convert SP FP m2/mq into 32-bit Integer m1 Packed truncated convert SP FP m2/mq into 16-bit Integer mm Packed SP FP Accumulate 2 words m2/mq and/to low, high m1 Packed SP FP Addition of m2/mq and/to m1 Packed FP Compare dwords m2/mq to m1; 1s m1 if =, else 0s Packed FP Compare dwords m2/mq to m1; 1s m1 if , else 0s Packed FP Compare dwords m2/mq to m1; 1s m1 if >, else 0s Return Packed Maximum of SP FPs m2/mq and/to m1 Return Packed Minimum of SP FPs m2/mq and/to m1 Packed SP FP Multiply m2/mq into m1 Packed SP FP Negative Accumulate 2 dwords to low, high mm Packed SP FP mixed Positive-Negative Accumulate 2 dwords Packed scalar FP Reciprocal approx.; result high & low B m1 Packed FP Reciprocal first Iteration step Packed FP Reciprocal second Iteration step Packed FP Reciprocal Square Root of first Iteration step Packed FP Reciprocal Square Root approximation Packed SP FP Subtract m2/mq from/to m1 Packed SP FP Subtract m1 from m2/mq; store result to m1 Packed convert signed 32-bit Integer m2/mq to SP FP m1 Packed convert signed 16-bit Integer m2/mq to SP FP mm Packed 16-bit integer Multiply m2/mq into m1 with Rounding Prefetch 32 bytes or more into L1 data cache, exclusive MESI Prefetch 32 B or > into L1 data cache & set MESI to modified Packed Swap high and low Doublewords of m2/mq to mm

ZF none none none none ZF none undefined undefined undefined undefined undefined undefined undefined undefined none none none all none none none none none IF, RF, VM none ZF ZF none none none none none none none none none none none none none none none none none none none none none none none none none none none none none

3DNow! Floating-Point Instructions:

0F 0F /r BF 0F 0F /r 1D 0F 0F /r 1C 0F 0F /r AE 0F 0F /r 9E 0F 0F /r B0 0F 0F /r 90 0F 0F /r A0 0F 0F /r A4 0F 0F /r 94 0F 0F /r B4 0F 0F /r 8A 0F 0F /r 8E 0F 0F /r 96 0F 0F /r A6 0F 0F /r B6 0F 0F /r A7 0F 0F /r 97 0F 0F /r 9A 0F 0F /r AA 0F 0F /r 0D 0F 0F /r 0C 0F 0F /r B7 0F 0D /0 0F 0D /1 0F 0F /r BB 0F 0E

3DNow! Performance-Enhancement Instructions:

3D Faster Entry/Exit of MMX or floating-point State

Floating-Point Instruction Abbreviation and Operand Legend: BCD The abbreviation stands for Binary Coded Decimal, which is the format that is used to perform arithmetic operations. m32fp This 4-byte operand contains a single-precision floating-point number, which is less accurate than double precision. m64fp An 8-byte double precision FP number operand, which takes the same length of calculation time as single precision. m80fp A 10-byte operand which contains the binary coded decimal format recognized by the FBLD & FBSTP instructions. m16int, m32int These are 2-byte or 4-byte memory operands, which contains a signed integer in 2's-complement notation. mem10r This 10-byte full precision FP number operand is for maximum accuracy of double precision number calculations. mem14, mem94 These are 14-/94-byte buffers, which are used for saving and restoring the FPU machine state information. ST(0), ST(i) These 2 operands are for the top element and element number i (range 0 through 7) of the floating-point stack. The Floating-Point Instruction Set:
In the opcode column, w is for the WAIT/FWAIT instruction, and +i (with a range of 0-7) is a number used when an operand is ST(i).

x87 Data Transfer Instructions:

w DF /4 w DF /6 DA C0+i DA D0+i DA C8+i DB C0+i DB D0+i DB C8+i DB D8+i DA D8+i w DF /0 w DB /0 w DF /5 w DF /2 w DB /2 w DF /3 w DB /3 w DF /7 w D9 /0 w DD /0 w DB /5 w D9 C0+i w D9 /2 w DD /2 w DD D0+i w D9 /3 w DD /3 w DB /7 w DD D8+i w D9 C9 w D9 C8+i w w w w w D9 E1 D8 /0 DC /0 D8 C0+i DC C0+i FBLD m80fp FBSTP m80fp FCMOVB ST(0), ST(i) FCMOVBE ST(0), ST(i) FCMOVE ST(0), ST(i) FCMOVNB ST(0), ST(i) FCMOVNBE ST(0), ST(i) FCMOVNE ST(0), ST(i) FCMOVNU ST(0), ST(i) FCMOVU ST(0), ST(i) FILD m16int FILD m32int FILD m64int FIST m16int FIST m32int FISTP m16int FISTP m32int FISTP m64int FLD m32fp FLD m64fp FLD mem10r FLD ST(i) FST m32fp FST m64fp FST ST(i) FSTP m32fp FSTP m64fp FSTP mem10r FSTP ST(i) FXCH FXCH ST(i) FABS FADD m32fp FADD m64fp FADD ST(0), ST(i) FADD ST(i), ST(0) P2 P2 P2 P2 P2 P2 P2 P2 Convert BCD to double-extended; push: ST(0) m80fp Convert ST(0) to 18-digit P BCD; Pop: m80fp ST(0) If Below (CF = 1): ST(0) ST(i) If Below or Equal (CF = 1, ZF = 1): ST(0) ST(i) If Equal (ZF = 1): ST(0) ST(i) If Not Below (CF = 0): ST(0) ST(i) If Not Below or Equal (CF = 0 & ZF = 0): ST(0) ST(i) If Not Equal (ZF = 0): ST(0) ST(i) If Not Unordered (PF = 0): ST(0) ST(i) If Unordered (PF = 1): ST(0) ST(i) Convert S m16int to double-extended; push: ST(0) m16int Convert S m32int to double-extended; push: ST(0) m32int Convert S m64int to double-extended; push: ST(0) m64int Convert ST(0) to S integer; m16int ST(0) Convert ST(0) to S integer; m32int ST(0) Convert ST(0) to S integer; m16int ST(0); Pop reg stack Convert ST(0) to S integer; m32int ST(0); Pop reg stack Convert ST(0) to S integer; m64int ST(0); Pop reg stack Push register stack: ST(0) m32fp Push register stack: ST(0) m64fp Push register stack: ST(0) mem10r Push register stack: ST(0) ST(i) Copy: m32fp ST(0) Copy: m64fp ST(0) Copy: ST(i) ST(0) Copy: m32fp ST(0); pop register stack Copy: m64fp ST(0); pop register stack Copy: mem10r ST(0); pop register stack Copy: ST(i) ST(0); pop register stack Exchange contents of ST(0) and ST(1) Exchange contents of ST(0) and ST(i) ST(0) |ST(0)| ST(0) ST(0) + m32fp ST(0) ST(0) + m64fp ST(0) ST(0) + ST(i) ST(i) ST(0) + ST(i) C1; #IS C1; #IS, #IA, #P C1; #IS C1; #IS C1; #IS C1; #IS C1; #IS C1; #IS C1; #IS C1; #IS C1; #IS C1; #IS C1; #IS C1; #IS, #IA, #P C1; #IS, #IA, #P C1; #IS, #IA, #P C1; #IS, #IA, #P C1; #IS, #IA, #P C1; #IS, #IA, #D C1; #IS, #IA, #D C1; #IS, #IA, #D C1; #IS, #IA, #D C1; #IS, #IA, #O, #U, #P C1; #IS, #IA, #O, #U, #P C1; #IS, #IA, #O, #U, #P C1; #IS, #IA, #O, #U, #P C1; #IS, #IA, #O, #U, #P C1; #IS, #IA, #O, #U, #P C1; #IS, #IA, #O, #U, #P C1; #IS C1; #IS

x87 Basic Arithmetic Instructions:

C1; #IS C1; #IS, #IA, #D, #O, #U, #P C1; #IS, #IA, #D, #O, #U, #P C1; #IS, #IA, #D, #O, #U, #P C1; #IS, #IA, #D, #O, #U, #P

w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w

DE C1 DE C0+i D9 E0 D8 /6 DC /6 D8 F0+i DC F8+i DE F9 DE F8+i D8 /7 DC /7 D8 F8+i DC F0+i DE F1 DE F0+i DE /0 DA /0 DE /6 DA /6 DE /7 DA /7 DE /1 DA /1 DE /4 DA /4 DE /5 DA /5 D8 /1 DC /1 D8 C8+i DC C8+i DE C9 DE C8+i D9 F8 D9 F5 D9 FC D9 FD D9 FA D8 /4 DC /4 D8 E0+i DC E8+i DE E9 DE E8+i D8 /5 DC /5 D8 E8+i DC E0+i DE E1 DE E0+i D9 F4 D8 /2 DC /2 D8 D1 D8 D0+i DB F0+i

FADDP FADDP ST(i), ST(0) FCHS FDIV m32fp FDIV m64fp FDIV ST(0), ST(i) FDIV ST(i), ST(0) FDIVP FDIVP ST(i), ST(0) FDIVR m32fp FDIVR m64fp FDIVR ST(0), ST(i) FDIVR ST(i), ST(0) FDIVRP FDIVRP ST(i), ST(0) FIADD m16int FIADD m32int FIDIV m16int FIDIV m32int FIDIVR m16int FIDIVR m32int FIMUL m16int FIMUL m32int FISUB m16int FISUB m32int FISUBR m16int FISUBR m32int FMUL m32fp FMUL m64fp FMUL ST(0), ST(i) FMUL ST(i), ST(0) FMULP FMULP ST(i), ST(0) FPREM FPREM1 FRNDINT FSCALE FSQRT FSUB m32fp FSUB m64fp FSUB ST(0), ST(i) FSUB ST(i), ST(0) FSUBP FSUBP ST(i), ST(0) FSUBR m32fp FSUBR m64fp FSUBR ST(0), ST(i) FSUBR ST(i), ST(0) FSUBRP FSUBRP ST(i), ST(0) FXTRACT FCOM m32fp FCOM m64fp FCOM FCOM ST(i) FCOMI ST(0), ST(i)

ST(1) ST(0) + ST(1); Pop register stack C1; #IS, #IA, #D, #O, #U, #P ST(i) ST(0) + ST(i); Pop register stack C1; #IS, #IA, #D, #O, #U, #P ST(0) -ST(0) C1; #IS ST(0) ST(0) / m32fp C1; #IS, #IA, #Z, #D, #O, #U, #P ST(0) ST(0) / m64fp C1; #IS, #IA, #Z, #D, #O, #U, #P ST(0) ST(0) / ST(i) C1; #IS, #IA, #Z, #D, #O, #U, #P ST(i) ST(i) / ST(0) C1; #IS, #IA, #Z, #D, #O, #U, #P ST(1) ST(1) / ST(0); Pop register stack C1; #IS, #IA, #Z, #D, #O, #U, #P ST(i) ST(i) / ST(0); Pop register stack C1; #IS, #IA, #Z, #D, #O, #U, #P ST(0) m32fp / ST(0) C1; #IS, #IA, #Z, #D, #O, #U, #P ST(0) m64fp / ST(0) C1; #IS, #IA, #Z, #D, #O, #U, #P ST(0) ST(i) / ST(0) C1; #IS, #IA, #Z, #D, #O, #U, #P ST(i) ST(0) / ST(i) C1; #IS, #IA, #Z, #D, #O, #U, #P ST(1) ST(0) / ST(1); Pop register stack C1; #IS, #IA, #Z, #D, #O, #U, #P ST(i) ST(0) / ST(i); Pop register stack C1; #IS, #IA, #Z, #D, #O, #U, #P ST(0) ST(0) + m16int C1; #IS, #IA, #D, #O, #U, #P ST(0) ST(0) + m32int C1; #IS, #IA, #D, #O, #U, #P ST(0) ST(0) / m16int C1; #IS, #IA, #Z, #D, #O, #U, #P ST(0) ST(0) / m32int C1; #IS, #IA, #Z, #D, #O, #U, #P ST(0) m16int / ST(0) C1; #IS, #IA, #Z, #D, #O, #U, #P ST(0) m32int / ST(0) C1; #IS, #IA, #Z, #D, #O, #U, #P ST(0) ST(0) * m16int C1; #IS, #IA, #D, #O, #U, #P ST(0) ST(0) * m32int C1; #IS, #IA, #D, #O, #U, #P ST(0) ST(0) - m16int C1; #IS, #IA, #D, #O, #U, #P ST(0) ST(0) - m32int C1; #IS, #IA, #D, #O, #U, #P ST(0) m16int - ST(0) C1; #IS, #IA, #D, #O, #U, #P ST(0) m32int - ST(0) C1; #IS, #IA, #D, #O, #U, #P ST(0) ST(0) * m32fp C1; #IS, #IA, #D, #O, #U, #P ST(0) ST(0) * m64fp C1; #IS, #IA, #D, #O, #U, #P ST(0) ST(0) * ST(i) C1; #IS, #IA, #D, #O, #U, #P ST(i) ST(0) * ST(i) C1; #IS, #IA, #D, #O, #U, #P ST(1) ST(0) * ST(1); Pop register stack C1; #IS, #IA, #D, #O, #U, #P ST(i) ST(i) * ST(0); Pop register stack C1; #IS, #IA, #D, #O, #U, #P ST(0) Partial Remainder of ST(0) / ST(1) (not IEEE) C0-C3; #IS, #IA, #D, #U 387 ST(0) Partial Remainder of ST(0) / ST(1) (IEEE Std 754) C0-C3; #IS, #IA, #D, #U ST(0) round ST(0) to an integer C1; #IS, #IA, #D, #P ST(1) ST(0) ST(0) * 2 C1; #IS, #IA, #D, #O, #U, #P ST(0) Square Root of ST(0) C1; #IS, #IA, #D, #P ST(0) ST(0) - m32fp C1; #IS, #IA, #D, #O, #U, #P ST(0) ST(0) - m64fp C1; #IS, #IA, #D, #O, #U, #P ST(0) ST(0) - ST(i) C1; #IS, #IA, #D, #O, #U, #P ST(i) ST(i) - ST(0) C1; #IS, #IA, #D, #O, #U, #P ST(1) ST(1) - ST(0); Pop register stack C1; #IS, #IA, #D, #O, #U, #P ST(i) ST(i) - ST(0); Pop register stack C1; #IS, #IA, #D, #O, #U, #P ST(0) m32fp - ST(0) C1; #IS, #IA, #D, #O, #U, #P ST(0) m64fp - ST(0) C1; #IS, #IA, #D, #O, #U, #P ST(0) ST(i) - ST(0) C1; #IS, #IA, #D, #O, #U, #P ST(i) ST(0) - ST(i) C1; #IS, #IA, #D, #O, #U, #P ST(1) ST(0) - ST(1); Pop register stack C1; #IS, #IA, #D, #O, #U, #P ST(i) ST(0) - ST(i); Pop register stack C1; #IS, #IA, #D, #O, #U, #P ST(1) exponent; ST(0) significand, push to reg stack C1; #IS, #IA, #Z, #D Compare: ST(0) - m32fp Compare: ST(0) - m64fp Compare: ST(0) - ST(1) Compare: ST(0) - ST(i) P2 Compare: ST(0) - ST(i); set EFLAGS C0-C3; #IS, #IA, #D C0-C3; #IS, #IA, #D C0-C3; #IS, #IA, #D C0-C3; #IS, #IA, #D C1; #IS, #IA

x87 Comparison Instructions:

DF F0+i D8 D9 D8 /3 DC /3 D8 D8+i DE D9 DE /2 DA /2 DE /3 DA /3 D9 E4 DD E1 DD E0+i DB E8+i DF E8+i DD E9 DD E8+i DA E9 w D9 E5 w w w w w w w w w w w w w w D9 F0 D9 FF D9 F3 D9 F2 D9 FE D9 FB w D9 F1 w D9 F9 w w w w w w w D9 E8 D9 EA D9 E9 D9 EC D9 ED D9 EB D9 EE

FCOMIP FCOMP FCOMP m32fp FCOMP m64fp FCOMP ST(i) FCOMPP FICOM m16int FICOM m32int FICOMP m16int FICOMP m32int FTST FUCOM FUCOM ST(i) FUCOMI ST(i) FUCOMIP ST(i) FUCOMP FUCOMP ST(i) FUCOMPP FXAM F2XM1 FCOS FPATAN FPTAN FSIN FSINCOS FYL2X FYL2XP1 FLD1 FLDL2E FLDL2T FLDLG2 FLDLN2 FLDPI FLDZ FCLEX FDECSTP FFREE ST(i) FINCSTP FINIT FLDENV mem14 FLDCW m16int FNCLEX FNINIT FNOP FNSAVE mem94 FNSTCW m16int FNSTENV mem14 FNSTSW AX FNSTSW m16int FRSTOR mem94 FSAVE mem94 FSTCW m16int FSTENV mem14 FSTSW AX

P2 Compare: ST(0) - ST(1); set EFLAGS; Pop register stack Compare: ST(0) - ST(1); Pop register stack Compare: ST(0) - m32fp; Pop register stack Compare: ST(0) - m64fp, Pop register stack Compare: ST(0) - ST(i); Pop register stack Compare: ST(0) - ST(1); Pop register stack twice Compare: ST(0) - m16int Compare: ST(0) - m32int Compare: ST(0) - m16int; Pop register stack Compare: ST(0) - m32int; Pop register stack Compare: ST(0) - 0.0 387 Unordered Compare: ST(0) - ST(1) 387 Unordered Compare: ST(0) - ST(i) P2 Unordered Compare: ST(0) - ST(i); set EFLAGS P2 Unordered Compare: ST(0) - ST(i); set EFLAGS, pop 387 Unordered Compare: ST(0) - ST(1); Pop register stack 387 Unordered Compare: ST(0) - ST(i); Pop register stack 387 Unordered Compare: ST(0) - ST(1); Pop register stack twice C0C3 type of value in ST(0) (Classify value)

C1; #IS, #IA C0-C3; #IS, #IA, #D C0-C3; #IS, #IA, #D C0-C3; #IS, #IA, #D C0-C3; #IS, #IA, #D C0-C3; #IS, #IA, #D C0-C3; #IS, #IA, #D C0-C3; #IS, #IA, #D C0-C3; #IS, #IA, #D C0-C3; #IS, #IA, #D C0-C3; #IS, #IA, #D C0-C3; #IS, #IA, #D C0-C3; #IS, #IA, #D C1; #IS, #IA C1; #IS, #IA C0-C3; #IS, #IA, #D C0-C3; #IS, #IA, #D C0-C3; #IS, #IA, #D C0, C1, C2, C3

x87 Transcendental Instructions:

ST(0) (2.0 ST(0) - 1) (where -1.0 ST(0) +1.0) C1; #IS, #IA, #D, #U, #P 387 ST(0) Cosine(ST(0)) C1, C2; #IS, #IA, #D, #U, #P ST(0) Arctan(ST(1) / ST(0)); pop register stack C1; #IS, #IA, #D, #U, #P Push register to stack: ST(0) Tan(ST(0)) C1, C2; #IS, #IA, #D, #U, #P 387 ST(0) Sine(ST(0)) C1, C2; #IS, #IA, #D, #P 387 ST(1) Sine; ST(0) Cos(ST(0)), push to register stack C1, C2; #IS, #IA, #D, #P ST(0) ST(1) * Log2ST(0); pop register stack C1; #IS, #IA, #Z, #D, #O, #U, #P ST(0) ST(1) * Log2(ST(0) + 1.0); pop reg stack C1; #IS, #IA, #D, #O, #U, #P Push register stack: ST(0) +1.0 Push register stack: ST(0) Log2 ( Push register stack: ST(0) Log210 ( Push register stack: ST(0) Log102 ( Push register stack: ST(0) Log2 ( Push register stack: ST(0) ( Push register stack: ST(0) +0.0 C1; #IS C1; #IS C1; #IS C1; #IS C1; #IS C1; #IS C1; #IS

x87 Load Constants:

1.442695040888963520) 3.321928094887362560) 0.301029995663981184) 0.693147180559945344) 3.141592653589793280)

x87 FPU Control Instructions:

9B DB E2 w D9 F6 w DD C0+i w D9 F7 9B DB E3 w D9 /4 w D9 /5 DB E2 DB E3 w D9 D0 DD /6 D9 /7 D9 /6 DF E0 DD /7 w DD /4 w DD /6 w D9 /7 w D9 /6 w DF E0 Clear (check unmasked) FP Exception flags IE, DE, ZE, OE, UE, PE, SF, B Decrement Stack Pointer (top field of FPU status register) C1 Set tag for ST(i) to empty undefined Increment Stack Pointer (top field of FPU status register) C1 Initialize (check unmasked exceptions) FPU C0, C1, C2, C3 FPU Environment mem14 (check unmasked exceptions) C0, C1, C2, C3 FPU Control Word m16int undefined Clear Exceptions (nowait unmask exceptions) IE, DE, ZE, OE, UE, PE, SF, ES, B Initialize FPU (nowait unmask exceptions) C0, C1, C2, C3 No Operation (takes up space in execution, only affects EIP) undefined mem94 87 state (check unmasked exceptions) C0, C1, C2, C3 m16int FPU Control Word (nowait unmask exceptions) undefined mem14 FPU Environment (nowait unmask exceptions) undefined AX FPU Status Word (nowait unmask exceptions) undefined m16int FPU Status Word (nowait unmask exceptions) undefined FPU state mem94 C0, C1, C2, C3 mem94 FPU state (check unmasked exceptions) C0, C1, C2, C3 m16int FPU Control Word (check unmasked exceptions) undefined mem14 FPU Environment (check unmasked exceptions) undefined AX FPU Status Word (check unmasked exceptions) undefined

w DD /7 9B 9B 0F AE /1 0F AE /0

FSTSW m16int FWAIT WAIT FXRSTOR m FXSAVE m

m16int FPU Status Word (check unmasked exceptions) Wait until pending unmasked FP exceptions are completed Wait until pending unmasked FP exceptions are completed P3 Restore: x87, MMX, XMM, & MXCSR regs m (512 B) P3 Save: m (512 B) x87, MMX, XMM, & MXCSR registers

undefined undefined undefined none none

x87 FPU and SIMD State Management Instructions:

IA-32 Instruction Format:

Instruction Prefixes Up to 4 prefixes of 1 byte each Opcode 1 or 2 byte opcode ModR/M 1 byte (if required) SIB Displacement Immediate 1 byte (if required) Address displacement Immediate data of 1, 2, or 4 bytes/none 1, 2, or 4 bytes/none

ModR/M:
7 Mod 65 Reg/ Opcode 32 R/M 0

SIB:
7 Scale 65 Index 32 Base 0

16-Bit & 32-Bit Addressing Forms with the ModR/M Byte:

rb(/r) rw(/r) rd(/r) mm(/r) xm(/r) /digit (Opcode) REG = 16-Bit Effective Address [BX+SI] [BX+DI] [BP+SI] [BP+DI] [SI] [DI] disp16 [BX] [BX+SI]+disp8 [BX+DI]+disp8 [BP+SI]+disp8 [BP+DI]+disp8 [SI]+disp8 [DI]+disp8 [BP]+disp8 [BX]+disp8 [BX+SI]+disp16 [BX+DI]+disp16 [BP+SI]+disp16 [BP+DI]+disp16 [SI]+disp16 [DI]+disp16 [BP]+disp16 [BX]+disp16 AL AX EAX MM0 XMM0 0 000 32-Bit Effective Address [EAX] [ECX] [EDX] [EBX] [][]4 disp325 [ESI] [EDI] [EAX]+disp86 [ECX]+disp8 [EDX]+disp8 [EBX]+disp8 [][]+disp8 [EBP]+disp8 [ESI]+disp8 [EDI]+disp8 [EAX]+disp32 [ECX]+disp32 [EDX]+disp32 [EBX]+disp32 [][]+disp32 [EBP]+disp32 [ESI]+disp32 [EDI]+disp32 Mod R/M 00 000 001 010 011 100 101 110 111 01 000 001 010 011 100 101 110 111 10 000 001 010 011 100 101 110 111 00 01 02 03 04 05 06 07 40 41 42 43 44 45 46 47 80 81 82 83 84 85 86 87 CL CX ECX MM1 XMM1 1 001 08 09 0A 0B 0C 0D 0E 0F 48 49 4A 4B 4C 4D 4E 4F 88 89 8A 8B 8C 8D 8E 8F DL DX EDX MM2 XMM2 2 010 BL BX EDX MM3 XMM3 3 011 AH SP ESP MM4 XMM4 4 100 CH BP EBP MM5 XMM5 5 101 DH SI ESI MM6 XMM6 6 110 30 31 32 33 34 35 36 37 70 71 72 73 74 75 76 77 B0 B1 B2 B3 B4 B5 B6 B7 BH DI EDI MM7 XMM7 7 111 38 39 3A 3B 3C 3D 3E 3F 78 79 7A 7B 7C 7D 7E 7F B8 B9 BA BB BC BD BE BF

Value of ModR/M Byte (in Hexadecimal) 10 18 20 28 11 19 21 29 12 1A 22 2A 13 1B 23 2B 14 1C 24 2C 15 1D 25 2D 16 1E 26 2E 17 1F 27 2F 50 58 60 68 51 59 61 69 52 5A 62 6A 53 5B 63 6B 54 5C 64 6C 55 5D 65 6D 56 5E 66 6E 57 5F 67 6F 90 98 A0 A8 91 99 A1 A9 92 9A A2 AA 93 9B A3 AB 94 9C A4 AC 95 9D A5 AD 96 9E A6 AE 97 9F A7 AF

EAX ECX EDX EBX ESP EBP ESI EDI

AX CX DX BX SP BP SI DI

AL CL DL BL AH CH DH BH

MM0 MM1 MM2 MM3 MM4 MM5 MM6 MM7

XMM 0 XMM 1 XMM 2 XMM 3 XMM 4 XMM 5 XMM 6 XMM 7

11

000 001 010 011 100 101 110 111

C0 C1 C2 C3 C4 C5 C6 C7

C8 C9 CA CB CC CD CE CF

D0 D1 D2 D3 D4 D5 D6 D7

D8 D9 DA DB DC DD DE DF

E0 E1 E2 E3 E4 E5 E6 E7

E8 E9 EA EB EC ED EE EF

F0 F1 F2 F3 F4 F5 F6 F7

F8 F9 FA FB FC FD FE FF

Notes:
1. 2. 3. 4. 5. 6. The default segment register is SS for the effective addresses containing a BP index; DS register is for other effective addresses. The disp16 nomenclature denotes a 16-bit displacement that follows behind ModR/M byte and that is added to the indexs value. The disp8 nomenclature denotes an 8-bit displacement following ModR/M byte and that is sign-extended and added to the index. The [][] nomenclature means a SIB (Scale, Index, & Base fields) byte follows ModR/M (Mod, reg/opcode, & R/M fields) byte. The disp32 nomenclature denotes a 32-bit displacement that follows ModR/M byte (or SIB byte if present) that is added to index. The disp8 denotes an 8-bit displacement that follows ModR/M byte (SIB byte if present) that is sign-extended and added to index. EAX 0 000 SS 00 Index 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 00 08 10 18 20 28 30 38 40 48 50 58 60 68 70 78 80 88 90 98 A0 A8 B0 B8 C0 C8 D0 D8 E0 E8 F0 F8 ECX 1 001 01 09 11 19 21 29 31 39 41 49 51 59 61 69 71 79 81 89 91 99 A1 A9 B1 B9 C1 C9 D1 D9 E1 E9 F1 F9 EDX EBX ESP [*] 2 3 4 5 010 011 100 101 Value of SIB Byte (in Hexadecimal) 02 03 04 05 0A 0B 0C 0D 12 13 14 15 1A 1B 1C 1D 22 23 24 25 2A 2B 2C 2D 32 33 34 35 3A 3B 3C 3D 42 43 44 45 4A 4B 4C 4D 52 53 54 55 5A 5B 5C 5D 62 63 64 65 6A 6B 6C 6D 72 73 74 75 7A 7B 7C 7D 82 83 84 85 8A 8B 8C 8D 92 93 94 95 9A 9B 9C 9D A2 A3 A4 A5 AA AB AC AD B2 B3 B4 B5 BA BB BC BD C2 C3 C4 C5 CA CB CC CD D2 D3 D4 D5 DA DB DC DD E2 E3 E4 E5 EA EB EC ED F2 F3 F4 F5 FA FB FC FD ESI 6 110 06 0E 16 1E 26 2E 36 3E 46 4E 56 5E 66 6E 76 7E 86 8E 96 9E A6 AE B6 BE C6 CE D6 DE E6 EE F6 FE EDI 7 111 07 0F 17 1F 27 2F 37 3F 47 4F 57 5F 67 6F 77 7F 87 8F 97 9F A7 AF B7 BF C7 CF D7 DF E7 EF F7 FF

32-Bit Addressing Forms with the SIB Byte:

rd(/r) Base = Base = Scaled Index [EAX] [ECX] [EDX] [EBX] none [EBP] [ESI] [EDI] [EAX*2] [ECX*2] [EDX*2] [EBX*2] none [EBP*2] [ESI*2] [EDI*2] [EAX*4] [ECX*4] [EDX*4] [EBX*4] none [EBP*4] [ESI*4] [EDI*4] [EAX*8] [ECX*8] [EDX*8] [EBX*8] none [EBP*8] [ESI*8] [EDI*8]

01

10

11

Notes:

1. The [*] nomenclature means a disp32 with no base if MOD is 00, [EBP] otherwise. This provides the following address modes: disp32[index] (MOD = 00). disp8[EBP][index] (MOD = 01). disp32[EBP][index] (MOD = 10).

ASCII Character Chart (rows 4-5 map to rows 0-1 using Ctrl + [letter/symbol]); read row then column:
0 1 2 3 4 5 6 7 0 NUL DLE SPC 0 @ P ` P 1 SOH DC1 ! 1 A Q A Q 2 STX DC2 2 B R b r 3 ETX DC3 # 3 C S c s 4 EOT DC4 $ 4 D T d t 5 ENQ NAK % 5 E U e u 6 ACK SYN & 6 F V f v 7 BEL ETB 7 G W g w 8 BS CAN ( 8 H X h x 9 HT EM ) 9 I Y i y A LF SUB * : J Z j z B VT ESC , ; K [ k { C FF FS + < L \ l | D CR GS = M ] m } E SO RS . > N ^ n ~ F SI US / ? O _ o DEL

Physical Communications Controls: NUL: Null; CAN: Cancel line; EM: End of Medium; SUB: Substitute; DEL: Delete Logical Communications Controls: SOH: Start of Header; STX: Start Text; ETX: End Text; EOT: End of Transmission; ENQ: Enquiry ACK: Acknowledgement; DLE: Data Link Escape; NAK: Negative Acknowledgement; SYN: Synchronous Idle; ETB: End Transmission Block Physical Device Controls: BEL: Bell; DC1, DC2, DC3, DC4: No ASCII meaning, used for XON/XOFF handshake schemes. Physical Device Format Affecters: BS: Backspace; HT: Horizontal Tab; LF: Line Feed; VT: Vertical Tab; FF: Form Feed; CR: Carriage Controls for Code Extensions: SI: Shift In; SO: Shift Out; ESC: Escape Information Separators: FS: File Separator; GS: Group Separator; RS: Record Separator; US: Unit Separator

IA-32 General Exceptions and Interrupts (Vector Numbers are in hexadecimal):

Vector No. 00 01 02 03 04 05 Source Protected Mode Real Address Mode Virtual 8086 Mode DIV and IDIV instructions. Yes Yes Yes Any code or data reference. Yes Yes Yes Un-mask external interrupt. Yes Yes Yes INT 3 instruction. Yes Yes Yes INTO instruction. Yes Yes Yes BOUND instruction. Yes Yes Yes UD2 instruction (P2) or 06 Yes Yes Yes reserved opcode. Floating-point or WAIT/ 07 Yes Yes Yes FWAIT instruction Instruction that can make 08 #DFDouble Fault Yes Yes Yes exception, NMI, or INTR. 09 #MFCoprocessor Seg Overrun. Floating-Point instruction. Yes Yes Yes 0A #TSInvalid TSS Task switch or TSS access. Yes Reserved Yes Loading segment registers 0B #NPSegment Not Present Yes Reserved Yes or accessing system segs. 0C #SSStack Segment Fault Stack ops & SS reg loads. Yes Yes Yes Any memery reference & 0D #GPGeneral Protection* Yes Yes Yes other protection checks. 0E #PFPage Fault Any memory reference. Yes Reserved Yes 0F (Intel Reserved. Dont use.) 10 #MFFloating-Point Error FP or (F)WAIT instruction. Yes Yes Yes 11 #ACAlignment Check Any data reference in mem. Yes Reserved Yes Model dependent machine 12 #MCMachine Check Yes Yes Yes check errors. 13 #XFSIMD FP Numeric Error SSE(2) FP instructions. Yes Yes Yes 14-1F (Intel Reserved. Dont use.) 20-FF Maskable Interrupts External, INTR or INT n. Name #DEDivide Error #DBDebug NMI Interrupt #BPBreakpoint #OFOverflow #BRBOUND Range Exceeded. #UDInvalid Opcode (undefined Opcode) #NMDevice Not Available (No Math Coprocessor)

Note:
* In real-address mode, vector 0D is the segment-overrun exception.

SIMD & x87 FPU Floating-Point Exceptions (#IS & #IA are invalids for x87):
Mnemonic Name #I Floating-point invalid operation: Source Invalid arithmetic operation or source operand

Encoding Sreg2 Field:

#IS #IA #Z #D #O #U #P

Stack overflow or underflow Invalid arithmetic operation Floating-point divide-by-zero Floating-point denormal operand Floating-point numeric overflow Floating-point numeric underflow Floating-point inexact result

x87 FPU stack overflow or underflow Invalid FPU arithmetic operation Divide-by-zero Source operand that is a denormal number Overflow in result Underflow in result Inexact result (precision)

Sreg2 Field* 00 01 10 11

Segment register Selected ES CS SS DS

Note:
* Do not use reserved encodings.

Note: * Used only with Push/Pop. Register Encoding Chart:

Reg No.* 0 1 2 3 4 5 6 7 +rb AL CL DL BL AH CH DH BH +rw AX CX DX BX SP BP SI DI +rd EAX ECX EDX EBX ESP EBP ESI EDI

Segment Register (sreg3) & Special-Purpose Register (eee) Encodings:

Sreg3 Field/eee 000 001 010 011 100 101 110 111 Segment Register Selected ES CS SS DS FS GS Reserved* Reserved* Control Register CR0 Reserved* CR2 CR3 CR4 Reserved* Reserved* Reserved* Debug Register DR0 DR1 DR2 DR3 Reserved* Reserved* DR6 DR7

Note:
* Do not use reserved encodings.

Note:
* Add to the instructions opcode.

EFLAGS (Program Status & Control) Register:

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I V V I A V R N O O D I T S Z A P C 0 0 0 0 0 0 0 0 0 0 I I 0 0 0 1 D C M F T P F F F F F F F F F P F L S CF: Cary Flag; S PF: Parity Flag; S AF: Auxiliary Carry Flag; S ZF: Zero Flag; S SF: Sign Flag; X TF: Trap Flag; X IF: Interrupt Enable Flag; X DF: Direction Flag; X OF: Overflow Flag; X IOPL: I/O Privilege Level; X NT: Nested Task; X RF: Resume Flag; X VM: Virtual-8086 Mode; X AC: Alignment Check; X VIF: Virtual Interrupt Flag; X VIP: Virtual Interrupt Pending; X ID: ID Flag Reserved bit positions. DO NOT USE. Note: S Indicates a Status Flag; C Indicates a Control Flag; X Indicates a System Flag

x87 FPU Status Word Register:

15 14 13 11 10 9 8 7 6 5 4 3 2 1 0 C C C C E S P U O Z D I B TOP 3 2 1 0 S F E E E E E E IE: Invalid Operation; DE: Denormalized Operand; ZE: Zero Divide; OE: Overflow; UE: Underflow; PE: Exception Flags Precision; SF: Stack Fault; ES: Error Summary Status; C0-C3: Condition Code; TOP: Top of Stack Pointer; B: FPU Busy

x87 FPU Control Word Register:

15 5 4 3 2 1 0 P U O Z D I X RC PC M M M M M M IM: Invalid Operand; DM: Denormal Operand; ZM: Zero Divide; OM: Overflow; UM: Underflow; PM: Precision; PC: Precision Control; RC: Rounding Control; X: Infinity Control Reserved bit positions. DO NOT USE. 14 13 12 11 10 9 8 7 6

General-Purpose Registers:
31 16 15 AH BH CH DH BP SI DI SP AL BL CL DL 0 16-bit AX BX CX DX 32-bit EAX EBX ECX EDX EBP ESI EDI ESP

Segment Registers (Segmented Model):

15 CS (Code Segment) DS (Data Segment) SS (Stack Segment) ES (Data Segment) FS (Data Segment) GS (Data Segment) 0

Fundamental Data Types:

Data Bits 127 32 31 16 15 8 7 0 Byte Word H L Double Word High Low Quad Word High Low DQword High Qword Low Qword Note: The highest bit is sign-bit for signed data types, indicating if the number is negative (1) or positive (0). 64 63

Instruction Pointer:
31 16 15 0 16-bit 32-bit IP EIP

Effective Address (Offset) Computation:

Base Index Scale Displacement EAX EAX 1 None EBX EBX ECX ECX 2 8-bit EDX + + EDX * ESP EBP 4 16-bit EBP ESI ESI EDI 8 32-bit EDI Note: Offset = Base + (Index * Scale) + Displacement

Effective Operand- and Address-Size Attributes:

D Flag in Code Segment Descriptor (1 for 32-bit) Operand-Size Prefix 66H Address-Size Prefix 67H Effective Operand Size Effective Address Size 0 N N 16 16 0 N Y 16 32 0 Y N 32 16 0 Y Y 32 32 1 N N 32 32 1 N Y 32 16 1 Y N 16 32 1 Y Y 16 16

Boolean Logic Truth Tables (AND NOT: row 1st operand, column 2nd operand):
AND 0 0 0 1 0 1 0 1 OR 0 0 0 1 1 1 1 1 XOR 0 1 0 0 1 1 1 0 NOT 0 1 1 0 AND NOT 0 1 0 0 0 1 1 0

Data Structure: Byte Offset

31 24 23 16 15
Highest

0 4 Byte 3 Byte 2 Byte 1 Byte 0 0

8 7

Encoding of Operation Direction (d) Bit:

d 0 1 Destination Source ModR/M or SIB Byte reg Field reg Field ModR/M or SIB Byte

Encoding of Operand Size (w) Bit:

w 0 1 Operand Size with 16-bit Attribute 8 Bits 16 Bits Operand Size with 32-bit Attribute 8 Bits 32 Bits

Encoding of Sign-Extend (s) Bit:

s 0 1 Effect on 8-Bit Immediate Data None Sign-extend to fill 16-bit or 32-bit destination Effect on 16- or 32-Bit Immediate Data None None

Encoding of Granularity (gg):

gg 0 0 0 1 Data Size P Bytes P Words gg 10 11 Data Size P Dwords Quadword

Encoding of Conditional Test (tttn) Field:

tttn 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AAA AAD AAM AAS ADC Mnemonic O NO B, NAE NB, AE E, Z NE, NZ BE, NA NBE, A S NS P, PE NP, PO L, NGE NL, GE LE, NG NLE, G Condition Overflow No Overflow Below, Not Above or Equal Not Below, Above or Equal Equal, Zero Not Equal, Not Zero Below or Equal, Not Above Not Below or Equal, Above Sign Not Sign Parity, Parity Even Not Parity, Parity Odd Less than, Not Greater than or Equal to Not Less than, Greater than or Equal to Less than or Equal to, Not Greater than Not Less than or Equal to, Greater than

Stack Structure:
Stack Segment Bottom of Stack (Initial ESP Value) Frame Boundary Local Variables for Calling Procedure Parameters Passed to Called Procedure Frame Boundary Return Instruction Pointer (EBP points to this) ESP points to TOS (SS Offset of Base) Top of Stack Push TOS Lower Pop TOS Higher mem, i reg1, reg2 mem, reg reg, i mem, i

Stack on Near & Far Calls/Returns:

Stack During Near Call Parameter 1 Parameter 2 (ESP Before) Frame Before Frame After Calling EIP (ESP After) Stack During Near Return (ESP After) Parameter 1 Parameter 2 Calling EIP (ESP Before) Stack During Far Call Parameter 1 Parameter 2 (ESP Before) Frame Before Frame After Calling CS Calling EIP (ESP After) Stack During Far Ret (ESP After) Parameter 1 Parameter 2 Calling CS Calling EIP (ESP Before)

0011 0111 1101 0101 : 0000 1010 1101 0100 : 0000 1010 0011 1111 reg1 to reg2 0001 000w : 11 reg1 reg2

BTS

0000 1111 : 1011 1010 : mod 110 r/m : ib 0000 1111 : 1011 0011 : 11 reg2 reg1 0000 1111 : 1011 0011 : mod reg r/m 0000 1111 : 1011 1010 : 11 101 reg : ib 0000 1111 : 1011 1010 : mod 101 r/m : ib

reg2 to reg1 0001 001w : 11 reg1 reg2 mem to reg 0001 001w : mod reg r/m reg to mem 0001 000w : mod reg r/m i to reg 1000 00sw : 11 010 reg : i i to AL/AX/EAX 0001 010w : i i to mem 1000 00sw : mod 010 r/m : i ADD reg1 to reg2 0000 000w : 11 reg1 reg2 reg2 to reg1 0000 001w : 11 reg1 reg2 mem to reg 0000 001w : mod reg r/m reg to mem 0000 000w : mod reg r/m i to reg 1000 00sw : 11 000 reg : i i to AL/AX/EAX 0000 010w : i i to mem 1000 00sw : mod 000 r/m : i AND reg1 to reg2 0010 000w : 11 reg1 reg2 reg2 to reg1 0010 001w : 11 reg1 reg2 mem to reg 0010 001w : mod reg r/m reg to mem 0010 000w : mod reg r/m i to reg 1000 00sw : 11 000 reg : i i to AL/AX/EAX 0010 010w : i i to mem 1000 00sw : mod 100 r/m : i ARPL from reg 0110 0011 : 11 reg1 reg2 from mem 0110 0011 : mod reg r/m BOUND 0110 0010 : mod reg r/m BSF reg1, reg2 0000 1111 : 1011 1100 : 11 reg2 reg1 mem, reg 0000 1111 : 1011 1100 : mod reg r/m BSR reg1, reg2 0000 1111 : 1011 1101 : 11 reg2 reg1 mem, reg 0000 1111 : 1011 1101 : mod reg r/m BSWAP 0000 1111 : 1100 1 reg BT reg, i 0000 1111 : 1011 1010 : 11 100 reg : ib mem, i 0000 1111 : 1011 1010 : mod 100 r/m : ib reg1, reg2 0000 1111 : 1010 0011 : 11 reg2 reg1 mem, reg 0000 1111 : 1010 0011 : mod reg r/m BTC reg, i 0000 1111 : 1011 1010 : 11 111 reg : ib mem, i 0000 1111 : 1011 1010 : mod 111 r/m : ib reg1, reg2 0000 1111 : 1011 1011 : 11 reg2 reg1 mem, reg 0000 1111 : 1011 1011 : mod reg r/m BTR reg, i 0000 1111 : 1011 1010 : 11 110 reg : ib IDIV AL/AX/EAX by reg 1111 011w : 11 111 reg AL/AX/EAX by mem 1111 011w : mod 111 r/m IMUL AL/AX/EAX with reg 1111 011w : 11 101 reg AL/AX/EAX with mem 1111 011w : mod 101 reg reg1 with reg2 0000 1111 : 1010 1111 : 11 : reg1 reg2 reg with mem 0000 1111 : 1010 1111 : mod reg r/m reg1 with i to reg2 0110 10s1 : 11 reg1 reg2 : i mem with i to reg 0110 10s1 : mod reg r/m : i IN fixed port 1110 010w : port number variable port 1110 110w INC reg 1111 111w : 11 000 reg reg (alt. encoding) 0100 0 reg mem 1111 111w : mod 000 r/m INS 0110 110w INT ib 1100 1101 : ib INT 3 1100 1100 INTO 1100 1110 INVD 0000 1111 : 0000 1000 INVLPG 0000 1111 : 0000 0001 : mod 111 r/m IRET/IRETD 1100 1111 Jcc 8-bit displacement 0111 tttn : 8 bit disp full displacement 0000 1111 : 1000 tttn : full disp JCXZ/JECXZ 1110 0011 : 8-bit disp JMP short 1110 1011 : 8-bit disp direct 1110 1001 : full disp

reg1, reg2 0000 1111 : 1010 1011 : 11 reg2 reg1 mem, reg 0000 1111 : 1010 1011 : mod reg r/m CALL direct 1110 1000 : full displacement reg indirect 1111 1111 : 11 010 reg mem indirect 1111 1111 : mod 010 r/m CBW 1001 1000 CDQ 1001 1001 CLC 1111 1000 CLD 1111 1100 CLI 1111 1010 CLTS 0000 1111 : 0000 0110 CMC 1111 0101 CMOVcc reg2 to reg1 0000 1111 : 0100 tttn : 11 reg1 reg2 mem to reg 0000 1111 : 0100 tttn : mod mem r/m CMP reg1 with reg2 0011 100w : 11 reg1 reg2 reg2 with reg1 0011 101w : 11 reg1 reg2 mem with reg 0011 100w : mod reg r/m reg with mem 0011 101w : mod reg r/m i with reg 1000 00sw : 11 111 reg : i i with AL/AX/EAX 0011 110w : i i with mem 1000 00sw : mod 111 r/m CMPS/CMPSB/CMPSW/CMPSD 1010 011w CMPXCHG reg1, reg2 0000 1111 : 1011 000w : 11 reg2 reg1 mem, reg 0000 1111 : 1011 000w : mod reg r/m CMPXCHG8B mem, reg 0000 1111 : 1100 0111 : mod reg r/m CPUID 0000 1111 : 1010 0010 CWD 1001 1001 CWDE 1001 1000 DAA 0010 0111 DAS 0010 1111 DEC reg 1111 111w : 11 001 reg reg (alt. encoding) 0100 1 reg mem 1111 111w : mod 001 r/m DIV AL/AX/EAX by reg 1111 011w : 11 110 reg AL/AX/EAX by mem 1111 011w : mod 110 r/m ENTER 1100 1000 : 16-bit disp : 8-bit level HLT 1111 0100 AL/AX/EAX to mem 1010 001w : full disp MOV reg to CR0 0000 1111 : 0010 0010 : 11 000 reg reg to CR2 0000 1111 : 0010 0010 : 11 010 reg reg to CR3 0000 1111 : 0010 0010 : 11 011 reg reg to CR4 0000 1111 : 0010 0010 : 11 100 reg CR0-CR4 to reg 0000 1111 : 0010 0000 : 11 eee reg MOV reg to DR0-DR3 0000 1111 : 0010 0011 : 11 eee reg reg to DR4-DR5 0000 1111 : 0010 0011 : 11 eee reg reg to DR6-DR7 0000 1111 : 0010 0011 : 11 eee reg DR6-DR7 to reg 0000 1111 : 0010 0001 : 11 eee reg DR4-DR5 to reg 0000 1111 : 0010 0001 : 11 eee reg DR0-DR3 to reg 0000 1111 : 0010 0001 : 11 eee reg MOV reg to sreg 1000 1110 : 11 sreg3 reg reg to SS 1000 1110 : 11 sreg3 reg mem to sreg 1000 1110 : mod sreg3 r/m mem to SS 1000 1110 : mod sreg3 r/m sreg to reg 1000 1100 : 11 sreg3 reg sreg to mem 1000 1100 : mod sreg3 r/m MOVS/MOVSB/MOVSW/MOVSD 1010 010w MOVSX reg2 to reg1 0000 1111 : 1011 111w : 11 reg1 reg2 mem to reg 0000 1111 : 1011 111w : mod reg r/m MOVZX reg2 to reg1 0000 1111 : 1011 011w : 11 reg1 reg2 mem to reg 0000 1111 : 1011 011w : mod reg r/m MUL AL/AX/EAX with reg 1111 011w : 11 100 reg AL/AX/EAX with mem 1111 011w : mod 100 reg

reg indirect 1111 1111 : 11 100 reg mem indirect 1111 1111 : mod 100 r/m JMP direct intersegment 1110 1010 : unS full offset, selector indirect intersegment 1111 1111 : mod 101 r/m LAHF 1001 1111 LAR from reg 0000 1111 : 0000 0010 : 11 reg1 reg2 from mem 0000 1111 : 0000 0010 : mod reg r/m LDS 1100 0101 : mod reg r/m LEA 1000 1101 : mod reg r/m LEAVE 1100 1001 LES 1100 0100 : mod reg r/m LFS 0000 1111 : 1011 0100 : mod reg r/m LGDT 0000 1111 : 0000 0001 : mod 010 r/m LGS 0000 1111 : 1011 0101 : mod reg r/m LIDT 0000 1111 : 0000 0001 : mod 011 r/m LLDT LDTR from reg 0000 1111 : 0000 0000 : 11 010 reg LDTR from mem 0000 1111 : 0000 0000 : mod 010 r/m LMSW from reg 0000 1111 : 0000 0001 : 11 110 reg from mem 0000 1111 : 0000 0001 : mod 110 r/m LOCK 1111 0000 LODS/LODSB/LODSW/LODSD 1010 110w LOOP 1110 0010 : 8-bit disp LOOPZ/LOOPE 1110 0001 : 8-bit disp LOOPNZ/LOOPNE 1110 0000 : 8-bit disp LSL from reg 0000 1111 : 0000 0011 : 11 reg1 reg2 from mem 0000 1111 : 0000 0011 : mod reg r/m LSS 0000 1111 : 1011 0010 : mod reg r/m LTR from reg 0000 1111 : 0000 0000 : 11 011 reg from mem 0000 1111 : 0000 0000 : mod 011 r/m MOV reg1 to reg2 1000 100w : 11 reg1 reg2 reg2 to reg1 1000 101w : 11 reg1 reg2 mem to reg 1000 101w : mod reg r/m reg to mem 1000 100w : mod reg r/m i to reg 1100 011w : 11 000 reg : i i to reg (alt. encoding) 1011 w reg : i i to mem 1100 011w : mod 000 r/m : i mem to AL/AX/EAX 1010 000w : full disp RCR reg by 1 1101 000w : 11 011 reg mem by 1 1101 000w : mod 011 r/m reg by CL 1101 001w : 11 011 reg mem by CL 1101 001w : mod 011 r/m reg by i 1100 000w : 11 011 reg : ib mem by i 1100 000w : mod 011 r/m : ib RDMSR 000 1111 : 0011 0010 RDPMC 0000 1111 : 0011 0011 RDTSC 0000 1111 : 0011 0001 REP INS 1111 0011 : 0110 110w REP LODS 1111 0011 : 1010 110w REP MOVS 1111 0011 : 1010 010w REP OUTS 1111 0011 : 0110 111w REP STOS 1111 0011 : 1010 101w REP CMPS 1111 0011 : 1010 011w REPE SCAS 1111 0011 : 1010 111w REPNE CMPS 1111 0010 : 1010 011w REPNE SCAS 1111 0010 : 1010 111w RET (same) no argument 1100 0011 adding i to SP 1100 0010 : 16-bit disp RET (other) intersegment 1100 1011 adding i to SP 1100 1010 : 16-bit disp ROL reg by 1 1101 000w : 11 000 reg mem by 1 1101 000w : mod 000 r/m reg by CL 1101 001w : 11 000 reg

NEG

1111 011w : 11 011 reg 1111 011w : mod 011 r/m NOP 1001 0000 NOT reg 1111 011w : 11 010 reg mem 1111 011w : mod 010 r/m OR reg1 to reg2 0000 100w : 11 reg1 reg2 reg2 to reg1 0000 101w : 11 reg1 reg2 mem to reg 0000 101w : mod reg r/m reg to mem 0000 100w : mod reg r/m i to reg 1000 00sw : 11 001 reg : i i to AL/AX/EAX 0000 110w : i i to mem 1000 00sw : mod 001 r/m : i OUT fixed port 1110 011w : port number variable port 1110 111w OUTS 0110 111w POP reg 1000 1111 : 11 000 reg reg (alt. encoding) 0101 1 reg mem 1000 1111 : mod 000 r/m POP sreg CS, DS, or ES 000 sreg2 111 sreg SS 000 sreg2 111 sreg FS or GS 0000 1111 : 10 sreg3 001 POPA/POPAD 0110 0001 POPF/POPFD 1001 1101 PUSH reg 1111 1111 : 11 110 reg reg (alt. encoding) 0101 0 reg mem 1111 1111 : mod 110 r/m i 0110 10s0 : i PUSH sreg CS/DS/ES/SS 000 sreg2 110 sreg FS or GS 0000 1111 : 10 sreg3 000 PUSHA/PUSHAD 0110 0000 PUSHF/PUSHFD 1001 1100 RCL reg by 1 1101 000w : 11 010 reg mem by 1 1101 000w : mod 010 r/m reg by CL 1101 001w : 11 010 reg mem by CL 1101 001w : mod 010 r/m reg by i 1100 000w : 11 010 reg : ib mem by i 1100 000w : mod 010 r/m :ib reg by CL 0000 1111 : 1010 0101 : 11 reg2 reg1 mem by CL 0000 1111 : 1010 0101 : mod reg r/m SHR reg by 1 1101 000w : 11 101 reg mem by 1 1101 000w : mod 101 r/m reg by CL 1101 001w : 11 101 reg mem by CL 1101 001w : mod 101 r/m reg by i 1100 000w : 11 101 reg :i8 mem by i 1100 000w : mod 101 r/m :i8 SHRD reg by i 0000 1111 : 1010 1100 : 11 reg2 reg1 : ib mem by i 0000 1111 : 1010 1100 : mod reg r/m : ib reg by CL 0000 1111 : 1010 1101 : 11 reg2 reg1 mem by CL 0000 1111 : 1010 1101 : mod reg r/m SIDT 0000 1111 : 0000 0001 : mod 001 r/m SLDT to reg 0000 1111 : 0000 0000 : 11 000 reg to mem 0000 1111 : 0000 0000 : mod 000 r/m SMSW to reg 0000 1111 : 0000 0001 : 11 100 reg to mem 0000 1111 : 0000 0001 : mod 100 r/m STC 1111 1001 STD 1111 1101 STI 1111 1011 STOS/STOSB/STOSW/STOSD 1010 101w STR to reg 0000 1111 : 0000 0000 : 11 001 reg to mem 0000 1111 : 0000 0000 : mod 001 r/m SUB reg1 to reg2 0010 100w : 11 reg1 reg2 reg2 to reg1 0010 101w : 11 reg1 reg2

reg mem

1101 001w : mod 000 r/m 1100 000w : 11 000 reg : ib 1100 000w : mod 000 r/m : ib ROR 1101 000w : 11 001 reg 1101 000w : mod 001 r/m 1101 001w : 11 001 reg 1101 001w : mod 001 r/m 1100 000w : 11 001 reg : ib 1100 000w : mod 001 r/m : ib RSM 0000 1111 : 1010 1010 SAHF 1001 1110 SAL same instruction as SHL SAR reg by 1 1101 000w : 11 111 reg mem by 1 1101 000w : mod 111 r/m reg by CL 1101 001w : 11 111 reg mem by CL 1101 001w : mod 111 r/m reg by i 1100 000w : 11 111 reg : ib mem by i 1100 000w : mod 111 r/m : ib SBB reg1 to reg2 0001 100w : 11 reg1 reg2 reg2 to reg1 0001 101w : 11 reg1 reg2 mem to reg 0001 101w : mod reg r/m reg to mem 0001 100w : mod reg r/m i to reg 1000 00sw : 11 011 reg : i i to AL/AX/EAX 0001 110w : i i to mem 1000 00sw : mod 011 r/m : i SCAS/SCASB/SCASW/SCASD 1101 111w SETcc reg 0000 1111 : 1001 tttn : 11 000 reg mem 0000 1111 : 1001 tttn : mod 000 r/m SGDT 0000 1111 : 0000 0001 : mod 000 r/m SHL reg by 1 1101 000w : 11 100 reg mem by 1 1101 000w : mod 100 r/m reg by CL 1101 001w : 11 100 reg mem by CL 1101 001w : mod 100 r/m reg by i 1100 000w : 11 100 reg : ib mem by i 1100 000w : mod 100 r/m : ib SHLD reg by i 0000 1111 : 1010 0100 : 11 reg2 reg1 : ib mem by i 0000 1111 : 1010 0100 : mod reg r/m : ib FS segment override 0110 0100 GS segment override 0110 0101 SS segment override 0011 0110 EMMS 0000 1111 : 0111 0111 MOVD reg to mm 0000 1111 : 0110 1110 : 11 mm reg mm to reg 0000 1111 : 0111 1110 : 11 mm reg mem to mm 0000 1111 : 0110 1110 : mod mm r/m mm to mem 0000 1111 : 0111 1110 : mod mm r/m MOVQ mm2 to mm1 0000 1111 : 0110 1111 : 11 mm1 mm2 mm1 to mm2 0000 1111 : 0111 1111 : 11 mm1 mm2 mem to mm 0000 1111 : 0110 1111 : mod mm r/m mm to mem 0000 1111 : 0111 1111 : mod mm r/m PACKSSDW mm2 to mm1 0000 1111 : 0110 1011 : 11 mm1 mm2 mem to mm 0000 1111 : 0110 1011 : mod mm r/m PACKSSWB mm2 to mm1 0000 1111 : 0110 0011 : 11 mm1 mm2 mem to mm 0000 1111 : 0110 0011 : mod mm r/m PACKUSWB mm2 to mm1 0000 1111 : 0110 0111 : 11 mm1 mm2 mem to mm 0000 1111 : 0110 0111 : mod mm r/m PADD mm2 to mm1 0000 1111 : 1111 11gg : 11 mm1 mm2 mem to mm 0000 1111 : 1111 11gg : mod mm r/m PADDS mm2 to mm1 0000 1111 : 1110 11gg : 11 mm1 mm2 mem to mm 0000 1111 : 1110 11gg : mod mm r/m PADDUS mm2 to mm1 0000 1111 : 1101 11gg : 11 mm1 mm2 mem to mm 0000 1111 : 1101 11gg : mod mm r/m PAND mm2 to mm1 0000 1111 : 1101 1011 : 11 mm1 mm2

mem by CL reg by i mem by i reg by 1 mem by 1 reg by CL mem by CL reg by i mem by i

mem to reg 0010 101w : mod reg r/m reg to mem 0010 100w : mod reg r/m i to reg 1000 00sw : 11 101 reg : i i to AL/AX/EAX 0010 110w : i i to mem 1000 00sw : mod 101 r/m : i TEST reg1 and reg2 1000 010w : 11 reg1 reg2 mem and reg 1000 010w : mod reg r/m i and reg 1111 011w : 11 000 reg : i i and AL/AX/EAX 1010 100w : i i and mem 1111 011w : mod 000 r/m : i UD2 0000 1111 : 0000 1011 VERR reg 0000 1111 : 0000 0000 : 11 100 reg mem 0000 1111 : 0000 0000 : mod 100 r/m VERW reg 0000 1111 : 0000 0000 : 11 101 reg mem 0000 1111 : 0000 0000 : mod 101 r/m WAIT 1001 1011 WBINVD 0000 1111 : 0000 1001 WRMSR 0000 1111 : 0011 0000 XADD reg1, reg2 0000 1111 : 1100 000w : 11 reg2 reg1 mem, reg 0000 1111 : 1100 000w : mod reg r/m XCHG reg1 with reg2 1000 011w : 11 reg1 reg2 AL/AX/EAX with reg 1001 0 reg mem with reg 1000 011w : mod reg r/m XLAT/XLATB 1101 0111 XOR reg1 to reg2 0011 000w : 11 reg1 reg2 reg2 to reg1 0011 001w : 11 reg1 reg2 mem to reg 0011 001w : mod reg r/m reg to mem 0011 000w : mod reg r/m i to reg 1000 00sw : 11 110 reg : i i to AL/AX/EAX 0011 010w : i i to mem 1000 00sw : mod 110 r/m : i Prefix Bytes address size 0110 0111 LOCK 1111 0000 operand size 0110 0110 CS segment override 0010 1110 DS segment override 0011 1110 ES segment override 0010 0110 FXSAVE 0000 1111 : 1010 1110 : 00 m512 SYSENTER 0000 1111 : 0101 1111 : 11 SYSEXIT 0000 1111 : 0101 1111 : 11 ADDPS xm to xm 0000 1111 : 0101 1000 : 11 xm1 xm2 mem to xm 0000 1111 : 0101 1000 : mod xm r/m
ADDSS xm to xm 1111 0011 : 0000 1111 : 0101 1000 : 11 xm1 xm2 mem to xm 1111 0011 : 0000 1111 : 0101 1000 : mod xm r/m

ANDNPS

xm to xm 0000 1111 : 0101 0101 : 11 xm1 xm2 mem to xm 0000 1111 : 0101 0101 : mod xm r/m ANDPS xm to xm 0000 1111 : 0101 0100 : 11 xm1 xm2 mem to xm 0000 1111 : 0101 0100 : mod xm r/m CMPPS xm to xm, i8 0000 1111 : 1100 0010 : 11 xm1 xm2 : i8 mem to xm, i8 0000 1111 : 1100 0010 : mod xm r/m : i8 CMPSS xm to xm, i8 1111 0011 : 0000 1111 : 1100 0010 : 11 xm1 xm2 : i8
mem to xm, i8 1111 0011 : 0000 1111 : 1100 0010 : mod xm r/m : i8

COMISS CVTPI2PS CVTPS2PI CVTSI2SS CVTSS2SI

xm to xm 0000 1111 : 0010 1111 : 11 xm1 xm2 mem to xm 0000 1111 : 0010 1111 : mod xm r/m mm to xm 0000 1111 : 0010 1010 : 11 xm1 mm1 mem to xm 0000 1111 : 0010 1010 : mod xm r/m xm to mm 0000 1111 : 0010 1101 : 11 mm1 xm1 mem to mm 0000 1111 : 0010 1101 : mod mm r/m rd to xm1 1111 0011 : 0000 1111 : 0010 1010 : 11 xm rd mem to xm 1111 0011 : 0000 1111 : 0010 1010 : mod xm r/m xm to rd 1111 0011 : 0000 1111 : 0010 1101 : 11 rd xm mem to rd 1111 0011 : 0000 1111 : 0010 1101 : mod rd r/m

mem to mm 0000 1111 : 1101 1011 : mod mm r/m PANDN mm2 to mm1 0000 1111 : 1101 1111 : 11 mm1 mm2 mem to mm 0000 1111 : 1101 1111 : mod mm r/m PCMPEQ mm1 with mm2 0000 1111 : 0111 01gg : 11 mm1 mm2 mm with mem 0000 1111 : 0111 01gg : mod mm r/m PCMPGT mm1 with mm2 0000 1111 : 0110 01gg : 11 mm1 mm2 mm with mem 0000 1111 : 0110 01gg : mod mm r/m PMADD mm2 to mm1 0000 1111 : 1111 0101 : 11 mm1 mm2 mem to mm 0000 1111 : 1111 0101 : mod mm r/m PMULH mm2 to mm1 0000 1111 : 1110 0101 : 11 mm1 mm2 mem to mm 0000 1111 : 1110 0101 : mod mm r/m PMULL mm2 to mm1 0000 1111 : 1101 0101 : 11 mm1 mm2 mem to mm 0000 1111 : 1101 0101 : mod mm r/m POR mm2 to mm1 0000 1111 : 1110 1011 : 11 mm1 mm2 mem to mm 0000 1111 : 1110 1011 : mod mm r/m PSLL mm1 by mm2 0000 1111 : 1111 00gg : 11 mm1 mm2 mm by mem 0000 1111 : 1111 00gg : mod mm r/m mm by i 0000 1111 : 0111 00gg : 11 110 mm : i8 PSRA mm1 by mm2 0000 1111 : 1110 00gg : 11 mm1 mm2 mm by mem 0000 1111 : 1110 00gg : mod mm r/m mm by i 0000 1111 : 0111 00gg : 11 100 mm : i8 PSRL mm1 by mm2 0000 1111 : 1101 00gg : 11 mm1 mm2 mm by mem 0000 1111 : 1101 00gg : mod mm r/m mm by i 0000 1111 : 0111 00gg : 11 010 mm : i8 PSUB mm1 to mm2 0000 1111 : 1111 10gg : 11 mm1 mm2 mm to mem 0000 1111 : 1111 10gg : mod mm r/m PSUBS mm1 to mm2 0000 1111 : 1110 10gg : 11 mm1 mm2 mm to mem 0000 1111 : 1110 10gg : mod mm r/m PSUBUS mm1 to mm2 0000 1111 : 1101 10gg : 11 mm1 mm2 mm to mem 0000 1111 : 1101 10gg : mod mm r/m PUNPCKH mm2 to mm1 0000 1111 : 0110 10gg : 11 mm1 mm2 mem to mm 0000 1111 : 0110 10gg : mod mm r/m PUNPCKL mm2 to mm1 0000 1111 : 0110 00gg : 11 mm1 mm2 mem to mm 0000 1111 : 0110 00gg : mod mm r/m PXOR mm2 to mm1 0000 1111 : 1110 1111 : 11 mm1 mm2 mem to mm 0000 1111 : 1110 1111 : mod mm r/m FXRSTOR 0000 1111 : 1010 1110 : 01 m512 MULSS xm to xm 1111 0011 : 0000 1111 : 0101 1001 : 11 xm1 xm2 mem to xm 1111 0011 : 0000 1111 : 0101 1001 : mod xm r/m ORPS xm to xm 0000 1111 : 0101 0110 : 11 xm1 xm2 mem to xm 0000 1111 : 0101 0110 : mod xm r/m RCPPS xm to xm 0000 1111 : 0101 0011 : 11 xm1 xm2 mem to xm 0000 1111 : 0101 0011 : mod xm r/m RCPSS xm to xm 1111 0011 : 0000 1111 : 0101 0011 : 11 xm1 xm2 mem to xm 1111 0011 : 0000 1111 : 0101 0011 : mod xm r/m RSQRTPS xm to xm 0000 1111 : 0101 0010 : 11 xm1 xm2 mem to xm 0000 1111 : 0101 0010 : mod xm r/m RSQRTSS xm to xm 1111 0011 : 0000 1111 : 0101 0010 : 11 xm1 xm2 mem to xm 1111 0011 : 0000 1111 : 0101 0010 : mod xm r/m SHUFPS xm to xm, i8 0000 1111 : 1100 0110 : 11 xm1 xm2 : i8
mem to xm, i8 0000 1111 : 1100 0110 : mod xm r/m : i8

CVTTPS2PI xm to mm

mem mm
CVTTSS2SI xm to rd mem to rd

0000 1111 : 0010 1100 : 11 mm1 xm1 0000 1111 : 0010 1100 : mod mm r/m
1111 0011 : 0000 1111 : 0010 1100 : 11 rd xm1 1111 0011 : 0000 1111 : 0010 1100 : mod rd r/m

DIVPS

xm to xm 0000 1111 : 0101 1110 : 11 xm1 xm2 mem to xm 0000 1111 : 0101 1110 : mod xm r/m DIVSS xm to xm 1111 0011 : 0000 1111 : 0101 1110 : 11 xm1 xm2 mem to xm 1111 0011 : 0000 1111 : 0101 1110 : mod xm r/m LDMXCSR md to MXCSR 0000 1111 : 1010 1110 : 10 md MAXPS xm to xm 0000 1111 : 0101 1111 : 11 xm1 xm2 mem to xm 0000 1111 : 0101 1111 : mod xm r/m MAXSS xm to xm 1111 0011 : 0000 1111 : 0101 1111 : 11 xm1 xm2 mem to xm 1111 0011 : 0000 1111 : 0101 1111 : mod xm r/m MINPS xm to xm 0000 1111 : 0101 1101 : 11 xm1 xm2 mem to xm 0000 1111 : 0101 1101 : mod xm r/m MINSS xm to xm 1111 0011 : 0000 1111 : 0101 1101 : 11 xm1 xm2 mem to xm 1111 0011 : 0000 1111 : 0101 1101 : mod xm r/m MOVAPS xm2 to xm1 0000 1111 : 0010 1000 : 11 xm2 xm1 mem to xm1 0000 1111 : 0010 1000 : mod xm r/m xm1 to xm2 0000 1111 : 0010 1001 : 11 xm1 xm2 xm1 to mem 0000 1111 : 0010 1001 : mod xm r/m MOVHLPS xm to xm 0000 1111 : 0001 0010 : 11 xm1 xm2 MOVHPS mem to xm 0000 1111 : 0001 0110 : mod xm r/m xm to mem 0000 1111 : 0001 0111 : mod xm r/m MOVLHPS xm to xm 0000 1111 : 0001 0110 : 11 xm1 xm2 MOVLPS mem to xm 0000 1111 : 0001 0010 : mod xm r/m xm to mem 0000 1111 : 0001 0011 : mod xm r/m MOVMSKPS xm to rd 0000 1111 : 0101 0000 : 11 rd xm MOVSS xm2 to xm1 1111 0011 : 0000 1111 : 0001 0000 : 11 xm2 xm1 mem to xm1 1111 0011 : 0000 1111 : 0001 0000 : mod xm r/m xm1 to xm2 1111 0011 : 0000 1111 : 0001 0000 : 11 xm1 xm2 xm1 to mem 1111 0011 : 0000 1111 : 0001 0000 : mod xm r/m MOVUPS xm2 to xm1 0000 1111 : 0001 0000 : 11 xm2 xm1 mem to xm1 0000 1111 : 0001 0000 : mod xm r/m xm1 to xm2 0000 1111 : 0001 0001 : xm1 xm2 xm1 to mem 0000 1111 : 0001 0001 : mod xm r/m MULPS xm to xm 0000 1111 : 0101 1001 : 11 xm1 xm2 mem to xm 0000 1111 : 0101 1001 : mod xm r/m
mem to xm
0110 0110 : 0000 1111 : 0101 1000 : mod xm r/m

ADDSD xm to xm 1111 0010 : 0000 1111 : 0101 1000 : 11 xm1 xm2 mem to xm 1111 0010 : 0000 1111 : 0101 1000 : mod xm r/m ANDNPD xm to xm 0110 0110 : 0000 1111 : 0101 0101 : 11 xm1 xm2 mem to xm 0110 0110 : 0000 1111 : 0101 0101 : mod xm r/m ANDPD xm to xm 0110 0110 : 0000 1111 : 0101 0100 : 11 xm1 xm2 mem to xm 0110 0110 : 0000 1111 : 0101 0100 : mod xm r/m CMPPD xm to xm, ib 0110 0110 : 0000 1111 : 1100 0010 : 11 xm1 xm2 : ib
mem to xm, ib 0110 0110 : 0000 1111 : 1100 0010 : mod xm r/m : ib

CMPSD xm to xm, ib

1111 0010 : 0000 1111 : 1100 0010 : 11 xm1 xm2 : ib

SQRTPS

xm to xm 0000 1111 : 0101 0001 : 11 xm1 xm2 mem to xm 0000 1111 : 0101 0001 : mod xm r/m SQRTSS xm to xm 0101 0011 : 0000 1111 : 0101 0001 : 11 xm1 xm2 mem to xm 0101 0011 : 0000 1111 : 0101 0001 : mod xm r/m STMXCSR MXCSR to mem 0000 1111 : 1010 1110 : 11 md SUBPS xm to xm 0000 1111 : 0101 1100 : 11 xm1 xm2 mem to xm 0000 1111 : 0101 1100 : mod xm r/m SUBSS xm to xm 1111 0011 : 0000 1111 : 0101 1100 : 11 xm1 xm2 mem to xm 1111 0011 : 0000 1111 : 0101 1100 : mod xm r/m UCOMISS xm to xm 0000 1111 : 0010 1110 : 11 xm1 xm2 mem to xm 0000 1111 : 0010 1110 : mod xm r/m

mem to xm, ib 1111 0010 : 0000 1111 : 1100 0010 : mod xm r/m : ib COMISD xm to xm 0110 0110 : 0000 1111 : 0010 1111 : 11 xm1 xm2 mem to xm 0110 0110 : 0000 1111 : 0010 1111 : mod xm r/m CVTPI2PD mm to xm 0110 0110 : 0000 1111 : 0010 1010 : 11 xm1 mm1 mem to mm 0110 0110 : 0000 1111 : 0010 1010 : mod xm r/m

CVTPD2PI xm to mm CVTSI2SD rd to xm1

mem to xm

0110 0110 : 0000 1111 : 0010 1101 : 11 mm1 xm1

mem to mm 0110 0110 : 0000 1111 : 0010 1101 : mod mm r/m

1111 0010 : 0000 1111 : 0010 1010 : 11 xm rd 1111 0010 : 0000 1111 : 0010 1010 : mod xm r/m CVTSD2SI xm to rd 1111 0010 : 0000 1111 : 0010 1101 : 11 rd xm mem to rd 1111 0010 : 0000 1111 : 0010 1101 : mod rd r/m CVTTPD2PI xm to mm 0110 0110 : 0000 1111 : 0010 1100 : 11 mm xm mem to mm 0110 0110 : 0000 1111 : 0010 1100 : mod mm r/m CVTTSD2SI xm to rd 1111 0010 : 0000 1111 : 0010 1100 : 11 rd xm mem to rd 1111 0010 : 0000 1111 : 0010 1100 : mod rd r/m

UNPCKHPS xm to xm

mem to xm UNPCKLPS xm to xm mem to xm XORPS xm to xm mem to xm PAVGB mm to mm mem to mm PAVGW mm to mm mem to mm PEXTRW mm to rd, ib PINSRW rd to mm, ib
mw to mm, ib

0000 1111 : 0001 0101 : 11 xm1 xm2 0000 1111 : 0001 0101 mod xm r/m 0000 1111 : 0001 0100 : 11 xm1 xm2 0000 1111 : 0001 0100 : mod xm r/m 0000 1111 : 0101 0111 : 11 xm1 xm2 0000 1111 : 0101 0111 : mod xm r/m 0000 1111 : 1110 0000 : 11 mm1 mm2 0000 1111 : 1110 0000 : mod mm r/m 0000 1111 : 1110 0011 : 11 mm1 mm2 0000 1111 : 1110 0011 : mod mm r/m 0000 1111 : 1100 0101 : 11 rd mm : ib 0000 1111 : 1100 0100 : 11 mm rd : ib
0000 1111 : 1100 0100 : mod mm r/m : ib

CVTPD2PS xm to xm

mem to xm CVTPS2PD xm to xm mem to xm CVTSD2SS xm to xm mem to xm CVTSS2SD xm to xm

mem to xm CVTPD2DQ xm to xm mem to xm
CVTTPD2DQ

0110 0110 : 0000 1111 : 0101 1010 : 11 xm1 xm2 0110 0110 : 0000 1111 : 0101 1010 : mod xm r/m

0000 1111 : 0101 1010 : 11 xm1 xm2 0000 1111 : 0101 1010 : mod xm r/m
1111 0010 : 0000 1111 : 0101 1010 : 11 xm1 xm2 1111 0010 : 0000 1111 : 0101 1010 : mod xm r/m 1111 0011 : 0000 1111 : 0101 1010 : 11 xm1 xm2 1111 0011 : 0000 1111 : 0101 1010 : mod xm r/m 1111 0010 : 0000 1111 : 1110 0110 : 11 xm1 xm2 1111 0010 : 0000 1111 : 1110 0110 : mod xm r/m 0110 0110 : 0000 1111 : 1110 0110 : 11 xm1 xm2 0110 0110 : 0000 1111 : 1110 0110 : mod xm r/m 1111 0011 : 0000 1111 : 1110 0110 : 11 xm1 xm2 1111 0011 : 0000 1111 : 1110 0110 : mod xm r/m 0110 0110 : 0000 1111 : 0101 1011 : 11 xm1 xm2 0110 0110 : 0000 1111 : 0101 1011 : mod xm r/m 1111 0011 : 0000 1111 : 0101 1011 : 11 xm1 xm2 1111 0011 : 0000 1111 : 0101 1011 : mod xm r/m

xm to xm

PMAXSW mm to mm mem to mm PMAXUB mm to mm mem to mm PMINSW mm to mm mem to mm PMINUB mm to mm mem to mm PMOVMSKB mm to rd PMULHUW mm to mm mem to mm PSADBW mm to mm mem to mm PSHUFW mm to mm, ib
MASKMOVQ

0000 1111 : 1110 1110 : 11 mm1 mm2 0000 1111 : 1110 1110 : mod mm r/m 0000 1111 : 1101 1110 : 11 mm1 mm2 0000 1111 : 1101 1110 : mod mm r/m 0000 1111 : 1110 1010 : 11 mm1 mm2 0000 1111 : 1110 1010 : mod mm r/m 0000 1111 : 1101 1010 : 11 mm1 mm2 0000 1111 : 1101 1010 : mod mm r/m 0000 1111 : 1101 0111 : 11 mm rd 0000 1111 : 1110 0100 : 11 mm1 mm2 0000 1111 : 1110 0100 : mod mm r/m 0000 1111 : 1111 0110 : 11 mm1 mm2 0000 1111 : 1111 0110 : mod mm r/m

mem to xm CVTDQ2PD xm to xm mem to xm CVTPS2DQ xm to xm mem to xm

CVTTPS2DQ

xm to xm

mem to xm CVTDQ2PS xm to xm

0000 1111 : 0111 0000 : 11 mm1 mm2 : ib mem to mm, ib 0000 1111 : 0111 0000 : mod mm r/m : ib

mm to mm 0000 1111 : 1111 0111 : 11 mm1 mm2 MOVNTPS xm to mem 0000 1111 : 0010 1011 : mod xm r/m MOVNTQ mm to mem 0000 1111 : 1110 0111 : mod mm r/m PREFETCH0 0000 1111 : 0001 1000 : 01 mem PREFETCH1 0000 1111 : 0001 1000 : 10 mem PREFETCH2 0000 1111 : 0001 1000 : 11 mem PREFETCHNTA 0000 1111 : 0001 1000 : 00 mem SFENCE 0000 1111 : 1010 1110 : 1111 1000 ADDPD xm to xm 0110 0110 : 0000 1111 : 0101 1000 : 11 xm1 xm2 xm to mem 0110 0110 : 0000 1111 : 0001 0010 : mod xm r/m MOVMSKPD xm to rd 0110 0110 : 0000 1111 : 0101 0000 : 11 rd xm MOVSD xm2 xm1 1111 0010 : 0000 1111 : 0001 0001 : 11 xm2 xm1 mem to xm1 1111 0010 : 0000 1111 : 0001 0001 : mod xm r/m xm1 to xm2 1111 0010 : 0000 1111 : 0001 0000 : 11 xm1 xm2
1111 0010 : 0000 1111 : 0001 0000 : mod xm r/m 0110 0110 : 0000 1111 : 0001 0001 : 11 xm2 xm1 mem to xm1 0110 0110 : 0000 1111 : 0001 0001 : mod xm r/m xm1 to xm2 0110 0110 : 0000 1111 : 0001 0000 : 11 xm1 xm2 xm1 to mem 0110 0110 : 0000 1111 : 0001 0000 : mod xm r/m MULPD xm to xm 0110 0110 : 0000 1111 : 0101 1001 : 11 xm1 xm2 mem to xm 0110 0110 : 0000 1111 : 0101 1001 : mod xm r/m MULSD xm to xm 1111 0010 : 0000 1111 : 0101 1001 : 11 xm1 xm2 mem to xm 1111 0010 : 0000 1111 : 0101 1001 : mod xm r/m ORPD xm to xm 0110 0110 : 0000 1111 : 0101 0110 : 11 xm1 xm2 mem to xm 0110 0110 : 0000 1111 : 0101 0110 : mod xm r/m SHUFPD xm to xm, ib 0110 0110 : 0000 1111 : 1100 0110 : 11 xm1 xm2 : ib mem to xm, ib 0110 0110 : 0000 1111 : 1100 0110 : mod xm r/m : ib SQRTPD xm to xm 0110 0110 : 0000 1111 : 0101 0001 : 11 xm1 xm2 mem to xm 0110 0110 : 0000 1111 : 0101 0001 : mod xm r/m SQRTSD xm to xm 1111 0010 : 0000 1111 : 0101 0001 : 11 xm1 xm2 mem to xm 1111 0010 : 0000 1111 : 0101 0001 : mod xm r/m SUBPD xm to xm 0110 0110 : 0000 1111 : 0101 1100 : 11 xm1 xm2 mem to xm 0110 0110 : 0000 1111 : 0101 1100 : mod xm r/m SUBSD xm to xm 1111 0010 : 0000 1111 : 0101 1100 : 11 xm1 xm2 mem to xm 1111 0010 : 0000 1111 : 0101 1100 : mod xm r/m

mem to xm DIVPD xm to xm mem to xm DIVSD xm to xm mem to xm MAXPD xm to xm mem to xm MAXSD xm to xm mem to xm MINPD xm to xm mem to xm MINSD xm to xm mem to xm MOVAPD xm2 to xm1 mem to xm1 xm1 to xm2

0000 1111 : 0101 1011 : 11 xm1 xm2 0000 1111 : 0101 1011 : mod xm r/m

xm1 to mem

MOVUPD xm2 to xm1

0110 0110 : 0000 1111 : 0101 1110 : 11 xm1 xm2 0110 0010 : 0000 1111 : 0101 1110 : mod xm r/m 1111 0010 : 0000 1111 : 0101 1110 : 11 xm1 xm2 1111 0010 : 0000 1111 : 0101 1110 : mod xm r/m 0110 0110 : 0000 1111 : 0101 1111 : 11 xm1 xm2 0110 0110 : 0000 1111 : 0101 1111 : mod xm r/m 1111 0010 : 0000 1111 : 0101 1111 : 11 xm1 xm2 1111 0010 : 0000 1111 : 0101 1111 : mod xm r/m 0110 0110 : 0000 1111 : 0101 1101 : 11 xm1 xm2 0110 0110 : 0000 1111 : 0101 1101 : mod xm r/m 1111 0010 : 0000 1111 : 0101 1101 : 11 xm1 xm2 1111 0010 : 0000 1111 : 0101 1101 : mod xm r/m 0110 0110 : 0000 1111 : 0010 1001 : 11 xm2 xm1 0110 0110 : 0000 1111 : 0010 1001 : mod xm r/m 0110 0110 : 0000 1111 : 0010 1000 : 11 xm1 xm2 xm1 to mem 0110 0110 : 0000 1111 : 0010 1000 : mod xm r/m MOVHPD mem to xm 0110 0110 : 0000 1111 : 0001 0111 : mod xm r/m xm to mem 0110 0110 : 0000 1111 : 0001 0110 : mod xm r/m MOVLPD mem to xm 0110 0110 : 0000 1111 : 0001 0011 : mod xm r/m mem to xm 0110 0110 : 0000 1111 : 1110 11gg : mod xm r/m PADDUS xm2 to xm1 0110 0110 : 0000 1111 : 1101 11gg : 11 xm1 xm2 mem to xm 0110 0110 : 0000 1111 : 1101 11gg : mod xm r/m PAND xm2 to xm1 0110 0110 : 0000 1111 : 1101 1011 : 11 xm1 xm2 mem to xm 0110 0110 : 0000 1111 : 1101 1011 : mod xm r/m PANDN xm2 to xm1 0110 0110 : 0000 1111 : 1101 1111 : 11 xm1 xm2 mem to xm 0110 0110 : 0000 1111 : 1101 1111 : mod xm r/m PAVGB xm to xm 0110 0110 : 0000 1111 : 1110 0000 : 11 xm1 xm2 mem to xm 0110 0110 : 0000 1111 : 1110 0000 : mod xm r/m PAVGW xm to xm 0110 0110 : 0000 1111 : 1110 0011 : 11 xm1 xm2 mem to xm 0110 0110 : 0000 1111 : 1110 0011 : mod xm r/m PCMPEQ xm1 with xm2 0110 0110 : 0000 1111 : 0111 01gg : 11 xm1 xm2 xm with mem 0110 0110 : 0000 1111 : 0111 01gg : mod xm r/m PCMPGT xm1 with xm2 0110 0110 : 0000 1111 : 0110 01gg : 11 xm1 xm2 xm with mem 0110 0110 : 0000 1111 : 0110 01gg : mod xm r/m PEXTRW xm to rd, ib 0110 0110 : 0000 1111 : 1100 0101 : 11 rd xm : ib PINSRW rd to xm, ib 0110 0110 : 0000 1111 : 1100 0100 : 11 xm rd : ib mw to xm, ib 0110 0110 : 0000 1111 : 1100 0100 : mod xm r/m : ib PMADD xm2 to xm1 0110 0110 : 0000 1111 : 1111 0101 : 11 xm1 xm2 mem to xm 0110 0110 : 0000 1111 : 1111 0101 : mod xm r/m PMAXSW xm to xm 0110 0110 : 0000 1111 : 1110 1110 : 11 xm1 xm2 mem to xm 0110 0110 : 0000 1111 : 1110 1110 : mod xm r/m PMAXUB xm to xm 0110 0110 : 0000 1111 : 1101 1110 : 11 xm1 xm2 mem to xm 0110 0110 : 0000 1111 : 1101 1110 : mod xm r/m

UCOMISD xm to xm mem to xm UNPCKHPD xm to xm

mem to xm UNPCKLPD xm to xm mem to xm

XORPD MOVD

xm to xm reg to xm xm to reg

mem to xm

mem to xm xm to mem MOVDQA xm2 to xm1 xm1 to xm2 mem to xm xm to mem MOVDQU xm2 to xm1 xm1 to xm2 mem to xm xm to mem MOVQ2DQ mm to xm MOVDQ2Q xm to mm

MOVQ mm2 to mm1 mm1 to mm2 mem to xm xm to mem

PACKSSDW

xm2 to xm1

mem to xm
PACKSSWB xm2 to xm1

mem to xm
PACKUSWB xm2 to xm1

PADDQ

mem to xm mm to mm 0000 1111 : 1101 0100 : 11 mm1 mm2 mem to mm 0000 1111 : 1101 0100 : mod mm r/m xm to xm 0110 0110 : 0000 1111 : 1101 0100 : 11 xm1 xm2
mem to xm
0110 0110 : 0000 1111 : 1101 0100 : mod xm r/m 0110 0110 : 0000 1111 : 1111 11gg : 11 xm1 xm2 0110 0110 : 0000 1111 : 1111 11gg : mod xm r/m 0110 0110 : 0000 1111 : 1110 11gg : 11 xm1 xm2 0110 0110 : 0000 1111 : 1110 10gg : mod xm r/m

0110 0110 : 0000 1111 : 0010 1110 : 11 xm1 xm2 0110 0110 : 0000 1111 : 0010 1110 : mod xm r/m 0110 0110 : 0000 1111 : 0001 0101 : 11 xm1 xm2 0110 0110 : 0000 1111 : 0001 0101 : mod xm r/m 0110 0110 : 0000 1111 : 0001 0100 : 11 xm1 xm2 0110 0110 : 0000 1111 : 0001 0100 : mod xm r/m 0110 0110 : 0000 1111 : 0101 0111 : 11 xm1 xm2 0110 0110 : 0000 1111 : 0101 0111 : mod xm r/m 0110 0110 : 0000 1111 : 0110 1110 : 11 xm reg 0110 0110 : 0000 1111 : 0111 1110 : 11 xm reg 0110 0110 : 0000 1111 : 0110 1110 : mod xm r/m 0110 0110 : 0000 1111 : 0111 1110 : mod xm r/m 0110 0110 : 0000 1111 : 0110 1111 : 11 xm1 xm2 0110 0110 : 0000 1111 : 0111 1111 : 11 xm1 xm2 0110 0110 : 0000 1111 : 0110 1111 : mod xm r/m 0110 0110 : 0000 1111 : 0111 1111 : mod xm r/m 1111 0011 : 0000 1111 : 0110 1111 : 11 xm1 xm2 1111 0011 : 0000 1111 : 0111 1111 : 11 xm1 xm2 1111 0011 : 0000 1111 : 0110 1111 : mod xm r/m 1111 0011 : 0000 1111 : 0111 1111 : mod xm r/m 1111 0011 : 0000 1111 : 1101 0110 : 11 mm1 mm2 1111 0010 : 0000 1111 : 1101 0110 : 11 mm1 mm2 0110 0110 : 0000 1111 : 0111 1110 : 11 xm1 xm2 0110 0110 : 0000 1111 : 1101 0110 : 11 xm1 xm2 0110 0110 : 0000 1111 : 0111 1110 : mod xm r/m 0110 0110 : 0000 1111 : 1101 0110 : mod xm r/m 0110 0110 : 0000 1111 : 0110 1011 : 11 xm1 xm2 0110 0110 : 0000 1111 : 0110 1011 : mod xm r/m 0110 0110 : 0000 1111 : 0110 0011 : 11 xm1 xm2 0110 0110 : 0000 1111 : 0110 0011 : mod xm r/m 0110 0110 : 0000 1111 : 0110 0111 : 11 xm1 xm2 0110 0110 : 0000 1111 : 0110 0111 : mod xm r/m

PMINSW xm to xm mem to xm PMINUB xm to xm

mem to xm PMOVMSKB xm to rd

PMULH PMULL

xm2 to xm1
mem to xm

xm2 to xm1

mem to xm PMULUDQ mm to mm mem to mm

0110 0110 : 0000 1111 : 1110 1010 : 11 xm1 xm2 0110 0110 : 0000 1111 : 1110 1010 : mod xm r/m 0110 0110 : 0000 1111 : 1101 1010 : 11 xm1 xm2 0110 0110 : 0000 1111 : 1101 1010 : mod xm r/m 0110 0110 : 0000 1111 : 1101 0111 : 11 xm rd 0110 0110 : 0000 1111 : 1110 0101 : 11 xm1 xm2 0110 0110 : 0000 1111 : 1110 0101 : mod xm r/m 0110 0110 : 0000 1111 : 1101 0101 : 11 xm1 xm2 0110 0110 : 0000 1111 : 1101 0101 : mod xm r/m

0000 1111 : 1111 0100 : 11 mm1 mm2 0000 1111 : 1111 0100 : mod mm r/m

0110 0110 : 0000 1111 : 1111 0100 : 11 xm1 xm2 0110 0110 : 0000 1111 : 1111 0100 : mod xm r/m POR xm2 to xm1 0110 0110 : 0000 1111 : 1110 1011 : 11 xm1 xm2 mem to xm 0110 0110 : 0000 1111 : 1110 1011 : mod xm r/m PSADBW xm to xm 0110 0110 : 0000 1111 : 1111 0110 : 11 xm1 xm2 mem to xm 0110 0110 : 0000 1111 : 1111 0110 : mod xm r/m PSHUFLW xm to xm, ib 1111 0010 : 0000 1111 : 0111 0000 : 11 xm1 xm2 : ib mem to xm, ib 1111 0010 : 0000 1111 : 0111 0000 : 11 mod xm r/m : ib PSHUFHW xm to xm, ib 1111 0011 : 0000 1111 : 0111 0000 : 11 xm1 xm2 : ib mem to xm, ib 1111 0011 : 0000 1111 : 0111 0000 : 11 mod xm r/m : ib PSHUFD xm to xm, ib 0110 0110 : 0000 1111 : 0111 0000 : 11 xm1 xm2 : ib mem to xm, ib 0110 0110 : 0000 1111 : 0111 0000 : 11 mod xm r/m : ib PSLLDQ xm, ib 0110 0110 : 0000 1111 : 0111 0011 : 11 111 xm : ib PSLL xm1 by xm2 0110 0110 : 0000 1111 : 1111 00gg : 11 xm1 xm2 xm by mem 0110 0110 : 0000 1111 : 1111 00gg : mod xm r/m xm by i 0110 0110 : 0000 1111 : 0111 00gg : 11 110 xm : ib PSRA xm1 by xm2 0110 0110 : 0000 1111 : 1110 00gg : 11 xm1 xm2 xm by mem 0110 0110 : 0000 1111 : 1110 00gg : mod xm r/m xm by i 0110 0110 : 0000 1111 : 0111 00gg : 11 100 xm : ib PSRLDQ xm, ib 0110 0110 : 0000 1111 : 0111 0011 : 11 011 xm : ib PSRL xm1 by xm2 0110 0110 : 0000 1111 : 1101 00gg : 11 xm1 xm2 xm by mem 0110 0110 : 0000 1111 : 1101 00gg : mod xm r/m xm by i 0110 0110 : 0000 1111 : 0111 00gg : 11 010 xm : ib

xm to xm

mem to xm

PSUBQ mm to mm
mem to mm xm to xm mem to xm

0000 1111 : 1111 1011 : 11 mm1 mm2 0000 1111 : 1111 1011 : mod mm r/m
0110 0110 : 0000 1111 : 1111 1011 : 11 xm1 xm2 0110 0110 : 0000 1111 : 1111 1011 : mod xm r/m 0110 0110 : 0000 1111 : 1111 10gg : 11 xm1 xm2 0110 0110 : 0000 1111 : 1111 10gg : mod xm r/m 0110 0110 : 0000 1111 : 1110 10gg : 11 xm1 xm2

PADD

xm2 to xm1 mem to xm PADDS xm2 to xm1 xm to mem PSUBUS xm1 to xm2 xm to mem PUNPCKH xm to xm

PSUB

0000 1111 : 1101 10gg : 11 xm1 xm2 0000 1111 : 1101 10gg : mod xm r/m

0110 0110 : 0000 1111 : 0110 10gg : 11 xm1 xm2 0110 0110 : 0000 1111 : 0110 10gg : mod xm r/m PUNPCKHQDQ xm to xm 0110 0110 : 0000 1111 : 0110 1101 : 11 xm1 xm2 mem to xm 0110 0110 : 0000 1111 : 0110 1101 : mod xm r/m PUNPCKL xm to xm 0110 0110 : 0000 1111 : 0110 00gg : 11 xm1 xm2 mem to xm 0110 0110 : 0000 1111 : 0110 00gg : mod xm r/m PUNPCKLQDQ xm to xm 0110 0110 : 0000 1111 : 0110 1100 : 11 xm1 xm2 mem to xm 0110 0110 : 0000 1111 : 0110 1100 : mod xm r/m PXOR xm2 to xm1 0110 0110 : 0000 1111 : 1110 1111 : 11 xm1 xm2 mem to xm 0110 0110 : 0000 1111 : 1110 1111 : mod xm r/m MASKMOVDQU xm to xm 0110 0110 : 0000 1111 : 1111 0111 : 11 xm1 xm2

mem to xm

CLFLUSH mem 0000 1111 : 1010 1110 : mod r/m MOVNTPD xm to mem 0110 0110 : 0000 1111 : 0010 1011 : mod xm r/m MOVNTDQ xm to mem 0110 0110 : 0000 1111 : 1110 0111 : mod xm r/m MOVNTI reg to mem 0000 1111 : 1100 0011 : mod reg r/m PAUSE 1111 0011 : 1001 0000 LFENCE 0000 1111 : 1010 1110 : 11 101 000 MFENCE 0000 1111 : 1010 1110 : 11 110 000 F2XM1 11011 001 : 1111 0000 FABS 11011 001 : 1110 0001 FADD ST(0) ST(0) + 32-bit mem 11011 000 : mod 000 r/m ST(0) ST(0) + 64-bit mem 11011 100 : mod 000 r/m

xm1 to xm2 xm to mem PSUBS xm1 to xm2 FICOMP 16-bit mem 32-bit mem FIDIV ST(0) ST(0) / 16-bit mem ST(0) ST(0) / 32-bit mem FIDIVR ST(0) 16-bit mem / ST(0) ST(0) 32-bit mem / ST(0) FILD 16-bit mem 32-bit mem 64-bit mem FIMUL ST(0) ST(0) * 16-bit mem ST(0) ST(0) * 32-bit mem FINCSTP FINIT FIST 16-bit mem 32-bit mem FISTP 16-bit mem 32-bit mem 64-bit mem FISUB ST(0) ST(0) - 16-bit mem ST(0) ST(0) - 32-bit mem FISUBR ST(0) 16-bit mem - ST(0) ST(0) 32-bit mem - ST(0) FLD 32-bit mem

11011 110 : mod 011 r/m 11011 010 : mod 011 r/m 11011 110 : mod 110 r/m 11011 010 : mod 110 r/m 11011 110 : mod 111 r/m 11011 010 : mod 111 r/m 11011 111 : mod 000 r/m 11011 011 : mod 000 r/m 11011 111 : mod 101 r/m 11011 110 : mod 001 r/m 11011 010 : mod 001 r/m 11011 001 : 1111 0111 11011 011 : 1110 0011 11011 111 : mod 010 r/m 11011 011 : mod 010 r/m 11011 111 : mod 011 r/m 11011 011 : mod 011 r/m 11011 111 : mod 111 r/m 11011 110 : mod 100 r/m 11011 010 : mod 100 r/m 11011 110 : mod 101 r/m 11011 010 : mod 101 r/m 11011 001 : mod 000 r/m

ST(d) ST(0) + ST(i) 11011 d00 : 11 000 ST(i) FADDP ST(0) ST(0) + ST(i) 11011 110 : 11 000 ST(i) FBLD 11011 111 : mod 100 r/m FBSTP 11011 111 : mod 110 r/m FCHS 11011 001 1110 0000 FCLEX 11011 011 : 1110 0010 FCMOVcc Below (B) 11011 010 : 11 000 ST(i) Equal (E) 11011 010 : 11 001 ST(i) Below or Equal (BE) 11011 010 : 11 010 ST(i) Unordered (U) 11011 010 : 11 011 ST(i) Not Below (NB) 11011 011 : 11 000 ST(i) Not Equal (NE) 11011 011 : 11 001 ST(i) Not Below or Equal (NBE) 11011 011 : 11 010 ST(i) Not Unordered (NU) 11011 011 : 11 011 ST(i) FCOM 32-bit mem 11011 000 : mod 010 r/m 64-bit mem 11011 100 : mod 010 r/m ST(i) 11011 000 : 11 010 ST(i) FCOMP 32-bit mem 11011 000 : mod 011 r/m 64-bit mem 11011 100 : mod 011 r/m ST(i) 11011 000 : 11 011 ST(i) FCOMPP 11011 110 : 11 011 001 FCOMI 11011 011 : 11 110 ST(i) FCOMIP 11011 111 : 11 110 ST(i) FCOS 11011 001 : 1111 1111 FDECSTP 11011 001 : 1111 0110 FDIV ST(0) ST(0) / 16-bit mem 11011 000 : mod 110 r/m ST(0) ST(0) / 64-bit mem 11011 100 : mod 110 r/m ST(d) ST(0) / ST(i) 11011 d00 : 1111 R ST(i) FDIVP ST(0) ST(0) / ST(i) 11011 110 : 1111 1 ST(i) FDIVR ST(0) 32-bit mem / ST(0) 11011 000 : mod 111 r/m ST(0) 64-bit mem / ST(0) 11011 100 : mod 111 r/m ST(d) ST(i) / ST(0) 11011 d00 : 1111 R ST(i) FDIVRP ST(0) ST(i) / ST(0) 11011 110 : 1111 0 ST(i) FFREE 11011 101 : 1100 0 ST(i) FIADD ST(0) ST(0) / 16-bit mem 11011 110 : mod 000 r/m ST(0) ST(0) / 32-bit mem 11011 010 : mod 000 r/m FICOM 16-bit mem 11011 110 : mod 010 r/m 32-bit mem 11011 010 : mod 010 r/m FSUB ST(0) ST(0) 32-bit mem 11011 000 : mod 100 r/m ST(0) ST(0) 64-bit mem 11011 100 : mod 100 r/m ST(d) ST(0) ST(i) 11011 d00 : 1110 R ST(i) FSUBP ST(0) ST(0) ST(i) 11011 110 : 1110 1 ST(i) FSUBR ST(0) 32-bit mem - ST(0) 11011 000 : mod 101 r/m ST(0) 64-bit mem - ST(0) 11011 100 : mod 101 r/m ST(d) ST(i) ST(0) 11011 d00 : 1110 R ST(i) FSUBRP ST(i) ST(i) ST(0) 11011 110 : 1110 0 ST(i) FTST 11011 001 : 1110 0100 FUCOM 11011 101 : 1110 0 ST(i) FUCOMP 11011 101 : 1110 1 ST(i) FUCOMPP 11011 010 : 1110 1001 FUCOMI 11011 011 : 11 101 ST(i) FUCOMIP 11011 111 : 11 101 ST(i) FXAM 11011 001 : 1110 0101 FXCH 11011 001 : 1100 1 ST(i) FXTRACT 11011 001 : 1111 0100 FYL2X 11011 001 : 1111 0001 FYL2XP1 11011 001 : 1111 1001 FWAIT 1001 1011 PAVGUSB mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1011 1111 PF2ID
0000 1111 : 0000 1111 : mod mm r/m : 1011 1111 mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 0001 1101 mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 0001 1101

11011 101 : mod 000 r/m 11011 011 : mod 101 r/m 11011 001 : 11 000 ST(i) FLD1 11011 001 : 1110 1000 FLDCW 11011 001 : mod 101 r/m FLDENV 11011 001 : mod 100 r/m FLDL2E 11011 001 : 1110 1010 FLDL2T 11011 001 : 1110 1001 FLDLG2 11011 001 : 1110 1100 FLDLN2 11011 001 : 1110 1101 FLDPI 11011 001 : 1110 1011 FLDZ 11011 001 : 1110 1110 FMUL ST(0) ST(0) * 32-bit mem 11011 000 : mod 001 r/m ST(0) ST(0) * 64-bit mem 11011 100 : mod 001 r/m ST(d) ST(0) * ST(i) 11011 d00 : 1100 1 ST(i) FMULP ST(0) ST(0) * ST(i) 11011 110 : 1100 1 ST(i) FNOP 11011 001 : 1101 0000 FPATAN 11011 001 : 1111 0011 FPREM 11011 001 : 1111 1000 FPREM1 11011 001 : 1111 0101 FPTAN 11011 001 : 1111 0010 FRNDINT 11011 001 : 1111 1100 FRSTOR 11011 101 : mod 100 r/m FSAVE 11011 101 : mod 110 r/m FSCALE 11011 001 : 1111 1101 FSIN 11011 001 : 1111 1110 FSINCOS 11011 001 : 1111 1011 FSQRT 11011 001 : 1111 1010 FST 32-bit mem 11011 001 : mod 010 r/m 64-bit mem 11011 101 : mod 010 r/m ST(i) 11011 101 : 11 010 ST(i) FSTCW 11011 001 : mod 111 r/m FSTENV 11011 001 : mod 110 r/m FSTP 32-bit mem 11011 001 : mod 011 r/m 64-bit mem 11011 101 : mod 011 r/m 80-bit mem 11011 011 : mod 111 r/m ST(i) 11011 101 : 11 011 ST(i) FSTSW AX FPU Status Word 11011 111 : 1110 0000 mem FPU Status Word 11011 101 : mod 111 r/m
mem to mm

64-bit mem 80-bit mem ST(i)

PFMIN PFMUL PFNACC PFPNACC PFRCP PFRCPIT1 PFRCPIT2 PFRSQIT1 PFRSQRT PFSUB PFSUBR PI2FD

mem to mm

0000 1111 : 0000 1111 : mod mm r/m : 1010 0100 mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1001 0100 mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1001 0100 mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1011 0100 mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1011 0100 mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1000 1010 mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1000 1010 mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1000 1110 mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1000 1110 mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1001 0110 mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1001 0110 mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1010 0110 mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1010 0110 mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1011 0110 mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1011 0110 mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1010 0111 mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1010 0111 mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1001 0111 mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1001 0111 mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1001 1010 mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1001 1010 mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1010 1010 mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1010 1010 mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 0000 1101

PF2IW

mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 0001 1100 0000 1111 : 0000 1111 : mod mm r/m : 0001 1100 PFACC mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1010 1110 mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1010 1110 PFADD mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1001 1110 mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1001 1110 PFCMPEQ mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1011 0000 mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1011 0000 PFCMPGE mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1001 0000 mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1001 0000 PFCMPGT mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1010 0000 mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1010 0000 PFMAX mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1010 0100 PFMAX mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1010 0100

mem to mm

0000 1111 : 0000 1111 : mod mm r/m : 0000 1101 mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 0000 1101 mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 0000 1101 PI2FW mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 0000 1100 mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 0000 1100 PMULHRW mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1011 0111 mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1011 0111 PREFETCH mm2 to mm1 0000 1111 : 0000 1101 : 11 000 mm

mem to mm

PI2FD

mem to mm
PREFETCHW mm2 to mm1

mem to mm

0000 1111 : 0000 1101 : mod 000 r/m 0000 1111 : 0000 1101 : 11 001 mm 0000 1111 : 0000 1101 : mod 001 r/m 0000 1111 : 0000 1110

PSWAPD FEMMS

mm2 to mm1 0000 1111 : 0000 1111 : 11 mm1 mm2 : 1011 1011 mem to mm 0000 1111 : 0000 1111 : mod mm r/m : 1011 1011

Pentium 6th Generation & NetBurst Processor Micro-Architectures with Interface to Memory Subsystem:
System Bus (64-bit) Bus Interface Unit 3rd Level Cache (NB server option) 2 Level Cache
nd

1st Level Cache Architecture Diagram:

Bank 1 Ban 2 Ban 3 Ban 4 Ban 5 Ban 6 Ban 7 Ban 8

Execution Units/Ports in Out-of-Order Core:

Load Unit
(16 entry buffer)

Store Addr. (12 entry)

Store Data (12 entry)

Banks interleaved on 4-byte memory boundaries

486 - 128 * 16-B lines * 4 sets = 8K

Pentium - 128 * 32-B lines * 2 sets = 8K

Reservation Station

P2/P3 - 128 * 32-B lines * 4 sets = 16K P4 - 32 * 64-B lines * 4 sets = 8K

NetBurst has only 4 ports.

Port 2 Port 4 Port 3 Port 1 (V) Port 0 (U)

Integer/FP, addr. generate, MMX, P3 FP, NB ALU 0 (2x), FP Move Integer, MMX, P3 FP, NB ALU1 (2x speed), Int. Operation (normal speed), FP Execute

(4-way P6, 8-way NB)

1 Level Cache (Pro Data

st

2-way; 4-way P2, P3, & NB)

It stores mem addresses in port 3 & data in port 0.

1st Level Instruction Cache (Pro, P2, & P3

4-way set associative)

Microcode Rom ID0 ID1 RAT ROB IFU0 IFU1 IFU2 Rd (In-Order issue)

Front End 12K ops 8-way Fetch/Decode NB Trace Cache

Execution
(Out-Of-Order Core) RS Port 0-4 ROB Wb

Retirement
(In-Order unit) 3 ops in cycle

Intel Architecture Registers

(Reg Retire File)

BTBs/Branch Prediction

(P6 256 entry BTB, NB 512 entry) BTB0 BTB1

Branch History Update

Information Returned by CPUID Instruction

Initial EAX Value EAX EBX ECX EDX EAX EBX Information Provided about the Processor Basic CPU Information Maximum Input Value for Basic CPUID Information Genu ntel ineI Version Information (Type, Family, Model, and Stepping ID) Bits 7-0: Brand Index Bits 15-8: CLFLUSH line size. (Value returned * 8 = cache line size) Bits 23-16: Reserved Bits 31-24: Processor local APIC physical ID Reserved Feature Information Cache and TLB Information Byte register AL indicates the number of times the CPUID instruction must Cache and TLB Information be executed with an input value of 2 to get a complete description of the Cache and TLB Information processors caches and TBLs. Bit 31 of each register indicates if it contains Cache and TLB Information valid info. (cleared is 0, reserved is 1). Info. (any order) in 1 B descriptors. Reserved Reserved

0H

1H ECX EDX EAX EBX ECX EDX EAX EBX

2H 3H

ECX EDX EAX EBX ECX EDX EAX EBX ECX EDX EAX EBX ECX EDX EAX EBX ECX EDX EAX EBX ECX EDX

80000000H

80000001H

80000002H

80000003H

80000004H

Bits 00-31 of 96-bit processor serial number. (Available in Pentium III only; otherwise reserved.) Bits 32-63 of 96-bit processor serial number. (Available in Pentium III only; otherwise reserved.) Extended Function CPUID Information Maximum Input Value for Extended Function CPUID Information Reserved. Reserved. Reserved. Extended Processor Signature and Extended Feature Bits. (Currently Reserved.) Reserved. Reserved. Reserved. Processor Brand String. Processor Brand String Continued. Processor Brand String Continued. Processor Brand String Continued. Processor Brand String Continued. Processor Brand String Continued. Processor Brand String Continued. Processor Brand String Continued. Processor Brand String Continued. Processor Brand String Continued. Processor Brand String Continued. Processor Brand String Continued.

Highest CPUID Source Operand for IA-32 Processors

IA-32 Processors Earlier Intel486 Processors Later Intel486 and Pentium Processors Pentium Pro, II, and Celeron Processors Pentium III Processors Pentium 4 Processors Intel Xenon Processors 31 28 27 19 15 13 20 16 14 12 Extende Extende EAX d d Family Model Processor Type Highest Value in EAX Basic Information Extended Function Information CPUID Not Implemented CPUID Not Implemented 1H Not Implemented 2H Not Implemented 3H Not Implemented 2H 80000004H 2H 80000004H 11 8 Family 7 4 Model 3 0 Stepping ID Type Original OEM Processor Intel OverDrive Processor Duel Processor Intel Reserved. Encoding 00B 01B 10B 11B

Processor Type Field Chart

Bit # 0 1 2 3 4 5 6 7 Mnemonic FPU VME DE PSE TSC MSR PAE MCE

CPUID Feature Flags Returned in EDX Register

Description Floating Point Unit On-Chip. The Processor contains an x87 FPU. Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements, including CR4.VME for controlling the feature, CR4.PVI for protected mode virtual interrupts, software interrupt indirection, expansion of the TSS with the software indirection bitmap, and EFLAGS.VIF and EFLAGS.VIP flags. Debugging Extensions. Support for I/O breakpoints, including CR4.DE for controlling the feature, and optional trapping of accesses to DR4 and DR5. Page Size Extension. Large pages of size 4Mb are supported, including CR4.PSE for controlling the feature, the defined dirty bit in PDE (Page Directory Entries), optional reserved bit trapping in CR3, PDEs, and PTEs. Time Stamp Counter. The RDTSC instruction is supported, including CR4.PSE for controlling privilege. Model Specific Registers RDMSR and WRMSR Instructions. The RDMSR and WRMSR instructions are supported. Some of the MSRs are implementation dependent. Physical Address Extension. Physical addresses greater than 32 bits are supported: extended page table entry formats, an extra level in the page translation tables is defined, 2 Mb pages are supported instead if 4 Mb pages if PAE bit is 1. The actual number of address bits beyond 32 is not defined, and is implementation specific. Machine Check Exception. Exception 18 is defined for Machine Checks, including CR4.MCE for controlling the feature. This feature does not define the model-specific implementations of machine-check error logging, reporting, and processor shutdowns. Machine Check exception handlers may have to depend on processor

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30-31

CX8 APIC Reserved SEP MTRR PGE MCA CMOV PAT PSE-36 PSN CLFSH Reserved DS ACPI MMX FXSR SSE SSE2 SS Reserved TM Reserved

version to do model specific processing of the exception, or test for the presence of the Machine Check feature. CMPXCHG8B Instruction. The CMPXCHG8B (64-bits) instruction is supported (implicitly locked & atomic). APIC On-Chip. The processor contains an Advanced Programmable Interrupt Controller (APIC), responding to memory-mapped commands in the physical address range FFFE0000H to FFFE0FFFH (by default some processors permit the APIC to be relocated). Reserved SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXITand associated MSRs are supported. Memory Type Range Registers. MTRRs are supported. The MTRRcap MSR contains feature bits that describe what memory types, how many variable MTRRS, and whether fixed MTRRs are supported. PTE Global Bit. The global bit in page directory entries (PDEs) and page table entries (PTEs) is supported, indicating TLB entries that are common to different processes and need not be flushed. The CR4.PGE bit controls this feature. Macine Check Architecture. The machine Check Architecture, which provides a compatible mechanism for error reporting in Pentium 4 processors, P6 family processors, and future processors, is supported. The MCG_CAP MSR contains feature bits describing how many banks of error reporting MSRs are supported. Conditional Move Instructions. The conditional move instruction CMOV is supported. In addition, if x87 FPU is present as indicated by the CPUID.FPU feature bit, then FCOMI and FCMOV instructions are supported. Page Attribute Table. Page Attribute Table is supported. This feature augments the Memory Type Range Registers (MTRRs), allowing an OS to specify attributes of memory on a 4K granularity through a linear address. 32-Bit Page Size Extension. Extended 4-Mb pages that are capable of addressing physical memiry beyond 4 Gb are supported. This feature indicates that the upper four bits of the physical address of the 4-Mb page is encoded by bits 13-16 of the page directory entry. Processor Serial Number. The processor supports the 96-bit processor ID number feature and it is enabled. CLFLUSH Instruction. CLFLUSH Instruction is supported. Reserved Debug Store. The processor supports the ability to write debug information into a memory resident buffer. This feature is used by the branch trace store (BTS) and precise event-based sampling (PEBS) facilities. Thermal Monitor and Software Controlled Clock Facilities. The processor implements internal MSRs that allow processor temperature to be monitored and processor performance to be modulated in predefined duty cycles under software control. Intel MMX Technology. The processor supports the Intel MMX technology. FXSAVE and FXRSTOR Instructions. The FXSAVE and FXSTOR instructions are supported for fast save and restore of the floating-point context. Presence if this bit also indicates that CR4.OSFXSR is available for an operating system to indicate that it supports the FXSAVE and FXSTOR instructions. SSE. The processor supports the SSE extensions. SSE2. The processor supports the SSE2 extensions. Self Snoop. The processor supports the management of conflicting memory types by performing a snoop of its own cache structure for transactions issued to the bus. Reserved Thermal Monitor. The processor implements the thermal monitor automatic thermal control circuitry (TCC). Reserved

Encoding of Cache and TLB Descriptors

Descriptor Value 00H 01H 02H 03H 04H 06H 08H 0AH 0CH 22H 23H 25H 29H 40H 41H 42H 43H Cache or TLB Description Null Descriptor Instruction TLB: 4 Kb Pages, 4-way set associative, 32 entries Instruction TLB: 4 Mb Pages, 4-way set associative, 2 entries Data TLB: 4 Kb Pages, 4-way set associative, 64 entries Data TLB: 4 Mb Pages, 4-way set associative, 8 entries 1st level instruction cache: 8 Kb, 4-way set associative, 32 byte line size 1st level instruction cache: 16 Kb, 4-way set associative, 32 byte line size 1st level data cache: 8 Kb, 2-way set associative, 32 byte line size 1st level data cache: 16 Kb, 4-way set associative, 32 byte line size 3rd level cache: 512 Kb, 4-way set associative, 64 byte line size 3rd level cache: 1 Mb, 8-way set associative, 64 byte line size 3rd level cache: 2 Mb, 8-way set associative, 64 byte line size 3rd level cache: 4 Mb, 8-way set associative, 64 byte line size No 2nd level cache or, if processor contains a valid 2nd level cache, no 3rd level cache 2nd level cache: 128 Kb, 4-way set associative, 32 byte line size 2nd level cache: 256 Kb, 4-way set associative, 32 byte line size 2nd level cache: 512 Kb, 4-way set associative, 32 byte line size

44H 45H 50H 51H 52H 5BH 5CH 5DH 66H 67H 68H 70H 71H 72H 79H 7AH 7BH 7CH 82H 84H 85H

2nd level cache: 1 Mb, 4-way set associative, 32 byte line size 2nd level cache: 2 Mb, 4-way set associative, 32 byte line size Instruction TLB: 4 Kb and 2 Mb or 4 Mb pages, 64 entries Instruction TLB: 4 Kb and 2 Mb or 4 Mb pages, 128 entries Instruction TLB: 4 Kb and 2 Mb or 4 Mb pages, 256 entries Data TLB: 4 Kb and 4 Mb pages, 64 entries Data TLB: 4 Kb and 4 Mb pages, 128 entries Data TLB: 4 Kb and 4 Mb pages, 256 entries 1st level data cache: 8 Kb, 4-way set associative, 64 byte line size 1st level data cache: 16 Kb, 4-way set associative, 64 byte line size 1st level data cache: 32 Kb, 4-way set associative, 64 byte line size Trace cache: 12K-op, 8-way set associative Trace cache: 16K-op, 8-way set associative Trace cache: 32K-op, 8-way set associative 2nd level cache: 128 Kb, 8-way set associative, sectored, 64 byte line size 2nd level cache: 256 Kb, 8-way set associative, sectored, 64 byte line size 2nd level cache: 512 Kb, 8-way set associative, sectored, 64 byte line size 2nd level cache: 1 Mb, 8-way set associative, sectored, 64 byte line size 2nd level cache: 256 Kb, 8-way set associative, 32 byte line size 2nd level cache: 1 Mb, 8-way set associative, 32 byte line size 2nd level cache: 2 Mb, 8-way set associative, 32 byte line size

Mapping of Brand Indices and IA-32 Processor Brand Strings

Brand Index 0 1 2 3 47 8 9 255 Brand String This processor does not support the brand identification feature Celeron processor Pentium III processor Intel Pentium III Xeon processor Reserved for future processor Intel Pentium 4 processor Reserved for future processor

Hexadecimal-Binary-Decimal Conversion
Hex 0 1 2 3 4 5 6 7 Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 000X 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 00X0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 0X00 0 256 512 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 X000 0 4096 8192 1228 8 1638 4 2048 0 2457 6 2867 2 3276 8 3686 4 4096 0 4505 6 4915 2 5324 8 5734 4 6144 0

32-Bit Register Review EAX/EDX EBX ECX EBP ESI EDI ESP General-purpose, MUL, DIV, port I/O, report Pentium cycles Great general-purpose use. No important special functions. General-purpose, REP string inst. loop count, low B shift count Address stack variables (stack-frame pointer), can borrow use General purpose, source data pointer for REP string instructions General purpose, destination pointer for REP string instructions Address stack parameters & variables, cannot use unless no int.

8 9 A B C D E F