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Experimental Design of a Nonlinear Control Technique for Three-Phase Shunt Active Power Filter
Salem Rahmani, Member, IEEE, Nassar Mendalek, Member, IEEE, and Kamal Al-Haddad, Fellow, IEEE
AbstractThis paper presents a nonlinear control technique for a three-phase shunt active power lter (SAPF). The method provides compensation for reactive, unbalanced, and harmonic load current components. A proportionalintegral (PI) control law is derived through linearization of the inherently nonlinear SAPF system model, so that the tasks of current control dynamics and dc capacitor voltage dynamics become decoupled. This decoupling allows us to control the SAPF output currents and the dc bus voltage independently of each other, thereby providing either one of these decoupled subsystems a dynamic response that signicantly slower than that of the other. To overcome the drawbacks of the conventional method, a computational control delay compensation method, which delaylessly and accurately generates the SAPF reference currents, is proposed. The rst step is to extract the SAPF reference currents from the sensed nonlinear load currents by applying the synchronous reference frame method, where a three-phase diode bridge rectier with RL load is taken as the nonlinear load, and then, the reference currents are modied, so that the delay will be compensated. The converter, which is controlled by the described control strategy, guarantees balanced overall supply currents, unity displacement power factor, and reduced harmonic load currents in the common coupling point. Various simulation and experimental results demonstrate the high performance of the nonlinear controller. Index TermsActive power lter, control delay compensation, modeling, nonactive load current compensation, nonlinear control, power quality.

I. I NTRODUCTION ARMONICS are typically caused by the use of nonlinear loads, such as switch-mode power converters, power-electronics-operated adjustable-speed drives, uorescent lamps, arc furnaces, welding equipment, and other nonlinear loads used in both domestic and industrial applications. The presence of harmonics in the system results in several effects (including increased heating losses in transformers, motors, and lines; low power factor; torque pulsation in motors; and poor utilization of distribution wiring and plant). In response to the power quality concerns of typical power distribution systems in terms of harmonic current distortion and power factor,
Manuscript received April 28, 2008; revised January 28, 2009, May 29, 2009, and September 2, 2009; acccepted December 2, 2009. Date of publication January 8, 2010; date of current version September 10, 2010. This work was supported by Canada Research Chair in Energy Conversion and Power Electronics at the cole de Technologie Suprieure. S. Rahmani and K. Al-Haddad are with the cole de Technologie Suprieure, University of Qubec, Montreal, QC H3C 1K3, Canada (e-mail: Salem.Rahmani@esstt.rnu.tn; kamal@ele.etsmtl.ca). N. Mendalek is with the Department of Electrical, Computer and Communication Engineering, Notre Dame University, Louaize, Lebanon (e-mail: nmendalek@ndu.edu.lb). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TIE.2009.2038945

IEEE 519 and IEC EN 61000-3 standards specify regulations governing harmonic compliance. A passive lter has been a viable approach because of low cost and high efciency. However, the performance of the passive scheme has a limitation since the addition of the passive lter interfaces with the system impedance and causes resonance with other networks [1], [2]. Numerous active solutions, which are becoming a more effective means to meet the harmonic standards by overcoming the drawback of the passive lter, have been proposed [3][10]. The SAPF operates by injecting the reactive, unbalanced, and harmonic load current components into the utility system with the same magnitudes as the nonactive load currents demanded by a given nonlinear load but with opposite phases [11][15]. Among the subjects related to the active lters design and applications, the methods for extraction of the harmonic load currents and determination of the lter reference current play an important and crucial role. Indeed, the accuracy and speed of the SAPF response are related to this point [16], [17]. The methods of reference current generation are categorized into two main elds: 1) time-domain and 2) frequencydomain methods [11][17]. Time-domain methods such as dq transformation (or synchronous rotating reference frame), pq transformation (or instantaneous reactive power), symmetrical components transformation, etc., are based on the measurements and transformation of three-phase quantities [12]. The main advantage of these time-domain control methods, compared with the frequency-domain methods, based on the fast Fourier transformation is the fast response obtained. On the other side, frequency-domain methods provide accurate individual and multiple harmonic load current detection. The compensation method presented in this paper is the time-domain control type of compensation, where all harmonic load current components are targeted and compensated. An SAPF offers different options of compensation, such as harmonic attenuation, load balancing, resonance elimination, and displacement power factor improvement [1], [9]. Thus, the control strategy and the method for extracting the nonactive load current references will depend on the compensation objectives [11][17]. Although conventional linear controllers may fulll certain compromises between steady-state performance, and harmonic load current compensation and dc bus voltage regulation, they remain unable to compensate the inherent nonlinearity of such circuits, which is generated by the switching process. This manifests with important overshoots and long settling times, during transients from both the ac or dc side [2], [11], [12], [15]. On the other hand, most of the techniques mentioned in the literature assume sinusoidal supply voltages when compensating unbalanced nonlinear load currents [3], [12]. However,

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in reality, the utility voltage available at the downstream end is nonsinusoidal due to the harmonic load currents. A thorough investigation of the experimental results reported in [2], [8], and [16], reveals that the total harmonic distortion (THD) in the supply currents cannot be brought down below 5% to satisfy the IEEE-519 standard. This is due to the presence of notches in the supply currents, whereas feedforward control methods are used. The drawbacks can be eliminated by using the nonlinear control theory, ideally without exaggerating computational and implementation complexities. In addition, Youssef et al. [18] and Yacoubi et al. [19], [20] implemented very useful advanced nonlinear control techniques to active rectiers with active ltering function. These control techniques can be applied to active ltering technology. In [21], a nonlinear control strategy of an SAPF based on the internal model principle is proposed. The stabilization of the dc-link voltage dynamics is addressed, along with the fulllment of the harmonic load current compensation objective. The two-time scale behavior of the SAF is exploited to apply the averaging theory in the control design. In [22], a nonlinear control strategy for an active lter is proposed. It is based on the inputoutput linearization method implemented on a dq0 rotating current reference frame. The structure balances the load currents, obtains unity displacement power factor, and reduces the harmonic load currents in arbitrary loads. In [23], the current loop dynamics in the synchronous dq frame are controlled using multiple-input multiple-output optimal control based on the predictive control approach. The nonlinear control strategy does not require online optimization and overcomes the aforementioned difculties by ensuring fast current tracking, current loop stability, and compensation robustness under nonideal load and/or supply conditions. In this paper, the theoretical development of the SAPF is based on the work done in [24]. However, no experimental validation for the proposed control was conducted. It was shown by simulations that the nonlinear control technique enhances the dynamic performance of the SAPF modeled in the synchronous orthogonal dq frame. The exact feedback linearization theory was applied in the design of the controller. This control strategy allowed the decoupling of the currents, enhanced their tracking behavior, and improved the dc voltage regulation. The reference signals were obtained by extracting the harmonic currents from the measured load currents. In the orthogonal frame, the fundamental current component can be seen as a dc component, and as a consequence, the harmonic load currents can be extracted with high-pass lters (HPFs). The HPFs were based on fourthorder Butterworth low-pass lters. The main problem with this method is the delay that occurs when the control system is digitally implemented. Even if the HPF would perfectly perform, not all the harmonic load currents could be ltered. In addition, the system cannot completely compensate load current unbalance because of the phase shift caused by the lter. The studies on active power lters, which appeared in the literature [1][17], [24], all ignore the delay time such as the current response delay generated by the boost inductors and dclink voltage feedback delay due to the detection circuits. The delay time caused by the lter control algorithm is due to the low-pass lter used for reference current calculation and

the active lter natural response determined by boost inductors and dc-link voltage capacitors [25]. To simplify the current control plant to be of rst-order delay type, voltage decouplers, rotating frame transformation, and pole-zero cancellation techniques were used in current regulators. In [26], the concept of delay time was discussed. The method considered the instantaneous power delay caused by the current regulators and dc-link voltage feedback circuit and presented the load power estimation method to improve the dynamic response of input power regulation. A computational control delay compensation method was also presented in [27], where only the feedforward control of the load current was used. The method is very effective for decreasing the magnitudes of the lower order harmonic load currents but cannot fully compensate the fast load current transients. The HPF time constant is about 8 ms. It is reported that, in the case of load current step changes, the system takes about 19 ms to reach steady state. In addition, a multistage adaptive lter was discussed in [28]. This method combines a low-pass lter and an adaptive predictive lter, making it possible to extract the sinusoidal active current component from the distorted waveform without harmful phase shift, even when the frequency and amplitude simultaneously altered. The drawback of this technique is the difculty to design the dc-link voltage and the current regulators. In this paper, the authors propose a detailed nonlinear control technique, as previously introduced in [24], that uses a computational control delay compensation method to overcome the conventional method drawbacks. The rst step is to extract the SAPF reference current. Then, the phase shift of the reference current is modied, so that the delay will be compensated. In addition, the nonlinear control is theoretically established and experimentally validated using both simulations and experiments. Consequently, the currents very closely track their references. The SAPF compensates for unwanted reactive, unbalanced, and harmonic load current components under nonsinusoidal supply voltage conditions. The SAPF performance, during both nominal and severe operating conditions, is then evaluated in real time using the dSPACE DS1104 controller board, which is supported by a Matlab/Simulink Real-Time Workshop environment. II. T HREE -P HASE S HUNT ACTIVE F ILTER T OPOLOGY An SAPF conguration is considered in this paper in order to avoid harmonic pollution along the power line caused by a three-phase diode bridge rectier load, followed by an inductor LL in series with a resistor RL . The SAPF acts as a controlled current source connected in parallel with the nonlinear load. It has the structure illustrated in Fig. 1. It consists of a fullbridge voltage source pulsewidth-modulation inverter, a dc-side capacitor Cdc , and ac-side high-frequency inductors Lc that are required to shape the compensator input currents i1 , i2 , and i3 . A. Modeling of Shunt Active Filter Kirchoffs rules for voltages and currents, as applied to this system, provide us with the three differential equations in the

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Fig. 1. Basic circuit of SAPF.

stationary abc frame v1 = v1N = Lc v2 = v2N v3 = v3N di1 + Rc i1 + v1M + vM N dt

The switching function ck of the kth leg of the converter (for k = 1, 2, 3) is dened as ck = 1, 0, if Sk is On and Sk is Off if Sk is Off and Sk is On. (3)

di2 + Rc i2 + v2M + vM N = Lc dt di3 + Rc i3 + v3M + vM N = Lc dt (1)

Thus, vkM = ck vdc . The phase-k dynamic equation of the lters model is given by the following equation: dik Rc 1 = ik dt Lc Lc ck 1 cm 3 m=1
3

where v1 , v2 , and v3 denote the line-to-ground voltages of the three-phase balanced system measured at the point of common coupling (PCC). Using the following assumptions: v1 + v2 + v3 = 0, the following relation is obtained: vM N = 1 vmM . 3 m=1
3

vdc +

vk . Lc

(4)

A switching state function dnk is dened as dnk = ck 1 cm 3 m=1

3

i1 + i2 + i3 = 0

.
n

(5)

(2)

The value of dnk depends on the switching state n and the phase k. In other words, dnk simultaneously depends on the switching functions of the three legs of the SAPF. This shows the interaction between the three phases.

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The resulting transformed model in the synchronous orthogonal rotating frame is given as follows [24]: Rc dnd i Lc Lc id v d d 1 d dnq c iq = Rc Lc iq + vq . L dt Lc dnq dnd vdc vdc 0 0 Cdc Cdc (6) B. Harmonic Current Control A PI control law was derived through linearization of the inherently nonlinear SAPF system model, thereby decoupling the tasks of harmonic load currents tracking and dc capacitor voltage regulation. This decoupling allows the SAPF to compensate for the ac currents and the dc-bus voltage independently of each other but results in either one of these decoupled subsystems having a dynamic response that is signicantly slower than that of the other. In order to obtain a fast dynamic response of harmonic load currents compensation, the structure of a fast inner loop (current tracking loop) and a slow outer loop (dc voltage regulation loop) is adopted. The dynamics of the ac currents in (6) can be rewritten as follows: Lc did + Rc id = Lc iq vdc dnd + vd dt diq + Rc iq = Lc id vdc dnq + vq . Lc dt

Fig. 2. Inner control loop of the current iq .

Fig. 3. DC-bus voltage control loop.

inate the zero in the closed-loop transfer function, a prelter Gp (s) is added, as shown in Fig. 2, i.e., Gp (s) = 1 . 1 + (kp /ki )s (12)

The response of the current loops becomes that of a secondorder transfer function with no zero; hence, the following design relations can easily be derived: kp = 2ni Lc Rc and 2 ki = Lc ni . The control law is given by the following: dnd = dnq = vd + Lc iq ud vdc vq Lc id uq . vdc (13) (14)

(7)

Let us dene the equivalent inputs as ud = Lc iq vdc dnd + vd uq = Lc id vdc dnq + vq . (8)

The inner control loop of the current iq is shown in Fig. 2. C. DC Voltage Regulation The instantaneous active and reactive powers exchanged between the SAPF and the ac mains are given by p = vd id and q = vd iq (because vq = 0 under ideal supply conditions, as shown here). To maintain some vdc level across the dc capacitor of the SAPF, the losses through the active power lters resistiveinductive branches can be compensated by acting on the supply current. Ideally, it must act on the active current component id Cdc dvdc = dnd id + dnq iq . dt (15)

Thus, through the input transformation (8), the coupled dynamics of the currents tracking problem have been transformed into decoupled dynamics. Hence, the currents id and iq can independently be controlled by acting upon inputs ud and uq , respectively. By using the error signals d = i id and q = i i d i iq , and applying proportional integral compensation, one q can choose dnd and dnq such that ud = kpd + ki i uq = kpq + ki i d dt i q dt. i (9)

The transfer function of the PI compensator is Gi (s) = s + kp Uq (s) Ud (s) = = kp q (s) d (s) s I I
ki

An equivalent input udc is dened as udc = dnd id + dnq iq . (10) (16)

and the closed-loop transfer function of the current loop is

ki s + kp Iq (s) Id (s) kp = = Iq (s) Id (s) Lc s2 + (Rc +kp ) s + Lc

To regulate the dc voltage vdc , the error vdc = vdc vdc is passed through a PI-type controller given by

udc = k1 vdc + k2
ki Lc

vdc dt.

(17)

(11) The transfer function of the PI compensator is Gv (s) = s + k2 Udc (s) 1 . = k1 s Vdc (s)
k

For the optimal value of the damping factor = 2/2, the theoretical overshoot is 20.79%. Nevertheless, in order to elim-

(18)

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Fig. 4. Nonlinear control scheme of the SAPF.

The resulting closed-loop transfer function is s + nv Vdc (s) 2 = 2nv 2 2 Vdc (s) s + 2nv s + nv where the proportional and integral gains are k1 = 2nv Cdc and
2 k2 = nv Cdc .

The control effort of this outer loop is given by the following [24]: (19) i = do 2 vdc u . dc 3 V (20)

Fig. 3 illustrates the outer control loop of the dc voltage.

The reference current in (20) is added to the harmonic reference current of id loop, as shown in Fig. 4. i is a dc do component, and it will force the SAPF to generate or to draw

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Fig. 5.

Delays generated by the system.

Fig. 6. Current controller performance without control delay compensation.

a small current at the fundamental frequency. Furthermore, by designing the dc voltage loop to be much slower than the current loops, there would not be any interaction between the two loops. Fig. 4 represents the nonlinear control of the SAPF. III. C ONTROL D ELAY C OMPENSATION In this paper, the analytical model and design methods are described in continuous time. In practice, a dc-link voltage regulator, current regulators, and low-pass lter are implemented by a personal-computer-based discrete system. A computational control delay compensation method is used. Fig. 5 illustrates the total delay resulting from the chain of acquisition and the real-time controller, which uses the sampling period named Ts . The delay time Tsens caused by boost inductors and dc-link capacitor is approximated to 100 s, which corresponds to a dephasing angle sens of 2 at 60 Hz. Moreover, the interface communication and computing time of the algorithms x the minimum sampling period of the DSP. The delay Tcirc brought by the digital circuit is thus equal to Ts . The delivered signal by the numerical system has pace in stairs of width Ts . By carrying out the average over each sampling period, one obtains the signal s3 . The delay Tsamp resulting from this average over one sampling period is equal to Ts /2. The delay Tcomp due to the discretization and the computing time is equal to 3Ts /2. The sampling period for program execution is Ts = 52 s. Thus, the total delay Td is approximately equal to 178 s. While s1 is the signal without delay, s2 is the signal at the output of the sensor, and s3 is the signal at the output of the DSP. The delay Td involves a dephasing angle d1 = 3.8 at 60 Hz between the reference current and the current injected by the SAPF. The proposed strategy consists of creating a phase lead at 60 Hz on the reference currents to compensate for the total delay. Therefore, from the measured voltages vs () at the PCC, the phase-locked loop rebuilds the voltages by integrating the desired dephasings (sens and comp ). Consequently, the reference currents are corrected, and the lter currents behave as desired.

Fig. 7. Waveforms showing the tracking performances of the inner loop.

Where sens is the delay caused by boost inductors and dclink capacitor, comp is the delay caused by discrete digital implementation and the computing time.

A. Current Controller Performance Fig. 6 shows test results of the current controller without control delay compensation. The d-axis id , the q-axis iq , and the phase 1 active lter current in steady-state operation superposed with their respective references are shown. The results show the appearance of a time delay between the reference currents and the sensed currents. Fig. 7 shows the test results of the nonlinear control with the proposed control delay compensation method. The results clearly show that the oscillating current harmonics injected by the lter track their reference templates with high accuracy. It demonstrates that the computational control delay compensation method performs very well.

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TABLE I S PECIFICATION PARAMETERS

IV. S IMULATION R ESULTS The nonlinear control scheme and compensation by SAPF is simulated under MATLAB/Simulink and power system blockset environment to estimate its performance. The nonlinear load consists of one three-phase and one single-phase diode rectier, so that the effectiveness of the nonlinear control scheme to compensate for unbalanced load can be tested. The rectiers are feeding RL-type circuits. The source current waveforms of the simulation results have been analyzed to obtain their THD under varying load conditions. The main purpose of the simulation is set to study three different aspects: 1) reactive and harmonic load currents compensation; 2) dynamic response of the SAPF to load variations; and 3) compensation of nonactive load currents. The system parameters used in these simulations are given in Table I. One can read, for the case of a balanced load, the following main power magnitudes (active power, reactive power, distortion power, and apparent power) and power factor: PL = 818.6 W; QL = 162 VAR; DL = 207.4 VAR; SL = 859.9 VA; and P F = 95.2%. The SAPF power magnitudes (active power, reactive power, distortion power, and apparent power) are given as follows: Pc = 6.6 W, Qc = 159 VAR, Dc = 226.6 VAR, and Sc = 276.9 VA. The source power magnitudes (active power, reactive power, and apparent power) and power factor are given as follows: Ps = 825.2 W, Qs = 3 VAR, Ss = 826.2 VA, and P F = 99.88%. One can deduce that the SAPF power rating to compensate reactive and harmonic load current components is 32.2% (Sc = 32.2%SL ) of the load nominal power. For the case of unbalanced nonlinear loads, the fundamental positive-sequence active power, reactive power, and apparent power are given as follows: PL1+ = 503.8 W, QL1+ = 65.55 VAR, and SL = 532.1 VA. The SAPF fundamental positive-sequence active power, positive-sequence reactive power, and apparent power are given as follows: Pc1+ = 8.22 W, Qc1+ = 60.8 VAR, and Sc = 197 VA. The source fundamental positive-sequence active power, positive-sequence reactive power, and apparent power are given as follows: Ps1+ = 512 W, Qs1+ = 4.75 VAR, and Ss = 513 VA.

Fig. 8.

Steady-state response of the SAPF.

Therefore, the maximum rating of the SAPF to achieve nonactive load current compensation represents 37% of the load nominal power. A. Reactive and Harmonic Currents Compensation of a Nonlinear Load The simulation results of the SAPF system are presented in Fig. 8. The supply voltage vs1 , load currents iL123 , supply currents is123 , SAPF currents (ic123 ), and dc voltage vdc are depicted there. The THD of the current generated by the nonlinear load is observed to be approximately 25.8%, whereas the compensated supply current has a THD of approximately 2.62% at steady state. A graphical representation of the load current (top plot) and the supply current (bottom plot) after SAPF connection appears in Fig. 9(a) and (b). The results presented in Figs. 8 and 9 coincide with those included in Figs. 13 and 14 of Section V-A. B. Response of the SAPF to Nonlinear Load Variation In practice, nonlinear loads are usually time varying in nature. Therefore, it is necessary to study the dynamic performance of the SAPF when variations in the nonlinear loads are considered. The nonlinear load current was subjected to 100% step decrease at t = 366.7 ms and 100% step increase at t = 483.3 ms. In other terms, the value of the load resistance is changed from 16 to 8 at t = 366.7 ms and then changed from 8 to 16 at t = 483.3 ms. The relevant waveforms are depicted in Fig. 10. These results conrm the good dynamic performance of the SAPF for a rapid change in the nonlinear load current. The waveforms presented in Fig. 10 coincide with those included in Section V-B. As shown in Fig. 15, the settling times of dc-link voltage vdc and line current is are less than 3 ms. Nevertheless, the results show that the computational

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Fig. 9. Spectrum of phase 1. (a) Load current. (b) Source current after compensation.

Fig. 11. Steady-state response of SAPF with nonlinear load unbalances.

Fig. 10. Dynamic response of SAPF under varying distorted nonlinear load conditions.

Fig. 12. Spectrum of load currents and source currents after compensation for asymmetrical load conditions.

control delay compensation possesses good dynamic response for both harmonic current compensation and dc-link voltage regulation. It is important to note that the THD of the supply currents are largely reduced, which is well below the IEEE-519 standard requirement. C. Compensation of Nonactive Load Currents With the adopted control algorithm, this test aims to evaluate the capability of the SAPF to compensate for nonactive load currents. To carry this out, the load consists of a three-phase diode rectier, followed by inductor LL = 10 mH in series with a resistor RL = 16 , and a single-phase diode rectier, followed by inductor LL = 10 mH in series with a resistor RL = 40 . The single-phase rectier is connected between

phases 1 and 2, as shown in Fig. 1. The supply voltage vs1 , unbalanced three-phase load currents iL123 , supply currents is123 , SAPF currents ic123 , and dc bus voltage of the SAPF are shown in Fig. 11. One notes that these supply currents after compensation are balanced. Furthermore, spectrum analysis of load and line currents depicted in Fig. 12 indicates that the SAPF can largely improve the THD of the supply currents while feeding unbalanced load. The THD of the source currents is123 are reduced from 15.91%, 22.12%, and 25.76% before compensation to 1%, 1.27%, and 1.27% after compensation, respectively. These results conrm the capability of the algorithm to balance the line currents while simultaneously compensating for reactive and harmonic load current components. The waveforms presented in this section and showed in Figs. 11 and 12

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TABLE II M AIN H ARMONIC C ONTENTS OF S IMULATED S OURCE C URRENTS

Fig. 14. Spectrum of the supply current in phase 1. (a) Before compensation. (b) After compensation. Fig. 13. Steady-state response of the SAPF with diode rectier load.

coincide with those included in Figs. 16 and 17 of Section V-C. The harmonic contents (peak) of the main load and source currents, along with %THD, are shown in Table II. V. E XPERIMENTAL R ESULTS The nonlinear control method is tested on a laboratory prototype of an SAPF. The SAPF consists of six insulated gate bipolar transistor (IGBT) modules GA100TS60U of infrared. The peak load power is 3.5 kW. The maximum rating of the SAPF is 1 kVA. The real-time performance of the SAPF system with developed algorithm was tested in the laboratory for several different operating conditions, such as steady-state and transient conditions, and under unbalanced nonlinear load. The experimental results are presented in Figs. 1317 and discussed in the succeeding sections. A. Steady-State Performance of the Nonlinear Control Scheme With SAPF Harmonic Load Current Compensation Experimental results aimed to validate the simulation results of the nonlinear control have been obtained for steady-state
Fig. 15. Dynamic response of the SAPF under varying distorted nonlinear load conditions.

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Fig. 16.

Steady-state response of the SAPF for asymmetrical load conditions.

bus voltage, phase-1 supply, load, and lter currents. The load current is abruptly decreased from 7.85 A (rms) to 3.8 A (rms) and then increased from 3.8 A (rms) to 7.85 A (rms). As viewed from the experimental results, the changeover from one operating condition to the other is quite smooth, therefore maintaining excellent compensation. The increase in load current will immediately be supplied from the SAPF, resulting in decreased energy storage of the dc bus capacitor. This reduction in the dc bus voltage of the SAPF will activate the dc voltage controller to increase the supply current. This increased source current tries to restore the stored energy of the capacitor in addition to increased load active power. Within one cycle, the supply current settles to steady-state value. Similarly, the reverse action takes place as the load current decreases from 7.85 A (rms) to 3.8 A (rms), causing the dc link to slightly increase, as shown in Fig. 15. This will momentarily decrease the supply current to reduce the capacitor voltage at a set reference value. Within one cycle of ac source, the supply current settles to steady-state value. Since the corrective action of the voltage controller is taken within a half cycle of the ac mains, it results in fast response of the scheme. It was observed that this dip in the dc-link voltage was about 7 V for 200-V dc link (3.5%). Nevertheless, the conditions previously discussed prove that the APF system compensates the reactive and harmonic load current components during steady state, as well as under transient operating conditions.

C. Compensation of Reactive, Unbalanced, and Harmonic Load Current Components The SAPF consists of six IGBTs (S1 , S2 S3 , S1 , S2 , S3 ). The load consists of three-phase and single-phase diode rectiers, followed by inductor LL in series with a resistor RL . The single-phase rectier is connected between phases 1 and 2 by closing the switch SW, as shown in Fig. 1. The global load currents containing asymmetrical components are shown in Fig. 16. This gure illustrates the supply voltages vs1 of phase 1, the unbalanced three phase load currents iL123 , the supply currents is123 , and the SAPF currents ic123 . One can note that supply currents after compensation are balanced. The spectral analysis of load and line currents is performed, using Fluke Model 41B Power Harmonics Analyzer. The results depicted in Fig. 17 shows the ability of the SAPF to improve the THD of the supply currents with unbalanced load. The rms source currents before compensation was Is1 = 4.31 A, Is2 = 4.64 A, and Is3 = 3.23 A; therefore, after compensation, these currents become equal to Is1 = Is2 = Is3 = 4.56 A. The THD of the source currents is123 are reduced, respectively, from 13.6%, 14%, and 21% before compensation to 2.9%, 3%, and 2.3% after compensation. The SAPF system works as expected. The compensated source currents, as viewed from Fig. 16, are sinusoidal and close to balanced. The lter currents suggest that the SAPF system inject different currents to compensate nonactive load current demands in each phase. This proves that the control approach with the SAPF system can quite effectively handle the most critical situation in a power distribution system.

Fig. 17. Harmonic spectra of load currents and supply currents.

operation mode, as shown in Fig. 13. These results show the effectiveness of the SAPF to compensate harmonic currents created by a three-phase diode rectier type of load. In this gure, the supply voltage vs1 in phase 1, the load currents iL123 , the supply currents is123 , and the compensating currents of the SAPF ic123 are presented. The harmonic spectrums of load and source currents have been given in Fig. 14(a) and (b), respectively. The compensated source current prole shows that the SAPF was effectively working, thus reducing the source current THD from 26% to 3.1%. This signicant reduction occurred when the utility voltage measured THD is 8.8%; consequently, the SAPF system is able to reduce the source current THD (3.1%) well below the IEEE-519 standard requirement. B. Dynamic Performance of the Active Power Filter Fig. 15 shows the transient response of the SAPF during sudden variations in nonlinear load. It also shows the SAPF dc-

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VI. C ONCLUSION The nonlinear control algorithm of an SAPF has been implemented to enhance its response for compensation of nonactive load currents. The nonlinear control technique of the SAPF has been designed, which is based on two inner current loops and an outer dc bus voltage regulator loop. It has been observed that there is no interaction between inner and outer loops in addition to good performance in both steady-state and transient operations. Simulation and experimental results have validated the nonlinear control approach of the SAPF. It has been shown that the system has 1.5 cycles for the outer voltage loop and 0.5 cycles for the inner current loop and is able to keep the THD of the supply current below the limits specied by the IEEE519 standard. The obtained results have demonstrated the high performance of the SAPF. R EFERENCES
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Salem Rahmani (M06) was born in Tunisia. He received the B.Sc.A. and M.Sc.A. (electrical) degrees and the Specialized Scientic Studies Certicate (CESS) from the High School of Sciences and Technologies of Tunis (ESSTT), Tunis, Tunisia, in 1992, 1995, and 2001, respectively, and the Ph.D. degree from the National Engineering School of Tunis (ENIT), Tunis, in 2004. In September 2002, he was an Assistant Professor with the Department of Electrical Engineering, High Institute of Medical Technologies of Tunis (ISTMT), Tunis. Since the elaboration of his Ph.D. degree, he has been a Member of the Research Group in Power Electronics and Industrial Control (GREPCI), cole de Technologie Suprieure, University of Qubec, Montreal, QC, Canada. His research interests are power quality, active lters, and resonant converters, including power converter topology, modeling, and control aspects.

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Nassar Mendalek (M00) was born in Lebanon. He received the B.E. degree in electrical engineering from St-Joseph University, Beirut, Lebanon, in 1983 and the M.S. and Ph.D. degrees from the Ecole de Technologie Suprieure, Montreal, QC, Canada, in 1997 and 2003, respectively. From 1983 to 1990, he was with the Lebanese Telecommunication Ministry as a Design and Support Engineer. From 1995 to 2004, he was with the Research Group in Power Electronics and Industrial Control (GREPCI), Ecole de Technologie Suprieure, where he was involved in teaching and research activities related to power electronics. Since 2004, he has been an Assistant Professor with the Department of Electrical, Computer and Communication Engineering, Notre Dame University, Louaize, Lebanon. He teaches courses in power electronics, energy conversion, and analog and digital electronics. His research interests include power quality, renewable energy, and the modeling and control aspects of power converter topologies.

Kamal Al-Haddad (S82M88SM92F07) was born in Beirut, Lebanon, in 1954. He received the B.Sc.A. and M.Sc.A. degrees from the University of Qubec Trois-Rivires, Trois-Rivires, QC, Canada, in 1982 and 1984, respectively, and the Ph.D. degree from the Institut National Polythechnique, Toulouse, France, in 1988. From June 1987 to June 1990, he was a Professor with the Engineering Department, Universit du Qubec Trois Rivires. Since June 1990, he has been a Professor with the Electrical Engineering Department, cole de Technologie Suprieure (ETS), Montreal, QC, where he has been the holder of the Canada Research Chair in Electric Energy Conversion and Power Electronics since 2002. He has supervised more than 60 Ph.D. and M.Sc.A. students working in the eld of power electronics. From 1992 to 2003, he was the Director of the graduate study programs at the ETS. He is a Consultant and has established a very solid link with many Canadian industries working in the eld of power electronics, electric transportation, aeronautics, and telecommunications. He is the Chief of the ETSBombardier Transportation North America division, which is a joint industrial research laboratory on electric traction system and power electronics. He is also a coauthor of the Power System Blockset software of Matlab. He has coauthored more than 250 transactions and conference proceeding papers. His research interests are highly efcient static power converters; harmonics and reactive power control using hybrid lters; and switch-mode and resonant converters, including the modeling, control, and development of prototypes for various industrial applications in electric traction, power supply for drives, telecommunication, etc. Dr. Al-Haddad is a Fellow Member of the Canadian Academy of Engineering and a Life Member of the Circle of Excellence of the University of Quebec. He is active in the IEEE Industrial Electronics Society, where he is the Vice President for Publication, an AdCom member, and serves as an Associate Editor for the IEEE T RANSACTIONS ON I NDUSTRIAL E LECTRONICS. He was the recipient of the Outstanding Researcher Award from ETS in 2000.