Introduction To Tools Of VHDL

For simulating any VHDL program we have to first open FPA Advantage 8.1 PS from the desktop. This will open a window of the program called as Design Manager window. Design Manger is the main interface of the program. We can create new project, open existing project, set preferences for the program, change settings using this interface, etc.

From the window that appears on our screen we select File --- New --- Project. With the help of this window we can give the name of the project for our VHDL program.

In the new opened window titled Create New Project, enter a name for your project in the Name of new project: filed and click Next.

On the following window, click Next again. This window gives us the summary of the project information we have just mentioned.

In the next window, select the radio button next to Create new design files and then click Finish.

After we open new file for simulating VHDL program the computer asks us about what type of program we want to design and its categories and also File Type. In our next window that is given below we select VHDL File from the given categories and COMBINED file from the File Types. By selecting the Combined file type we are selecting or including both the ENTITY and ARCHITECTURE in our VHDL program.

After we declare that we need both the Entity and Architecture field we need to also declare their corresponding names. Thus in our next window we declare the name of the Entity and Architecture.

After we assign the name of Entity and the Architecture the window for writing the program is opened and we have to write the VHDL Dataflow code for the given program as it is shown in the below screen.

Code Window

After done with the coding, save the code by clicking File and then Save.

In order to compile the program, click the icon in the task bar as shown below:

This also opens log on window which gives us information about the complete compilation of program. In the next window titled as Start ModelSim, click OK to proceed with the simulation.

This will open the ModelSim simulator window with the object page also as shown.

Model Sim Simulator

The object screen tells us about the inputs and output terminal we have used in our VHDL code. Press and hold
the Ctrl key on the keyboard and click every literal inside the Objects pane.

In the taskbar, click Add, then click Wave and then select Signals in Design.

This will open a new window, Wave showing the timeline and all the input/output literals on the left.

Result Window
Right click at all input literals and select Force to force the value of the input only. In the next dialogue box, enter the value 0 or 1 in the Value field and click OK.

Repeat the last two steps for other input signals as well. Then click the icon as shown below to obtain the timing diagram as output to your digital design. After Forcing the required value for each input signal, click Run button as shown below to obtain the corresponding timing diagram.

Result Window

ELECTRONICS AND COMMUNICATION ENGINEERING ASET(NOIDA)

DCS-II LAB RECORD

Submitted to Dr.Pradeep Kumar(Faculty ASET)

Submitted by Rohit Panwar 5ECE-1 A2305109071

INDEX

S. No

Name of the Experiment

Date of Experiment

Signature

EXPERIMENT No. 2
Aim:
To implement VHDL code for Half Adder, Full Adder, Half Subtractor and Full Subtractor.

Apparatus Required:

Theory:
A) Half Adder The half adder is an example of a simple, functional digital circuit built from two logic gates. It accepts two binary digits on its inputs i.e. A and B and produce two binary digits outputs, a sum(S) and a carry (C). Mathematically, the equations are represented as: Sum = A XOR B Carry = A AND B eqn.(2.1) eqn.(2.2)

The half adder is an example of a simple, functional digital circuit built from two logic gates
Logic Diagram:

Figure.(2.1)

Truth Table:

Table.(2a) A 0 0 1 1 B 0 1 0 1 S 0 1 1 0 C 0 0 0 1

B) Full Adder The full adder is usually a component in a cascade of adders , which adds 8,16,32 etc. binary numbers. The full adder accepts two input bits (A and B) and an input carry( Cin ) and generates a sum(S) and an output carry(Cout). Mathematically, the equations are represented as: Sum= A XOR B XOR Cin Carry = AB + BCin + ACin eqn.(2.3) eqn.(2.4)

Logic Diagram:

Figure.(2.2)

Truth table: Table.(2b) A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1 Cout 0 0 0 1 0 1 1 1

C) Half Subtractor The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow). Mathematically, the equations are represented as: Difference= A XOR B Borrow = A'B Logic Diagram: eqn.(2.5) eqn.(2.6)

Figure.(2.3)

Truth Table: Table.(2c) X 0 0 1 1 Y 0 1 0 1 D 0 1 1 0 B 0 1 0 0

D) Full Subtractor The full-subtractor is a combinational circuit which is used to perform subtraction of three bits. The Full Subtractor accepts two input bits (A and B) and an borrow( BORin ) and generates a Difference(D) and an output borrow(BORout).

Mathematically, the equations are represented as: Difference = A XOR B XOR BORin Borrow = A'BORin + A'B + B BORin

Logic Diagram:

Figure.(2.4)

Truth table: Table.(2d) A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 BORin 0 1 0 1 0 1 0 1 D 0 1 1 0 1 0 0 1 BORout 0 1 1 1 0 0 0 1

A)VHDL code for Half Adder

1)Using Dataflow Modeling

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY halfadder IS port(a,B: IN std_logic; Sum,Carry: OUT std_logic); END ENTITY halfadder; -ARCHITECTURE half_adder_A OF halfadder IS BEGIN Sum<= A XOR B; Carry<= A AND B; END ARCHITECTURE half_adder_A;

2)Using Behavioral Modeling

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY halfadder IS port(A,B: IN std_logic; Sum,Carry: OUT std_logic); END ENTITY halfadder; -ARCHITECTURE half_beh OF halfadder IS BEGIN process (A,B) begin Sum<= A XOR B; Carry<= A AND B; end process ; END ARCHITECTURE half_beh;

Output:

Result window of Half Adder

B) VHDL code for Full Adder

1)Using Dataflow Modeling LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY fulladder IS port(A,B,C:IN std_logic; Sum,Carry:OUT std_logic); END ENTITY fulladder; -ARCHITECTURE fulladder_A OF fulladder IS BEGIN Sum <= A XOR B XOR C; Carry<= (A AND B) OR (B AND C) OR (A AND C); END ARCHITECTURE fulladder_A;

2)Using Behavioral Modeling

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY fulladder IS port(A,B,C: IN std_logic; Sum,Carry: OUT std_logic); END ENTITY fulladder; -ARCHITECTURE fulladder_beh OF fulladder IS BEGIN process(A,B,C) Variable v1,v2,v3:std_logic; BEGIN Sum <= A XOR B XOR C; v1:= A AND B; v2:= B AND C; v3:= A AND C; Carry<= v1 OR v2 OR v3; end process; END ARCHITECTURE fulladder_beh; Output:

Result window of Full Adder

C) VHDL code for Half Subtractor

1)Using Dataflow Modeling LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY halfsub IS port(A,B:IN std_logic; Borrow, Diff:OUT std_logic); END ENTITY halfsub; -ARCHITECTURE halfsub_A OF halfsub IS BEGIN Diff<= A XOR B; Borrow<= (NOT A) AND B; END ARCHITECTURE halfsub_A;

2)Using Behavioral Modeling

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY halfsub IS port(A,B: IN std_logic; Diff,Borrow: OUT std_logic); END ENTITY halfsub; -ARCHITECTURE halfsub_beh OF halfsub IS BEGIN process (A,B) begin Diff<= A XOR B; Borrow<= (NOT A) AND B; end process ; END ARCHITECTURE halfsub_beh;

Output:

Result window of Half Subtrator

C) VHDL code for Full Subtractor

1)Using Dataflow Modeling

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY fullsub IS port(A,B,C: IN std_logic; Diff,Borrow: OUT std_logic); END ENTITY fullsub; -ARCHITECTURE fullsub_A OF fullsub IS BEGIN Diff<=A XOR B XOR C; Borrow<= ((NOT A) AND B) OR ((NOT A) AND C) OR (B AND C); END ARCHITECTURE fullsub_A;

2)Using Behavioral Modeling

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY fullsub IS port(A,B,C: IN std_logic; Diff,Borrow: OUT std_logic); END ENTITY fullsub; -ARCHITECTURE fullsub_beh OF fullsub IS BEGIN process(A,B,C) Variable v1,v2,v2: std_logic; BEGIN Diff<= A XOR B XOR C; v1:= (NOT A) AND B; v2:= (NOT A) AND C; v3:= B AND C; Borrow<= v1 OR v2 OR v3; end process; END ARCHITECTURE fullsub_beh; Output:

Result window of Full Subtrator

Structural coding
1) Half Adder library ieee; use ieee.std_logic_1164.all; entity andGate is port( A, B : in std_logic; F : out std_logic); end andGate; architecture func of andGate is begin F <= A and B; end func; entity xorGate is port( A, B : in std_logic; F : out std_logic); end xorGate; architecture func of xorGate is begin F <= A xor B; end func; entity halfAdder port( A, B : in std_logic; sum, Cout : out std_logic); end halfAdder; architecture halfAdder of halfAdder is component andGate port( A, B : in std_logic; F : out std_logic); end component; component xorGate port( A, B : in std_logic; F : out std_logic); end component; begin G1 : xorGate port map(A, B, sum); G2 : andGate port map(A, B, Cout); end halfAdder;

Result:
VHDL code for Half Adder, Full Adder, Half Subtrator and Full Subtrator were implemented and their simulation were tested.