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EXPERIMENT NO.

9
Aim
To implement VHDL code for Binary to Gray Code Converter.

Tool required
Mentor Graphics FPGA advantage 8.1ps Model sim 6.3a

Theory
Gray Code This is a variable weighted code and is cyclic. This means that it is arranged so that every transition from one value to the next value involves only one bit change. The gray code is sometimes referred to as reflected binary, because the first eight values compare with those of the last 8 values, but in reverse order. The gray code is often used in mechanical applications such as shaft encoders. Converting Gray Code to Binary A. write down the number in gray code B. the most significant bit of the binary number is the most significant bit of the gray code C. add (using modulo 2) the next significant bit of the binary number to the next significant bit of the gray coded number to obtain the next binary bit D. repeat step C till all bits of the gray coded number have been added modulo 2 the resultant number is the binary equivalent of the gray number Converting Binary to Gray A. write down the number in binary code B. the most significant bit of the gray number is the most significant bit of the binary code

C. add (using modulo 2) the next significant bit of the binary number to the next significant bit of the binary number to obtain the next gray coded bit D. repeat step C till all bits of the binary coded number have been added modulo 2 the resultant number is the gray coded equivalent of the binary number

Conversion Table Decimal Binary Grey 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000

Table.(9.1)

VHDL code for Binary To Grey Code Converter


LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY BTG1 IS port (B0, B1, B2, B3: IN STD_LOGIC; G0, G1, G2, G3: OUT STD_LOGIC); END ENTITY BTG1; ARCHITECTURE BTG2 OF BTG1 IS BEGIN PROCESS(B0, B1, B2, B3) BEGIN IF(B0 = '0' AND B1 = '0' AND B2 = '0' AND B3 = '0') THEN G0 <= '0'; G1 <= '0'; G2 <= '0'; G3 <= '0'; ELSIF(B0 = '0' AND B1 = '0' AND B2 = '0' AND B3 = '1') THEN G0 <= '0'; G1 <= '0'; G2 <= '0'; G3 <= '1'; ELSIF(B0 = '0' AND B1 = '0' AND B2 = '1' AND B3 = '0') THEN G0 <= '0'; G1 <= '0'; G2 <= '1'; G3 <= '1'; ELSIF(B0 = '0' AND B1 = '0' AND B2 = '1' AND B3 = '1') THEN G0 <= '0'; G1 <= '0'; G2 <= '1'; G3 <= '0'; ELSIF(B0 = '0' AND B1 = '1' AND B2 = '0' AND B3 = '0') THEN G0 <= '0'; G1 <= '1'; G2 <= '1'; G3 <= '0'; ELSIF(B0 = '0' AND B1 = '1' AND B2 = '0' AND B3 = '1') THEN G0 <= '0'; G1 <= '1'; G2 <= '1'; G3 <= '1'; ELSIF(B0 = '0' AND B1 = '1' AND B2 = '1' AND B3 = '0') THEN G0 <= '0'; G1 <= '1'; G2 <= '0'; G3 <= '1'; ELSIF(B0 = '0' AND B1 = '1' AND B2 = '1' AND B3 = '1') THEN

G0 <= '0'; G1 <= '1'; G2 <= '0'; G3 <= '0'; ELSIF(B0 = '1' AND B1 = '0' AND B2 = '0' AND B3 = '0') THEN G0 <= '1'; G1 <= '1'; G2 <= '0'; G3 <= '0'; ELSIF(B0 = '1' AND B1 = '0' AND B2 = '0' AND B3 = '1') THEN G0 <= '1'; G1 <= '1'; G2 <= '0'; G3 <= '1'; END IF; END PROCESS; END ARCHITECTURE BTG2;

Output:

Result Window of Binary To Grey Code Converter

Result
The VHDL code for Binary To Grey Code Converter were implemented and simulated successfully.