EXPERIMENT NO.

5
Aim
To implement VHDL code for 2 bit and 4 bit magnitude comparator.

Tool required
Mentor Graphics FPGA advantage 8.1ps Model sim 6.3a

Theory
A digital comparator or magnitude comparator is a hardware electronic device that takes two numbers as input in binary form and determines whether one number is greater than, less than or equal to the other number. Comparators are used in a central processing units (CPU) and microcontrollers. Examples of digital comparator include the CMOS 4063 and 4585 and the TTL 7485 and 74682-'89.

A magnitude comparator is a combinational circuit that compares two numbers A & B to determine whether: A > B, or

A = B, or A<B Inputs First n-bit number A Second n-bit number B Outputs 3 output signals (GT, EQ, LT), where: 1. GT = 1 IF A > B 2. EQ = 1 IF A = B 3. LT = 1 IF A < B GT = Greater than; EQ = Equal To; LT = Less Than

2 bit magnitude comparator

A 2 bit magnitude comparator consists of 2 inputs of 2 bit each and 3 outputs.

Truth Table A1 A0 B1 B0 A>B A=B A<B 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0

1 1 1 1 1 Logic Equation

0 1 1 1 1

1 0 0 1 1

1 0 1 0 1

0 1 1 1 0

0 0 0 0 1

1 0 0 0 0

Table(5.1a)

A<B = A1B1 + A1A0B0 + A0B1B0 A>B = A1B1 + A0B1B0 + B0A1A0 A=B = A0B0 + A1A0B1B0 + A1A0B1B0

4 bit magnitude comparator

A 2X4 decoder consists of 2 inputs of f bit each and 3 outputs. Consider two 4-bit binary numbers A and B such that A = A3A2A1A0 B = B3B2B1B0 Here each subscript represents one of the digits in the numbers.
Equality

The binary numbers A and B will be equal if all the pairs of significant digits of both numbers are equal, i.e., A3 = B3, A2 = B2, A1 = B1 and A0 = B0 Since the numbers are binary, the digits are either 0 or 1 and the boolean function for equality of any two digits Ai and Bi can be expressed as . xi is 1 only if Ai and Bi are equal.

For the equality of A and B, all xi variables (for i=0,1,2,3) must be 1. So the quality condition of A and B can be implemented using the AND operation as (A = B) = x3x2x1x0 The binary variable (A=B) is 1 only if all pairs of digits of the two numbers are equal.
Inequality

In order to manually determine the greater of two binary numbers, we inspect the relative magnitudes of pairs of significant digits, starting from the most significant bit, gradually proceeding towards lower significant bits until an inequality is found. When an inequality is found, if the corresponding bit of A is 1 and that of B is 0 then we conclude that A>B. This sequential comparison can be expressed logically as:

(A>B) and (A < B) are output binary variables, which are equal to 1 when A>B or A<B respectively.

VHDL code for 2 bit magnitude comparator

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY comp IS port(a1,a0,b1,b0:in std_logic; y0,y1,y2:out std_logic); END ENTITY comp; ARCHITECTURE comp_data OF comp IS BEGIN process(a0,a1,b0,b1) begin if(a1>b1) then y0<='0'; y1<='1'; y2<='0'; elsif(b1>a1) then y0<='1'; y1<='0'; y2<='0'; elsif(a1=b1) then if(a0>b0) then y0<='0';

y1<='1'; y2<='0'; elsif(b0>a0) then y0<='1'; y1<='0'; y2<='0'; elsif(a0=b0) then y0<='0'; y1<='0'; y2<='1'; end if; end if; end process; END ARCHITECTURE comp_data; Output:

Result window of 2 bit magnitude comparator

VHDL code for 4 bit magnitude comparator

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY MAG4BH IS

PORT(A0,A1,A2,A3,B0,B1,B2,B3: IN STD_LOGIC; X,Y,Z:OUT STD_LOGIC); END ENTITY MAG4BH; ARCHITECTURE MAG4BH_ARCH OF MAG4BH IS BEGIN PROCESS(A0,A1,A2,A3,B0,B1,B2,B3) BEGIN IF(A0>B0) THEN Z<='1'; X<='0'; Y<='0'; ELSIF(A0<B0) THEN Z<='0'; X<='0'; Y<='1'; ELSIF(A0=B0) THEN IF(A1>B1) THEN Z<='1'; X<='0'; Y<='0'; ELSIF(A1<B1) THEN Z<='0'; X<='0'; Y<='1'; ELSIF(A1=B1)THEN IF(A2>B2) THEN Z<='1'; X<='0'; Y<='0'; ELSIF(A2<B2) THEN Z<='0'; X<='0'; Y<='1'; ELSIF(A2=B2) THEN IF(A3>B3) THEN Z<='1'; X<='0'; Y<='0'; ELSIF(A3<B3) THEN Z<='0'; X<='0'; Y<='1'; ELSE Z<='0'; X<='1'; Y<='0'; END IF;

END IF; END IF; END IF; END PROCESS; END ARCHITECTURE MAG4BH_ARCH; Output:

Result window of 4 bit magnitude Comparator

Result
The VHDL code for 2 bit and 4 bit magnitude comparators were implemented and simulated successfully.