Code No: RR411403 Set No.

1
IV B.Tech I Semester Regular Examinations, November 2007
COMPUTER ORGANISATION
(Mechatronics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. (a) What is an overflow? Explain with an example.

(b) Explain about PCI in a single-processor system with relevant block diagram.
[8+8]

2. (a) What do you mean by a variable length instruction? Expalin with an example.
(b) Assume an instruction set that uses a fixed 16 bit instruction length. Operand
specifies are 6 bits in length. There are K two operand instructions and L
zero operand instructions. What is the maximum number of one operand
instructions can be supported? [8+8]

3. (a) Write the sequence of micro-operations required for the single internal bus
structure to add a number to the AC when the number is
i. An immediate operand
ii. A direct address operand
iii. An indirect address operand
(b) When an interrupt cycle occurs ? What are the micro-operations required to
carryout this cycle ? Explain. [8+8]

4. (a) Explain the variety of techniques available for sequencing of microinstructions

based on the format of the address information in the microinstruction.
(b) Hardwired control unit is faster than microprogrammed control unit. Justify
this statement [10+6]

5. Explain the one dimensional and two dimensional RAM organizations in detail:
[16]

6. Explain the follwoing in detail:

(a) Cache types

(b) Performance of Cache memory. [8+8]

7. Discuss the following

(a) Multi-bus
(b) I/O channel
(c) I/O modules
(d) I/O processor [4+4+4+4]

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Code No: RR411403 Set No. 1
8. (a) A DMA controller transfers 16-bit words to memory using cycle stealing. The
words are assembled from a device that transmits characters at a rate of 2400
characters per second. The CPU is fetching and executing instructions at an
average rate of one million instructions per second. By how much will the
CPU be slowed down because of the DMA transfer?
(b) What are Bus arbitration schemes? Explain. [8+8]

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Code No: RR411403 Set No. 2
IV B.Tech I Semester Regular Examinations, November 2007
COMPUTER ORGANISATION
(Mechatronics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) What are various bus configurations and bus data transfer types? Explain
them.
(b) Represent the binary equivalent of -8 in 3 different ways using register of 12
bits. [10+6]

2. (a) What are the different data transfer operations performed on machine? De-
scribe each one of them.
(b) Describe different indirect addressing techniques with examples. [8+8]

3. (a) Draw the diagram of a simple CPU with a single accumulator showing data
paths and control signals. Use this diagram to explain the functioning of a
control unit.
(b) Write the sequence of micro-operations required to add a value from memory
to the AC. [8+8]

4. Consider an accumulator based CPU with the following eight one address instruc-
tions. LOAD X, STORE X, ADD X, AND X, JMP X, JMPZ X, CMPL, (Com-
plement Accumulator), and RSHIFT. Give fetch and execute cycle operations and
identify the necessary control signals to be generated for the above instructions by
a micro programmed control unit. [16]

5. (a) What is the use of associative memory

(b) Explain the direct mapping and set-associative address mapping techniques
in detail. [8+8]

6. (a) What are the advantages of paging?

(b) Explain how the logical address can be converted into physical address in a
paging system? [8+8]

7. What is Asynchronous Data Transfer? Explain various methods of asynchronous

data transfer with timing diagrams. [16]

8. Why are read and write control lines in a DMA controller bi-directional? Under
what condition and for what purpose are they used as inputs? Under what condition
and for what purpose are they used as outputs? Explain. [16]

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Code No: RR411403 Set No. 3
IV B.Tech I Semester Regular Examinations, November 2007
COMPUTER ORGANISATION
(Mechatronics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Discuss about I E E E standard for binary floating-point arithmetic.

(b) Discuss about floating-point division with a flow chart. [8+8]

2. (a) Describe the various addressing techniques with examples.

(b) List out the characteristics of RISC architectures. [10+6]

3. With a neat diagram showing the pin layout of 8085, explain in brief the function
of each pin. [16]

4. (a) List and explain the explicit microinstruction address generation techniques.
(b) Explain briefly the classification of microinstructions.
(c) Compare horizontal and vertical microinstructions. [6+6+4]

5. (a) Compare SRAM with DRAM

(b) Why are the multilevel memories used in a computer system ? [8+8]

6. Explain the follwoing in detail:

(a) Cache types

(b) Performance of Cache memory. [8+8]

7. (a) Differentiate between various memory mapped I/O.

(b) Differentiate between strobe control and hand shaking.
(c) Differentiate between synchronous and asynchronous Data Transfer. [6+5+5]

8. (a) What is Cycle Stealing mode of data transfer? Where is it used. Explain.
(b) What is a masked interrupt? What is the advantage of masking? [8+8]

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Code No: RR411403 Set No. 4
IV B.Tech I Semester Regular Examinations, November 2007
COMPUTER ORGANISATION
(Mechatronics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Discuss about general purpose registers and memory formats of I A S com-
puter.
(b) What are various ways of representing negative numbers. [8+8]

2. (a) Describe different data transfer and arithmetic instructions with examples
(b) What is normalization .How normalization is performed in floating point ar-
chitecture. [8+8]

3. Define the term addressing mode. Also explain different addressing modes available
in 8085 with an example for each. [16]

4. Consider an accumulator based CPU with the following eight one address instruc-
tions. LOAD X, STORE X, ADD X, AND X, JMP X, JMPZ X, CMPL, (Com-
plement Accumulator), and RSHIFT. Give fetch and execute cycle operations and
identify the necessary control signals to be generated for the above instructions by
a micro programmed control unit. [16]

5. Explain the one dimensional and two dimensional RAM organizations in detail:
[16]

6. (a) What do you mean by virtual memory?

(b) Explain the demand paging technique in detail. [8+8]

7. What is Asynchronous Data Transfer? Explain various methods of asynchronous

data transfer with timing diagrams. [16]

8. (a) Describe the centralized and distributed bus arbitration schemes.

(b) Discuss the need of interface circuits. [8+8]

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