Code No: RR220501 Set No.

1
II B.Tech II Semester Supplimentary Examinations, Aug/Sep 2007
COMPUTER ORGANIZATION
( Common to Computer Science & Engineering, Information Technology,
Computer Science & Systems Engineering and Electronics & Computer
Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) What is instruction Cycle ?

(b) Elaborate the characteristics of a hypothetical machine
(c) What do you mean by hardwired program? [6+6+4]
2. (a) What is BCD representation. List the advantages of it.
(b) Convert the following binary numbers to decimal and octal forms
i. 101101110
ii. 1.011101 [8+8]
3. (a) Discuss various aspects of instruction set design.
(b) Explain about various types of data on which machine instructions operate.
[10+6]
4. (a) List the characteristics of superscalar processors and contrast it with CISC
processors.
(b) Explain the instruction execution characteristics of RISC processors.
(c) What is semantic gap problem? [6+6+4]
5. (a) Discuss about principles of cache memory.
(b) Elaborate on elements of cache memory.
(c) Explain the purpose of replacement algorithms [6+5+5]
6. (a) List the hardware events that occur after an I/O device completes an I/O
operation in interrupt driven I/O.
(b) List and explain the interrupt modes of Intel 8259A interrupt controller.
[8+8]
7. (a) List and explain the functions of control unit
(b) What is sequencing logic unit? Explain it’s purpose. [8+8]
8. (a) Differentiate between miltiprocessors and multicomputers.
(b) Discuss about instruction pipeline. [7+9]

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Code No: RR220501 Set No. 2
II B.Tech II Semester Supplimentary Examinations, Aug/Sep 2007
COMPUTER ORGANIZATION
( Common to Computer Science & Engineering, Information Technology,
Computer Science & Systems Engineering and Electronics & Computer
Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) How optional signal lines for PCI are functionally grouped .
(b) Explain typical server system using PCI configuration. [8+8]

2. (a) What is BCD representation. List the advantages of it.

(b) Convert the following binary numbers to decimal and octal forms
i. 101101110
ii. 1.011101 [8+8]

3. List branch oriented, load/store and floating point operation of power PC with
description [16]

4. (a) Give weighted relative dynamic frequency of HLL operations

(b) What do you mean by dynamic percentage of operands?
(c) Discuss about overlapping register windows [6+5+5]

5. (a) Differentiate between single versus two-level caches.

(b) Elaborate on Pentium Cache Organization. [8+8]

6. (a) List the hardware events that occur after an I/O device completes an I/O
operation in interrupt driven I/O.
(b) List and explain the interrupt modes of Intel 8259A interrupt controller.
[8+8]

7. (a) List and explain the functions of control unit

(b) What is sequencing logic unit? Explain it’s purpose. [8+8]

8. (a) Give a summary of arithmetic and logical operations that are defined for the
vector architecture.
(b) What is cache coherence problem. Discuss about different cache coherance
approches. [8+8]

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Code No: RR220501 Set No. 3
II B.Tech II Semester Supplimentary Examinations, Aug/Sep 2007
COMPUTER ORGANIZATION
( Common to Computer Science & Engineering, Information Technology,
Computer Science & Systems Engineering and Electronics & Computer
Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Explain the purpose and merits of interrupts.

(b) Draw and explain the instruction cycle with interrupts.
(c) What is interrupt handler? Explain its purpose. [6+6+4]
2. (a) What do you mean by improper storage of floating point numbers. Explain
with an example.
(b) What is the range of real numbers represented in normalized floating point
representation in a 6 digit register. [8+8]
3. (a) What is big-endian and little-endian address mapping
(b) List points favoring big-endian and little-endian styles.
(c) What is bit ordering? [6+6+4]
4. (a) Explain about the machine state register.
(b) List the characteristics of CISC and RISC processors [8+8]
5. (a) Explain the operation of a static RAM cell.
(b) Explain the internal organization of 1M×1 dynamic memory chip.
(c) How should you build 64K×8 memory module using 16K×1 static memory
chips. [4+6+6]
6. (a) What is multiple-platter disk.
(b) Differentiate between fixed and movable head disks.
(c) Define ‘disk access time’, ‘seek time’ and ‘rotational latency’.
[5+5+6]
7. Discuss about horizontal and vertical instruction formats. Also differentiate be-
tween horizontal and vertical instruction formats. [16]
8. (a) Discuss about addressing modes sutiable for a pipelined processor.
(b) Differentiate between complex and simple addressing modes in a pipeline
(c) What is multiple execution unit. Explain their functioning and uses.
[6+4+6]

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Code No: RR220501 Set No. 4
II B.Tech II Semester Supplimentary Examinations, Aug/Sep 2007
COMPUTER ORGANIZATION
( Common to Computer Science & Engineering, Information Technology,
Computer Science & Systems Engineering and Electronics & Computer
Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Differentiate between traditional and high performance bus architectures

(b) List the key elements of bus design. [8+8]

2. (a) Explain about the arithmetic in excess - 3 code.

(b) Discuss about normalized floating point representation [6+10]

3. Discuss various key design issues of an instruction format. [16]

4. (a) Discuss about RISC pipelining with regular instructions

(b) How would you optimize RISC pipelining?
(c) Give reasons for reduction in overall execution rate of RISC processors
[8+4+4]

5. (a) Explain major differences between cache-main and main-secondary memory

hierarchies
(b) Discuss main features and basic structure of caches. [8+8]

6. (a) What is multiple-platter disk.

(b) Differentiate between fixed and movable head disks.
(c) Define ‘disk access time’, ‘seek time’ and ‘rotational latency’.
[5+5+6]

7. (a) Discuss about the evolution of I/O function.

(b) Explain the characteristics of I/O channels. [8+8]

8. (a) Differentiate between miltiprocessors and multicomputers.

(b) Discuss about instruction pipeline. [7+9]

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